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msm: clock-9615: Modify PLL9 (SC_PLL0) usage

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Previously PLL9 was being configured to run at 440MHz
and was also being switched to FSM mode by the 9615
clock driver. The bootchain now configures this PLL
in non-FSM mode and - at runtime - programs the PLL
to run at 440 or 550MHz.

At runtime, detect the rate of PLL9 in the clock
driver and fixup the rate in the pll clock structure
accordingly. Also fixup acpuclock tables to reflect
the rate of the PLL at runtime.

Change-Id: Ib304ce22d1e92affba9f6ea044764160dfcfc484
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
This commit is contained in:
Vikram Mulukutla
2012-01-10 14:19:44 -08:00
committed by Linux Build Service Account
parent f0cfc845b7
commit 01d06b8962
2 changed files with 19 additions and 2 deletions
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13
arch/arm/mach-msm/acpuclock-9615.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -98,6 +98,7 @@ static struct msm_bus_paths bw_level_tbl[] = {
[2] = BW_MBPS(552), /* At least 69 MHz on bus. */
[3] = BW_MBPS(736), /* At least 92 MHz on bus. */
[4] = BW_MBPS(1064), /* At least 133 MHz on bus. */
[5] = BW_MBPS(1536), /* At least 192 MHz on bus. */
};
static struct msm_bus_scale_pdata bus_client_pdata = {
@@ -114,6 +115,7 @@ static struct clkctl_acpu_speed acpu_freq_tbl[] = {
{ 1, 138000, SRC_PLL0, 6, 1, 950000, 1050000, 2 },
{ 1, 276000, SRC_PLL0, 6, 0, 1050000, 1050000, 2 },
{ 1, 384000, SRC_PLL8, 3, 0, 1150000, 1150000, 4 },
/* The row below may be changed at runtime depending on hw rev. */
{ 1, 440000, SRC_PLL9, 2, 0, 1150000, 1150000, 4 },
{ 0 }
};
@@ -324,6 +326,15 @@ static int __init acpuclk_9615_init(struct acpuclk_soc_data *soc_data)
}
}
/* Determine the rate of PLL9 and fixup tables accordingly */
if (clk_get_rate(clocks[SRC_PLL9].clk) == 550000000) {
for (i = 0; i < ARRAY_SIZE(acpu_freq_tbl); i++)
if (acpu_freq_tbl[i].src == SRC_PLL9) {
acpu_freq_tbl[i].khz = 550000;
acpu_freq_tbl[i].bw_level = 5;
}
}
/* Improve boot time by ramping up CPU immediately. */
for (i = 0; acpu_freq_tbl[i].khz != 0; i++)
max_cpu_khz = acpu_freq_tbl[i].khz;

8
arch/arm/mach-msm/clock-9615.c
View File

@@ -1745,7 +1745,7 @@ static void set_fsm_mode(void __iomem *mode_reg)
*/
static void __init reg_init(void)
{
u32 regval, is_pll_enabled;
u32 regval, is_pll_enabled, pll9_lval;
/* Enable PDM CXO source. */
regval = readl_relaxed(PDM_CLK_NS_REG);
@@ -1808,6 +1808,12 @@ static void __init reg_init(void)
} else if (!(readl_relaxed(BB_PLL14_MODE_REG) & BIT(20)))
WARN(1, "PLL14 enabled in non-FSM mode!\n");
/* Detect PLL9 rate and fixup structure accordingly */
pll9_lval = readl_relaxed(SC_PLL0_L_VAL_REG);
if (pll9_lval == 0x1C)
pll9_acpu_clk.rate = 550000000;
/* Enable PLL4 source on the LPASS Primary PLL Mux */
regval = readl_relaxed(LCC_PRI_PLL_CLK_CTL_REG);
writel_relaxed(regval | BIT(0), LCC_PRI_PLL_CLK_CTL_REG);