ARM: vfp: Move exception address fixup into vfphw.S
If the PC on the stack is updated in entry-armv.S, do_undefinstr can get called after the fixup. do_undefinstr does its own fixup, and doing both causes the PC to point to half way through an instruction. Instead, do the fixup in do_vfp, where only the vfp code can get called. Change-Id: I6d966887adc8ed58d88bfe0cb3c0ba29213be488 Signed-off-by: Colin Cross <ccross@android.com>
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@@ -492,8 +492,7 @@ __und_usr:
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blo __und_usr_unknown
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blo __und_usr_unknown
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3: ldrht r0, [r4]
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3: ldrht r0, [r4]
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add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
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add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
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str r2, [sp, #S_PC] @ it's a 2x16bit instr, update
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orr r0, r0, r5, lsl #16
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orr r0, r0, r5, lsl #16 @ regs->ARM_pc
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#else
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#else
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b __und_usr_unknown
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b __und_usr_unknown
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#endif
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#endif
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@@ -10,7 +10,7 @@
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*
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*
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* Basic entry code, called from the kernel's undefined instruction trap.
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* Basic entry code, called from the kernel's undefined instruction trap.
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* r0 = faulted instruction
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* r0 = faulted instruction
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* r5 = faulted PC+4
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* r2 = faulted PC+4
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* r9 = successful return
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* r9 = successful return
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* r10 = thread_info structure
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* r10 = thread_info structure
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* lr = failure return
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* lr = failure return
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@@ -26,6 +26,7 @@ ENTRY(do_vfp)
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str r11, [r10, #TI_PREEMPT]
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str r11, [r10, #TI_PREEMPT]
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#endif
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#endif
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enable_irq
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enable_irq
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str r2, [sp, #S_PC] @ update regs->ARM_pc for Thumb 2 case
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ldr r4, .LCvfp
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ldr r4, .LCvfp
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ldr r11, [r10, #TI_CPU] @ CPU number
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ldr r11, [r10, #TI_CPU] @ CPU number
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add r10, r10, #TI_VFPSTATE @ r10 = workspace
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add r10, r10, #TI_VFPSTATE @ r10 = workspace
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