Merge "qup_i2c: Enabling CORE_ON_EN bit while disabling the QuPE PCLKs" into msm-3.0
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QuIC Gerrit Code Review
commit
1fc478e91a
@@ -33,6 +33,7 @@
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/gpio.h>
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#include <mach/socinfo.h>
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MODULE_LICENSE("GPL v2");
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MODULE_VERSION("0.2");
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@@ -303,6 +304,30 @@ qup_update_state(struct qup_i2c_dev *dev, uint32_t state)
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return 0;
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}
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/*
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* Before calling qup_config_core_on_en(), please make
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* sure that QuPE core is in RESET state.
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*
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* Configuration of CORE_ON_EN - BIT13 in QUP_CONFIG register
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* is only required for targets like 7x27a, where it needs
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* be turned on for disabling the QuPE pclks.
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*/
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static void
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qup_config_core_on_en(struct qup_i2c_dev *dev)
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{
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uint32_t status;
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if (!(cpu_is_msm7x27a() || cpu_is_msm7x27aa() ||
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cpu_is_msm7x25a() || cpu_is_msm7x25aa()))
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return;
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status = readl_relaxed(dev->base + QUP_CONFIG);
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status |= BIT(13);
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writel_relaxed(status, dev->base + QUP_CONFIG);
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/* making sure that write has really gone through */
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mb();
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}
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static void
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qup_i2c_pwr_mgmt(struct qup_i2c_dev *dev, unsigned int state)
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{
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@@ -313,6 +338,7 @@ qup_i2c_pwr_mgmt(struct qup_i2c_dev *dev, unsigned int state)
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} else {
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qup_update_state(dev, QUP_RESET_STATE);
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clk_disable_unprepare(dev->clk);
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qup_config_core_on_en(dev);
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clk_disable_unprepare(dev->pclk);
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}
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}
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