From b54fe5e73ee40112272b8eef11520a1076c44c97 Mon Sep 17 00:00:00 2001 From: Matt Wagantall Date: Wed, 14 Mar 2012 18:41:23 -0700 Subject: [PATCH] msm: pil-gss: Remove GSS QGIC bus workaround from pil_gss_reset_trusted() This workaround is now handled in secure context within the call to pas_auth_and_reset(). Remove the unnecessary code. With recent secure image builds, the accesses performed by the removed code had no effect anyway, since the registers involved are protected behind an XPU. Change-Id: If2c34517e290f44a41980c9812fff1f21e8052b7 Signed-off-by: Matt Wagantall --- arch/arm/mach-msm/pil-gss.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/arch/arm/mach-msm/pil-gss.c b/arch/arm/mach-msm/pil-gss.c index 56599ea45f0..fa4f28cca62 100644 --- a/arch/arm/mach-msm/pil-gss.c +++ b/arch/arm/mach-msm/pil-gss.c @@ -312,22 +312,6 @@ static int pil_gss_reset_trusted(struct pil_desc *pil) if (err) goto halt_port; - if (cpu_is_apq8064() && - ((SOCINFO_VERSION_MAJOR(socinfo_get_version()) == 1) && - (SOCINFO_VERSION_MINOR(socinfo_get_version()) == 0))) { - err = smp_call_function_single(0, cfg_qgic2_bus_access, drv, 1); - if (err) { - pr_err("Failed to configure QGIC2 bus access\n"); - pil_gss_shutdown_trusted(pil); - return err; - } - /* - * On 8064v1.0, pas_auth_and_reset() will not release the A5 - * from reset. Linux must do this after cfg_qgic2_bus_access() - * is called on CPU0. - */ - writel_relaxed(0x0, drv->base + GSS_CSR_RESET); - } return 0; halt_port: