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ASoC: wcd9304: Add driver for Sitar codec.

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Add support for 5 RX and 4 TX Slimbus channel support.
Headphone/Earphone/4 DMIX/2 AMIC and IIR1 support

Change-Id: I1b7ad5e5fd9d87aab80d6533503371e63df8cc0a
Signed-off-by: Asish Bhattacharya <asishb@codeaurora.org>
This commit is contained in:
Asish Bhattacharya
2012-02-15 08:31:52 +05:30
parent b1aeae22ff
commit b86c3477a8
16 changed files with 6345 additions and 90 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/configs/msm8960-perf_defconfig
View File

@@ -301,6 +301,7 @@ CONFIG_MFD_PM8921_CORE=y
CONFIG_MFD_PM8821_CORE=y
CONFIG_MFD_PM8038_CORE=y
CONFIG_MFD_PM8XXX_BATT_ALARM=y
CONFIG_WCD9304_CODEC=y
CONFIG_WCD9310_CODEC=y
CONFIG_REGULATOR_PM8XXX=y
CONFIG_REGULATOR_GPIO=y
@@ -319,6 +320,7 @@ CONFIG_IMX074_ACT=y
CONFIG_OV2720=y
CONFIG_S5K3L1YX=y
CONFIG_MSM_GEMINI=y
CONFIG_S5K3L1YX=y
CONFIG_RADIO_IRIS=y
CONFIG_RADIO_IRIS_TRANSPORT=m
CONFIG_ION=y
@@ -336,8 +338,9 @@ CONFIG_FB_MSM_OVERLAY=y
CONFIG_FB_MSM_OVERLAY0_WRITEBACK=y
CONFIG_FB_MSM_OVERLAY1_WRITEBACK=y
CONFIG_FB_MSM_LVDS_MIPI_PANEL_DETECT=y
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
CONFIG_FB_MSM_WRITEBACK_MSM_PANEL=y
CONFIG_FB_MSM_MIPI_PANEL_DETECT=y
CONFIG_FB_MSM_HDMI_MSM_PANEL=y
CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_SOUND=y
@@ -351,7 +354,6 @@ CONFIG_SND_SOC_MSM8960=y
CONFIG_HID_APPLE=y
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_MICROSOFT=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_SUSPEND=y
CONFIG_USB_EHCI_HCD=y

4
arch/arm/configs/msm8960_defconfig
View File

@@ -297,12 +297,11 @@ CONFIG_PM8921_BMS=y
CONFIG_SENSORS_PM8XXX_ADC=y
CONFIG_THERMAL=y
CONFIG_THERMAL_TSENS8960=y
CONFIG_THERMAL_PM8XXX=y
CONFIG_THERMAL_MONITOR=y
CONFIG_MFD_PM8921_CORE=y
CONFIG_MFD_PM8821_CORE=y
CONFIG_MFD_PM8038_CORE=y
CONFIG_MFD_PM8XXX_BATT_ALARM=y
CONFIG_WCD9304_CODEC=y
CONFIG_WCD9310_CODEC=y
CONFIG_REGULATOR_PM8XXX=y
CONFIG_REGULATOR_GPIO=y
@@ -353,7 +352,6 @@ CONFIG_SND_SOC_MSM8960=y
CONFIG_HID_APPLE=y
CONFIG_HID_MAGICMOUSE=y
CONFIG_HID_MICROSOFT=y
CONFIG_USB=y
CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
CONFIG_USB_SUSPEND=y
CONFIG_USB_EHCI_HCD=y

127
arch/arm/mach-msm/board-8930.c
View File

@@ -42,6 +42,10 @@
#include <linux/gpio_keys.h>
#include <linux/memory.h>
#include <linux/slimbus/slimbus.h>
#include <linux/mfd/wcd9xxx/core.h>
#include <linux/mfd/wcd9xxx/pdata.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/setup.h>
@@ -68,12 +72,6 @@
#include <mach/msm_xo.h>
#include <mach/restart.h>
#ifdef CONFIG_WCD9310_CODEC
#include <linux/slimbus/slimbus.h>
#include <linux/mfd/wcd9xxx/core.h>
#include <linux/mfd/wcd9xxx/pdata.h>
#endif
#include <linux/ion.h>
#include <mach/ion.h>
#include <mach/mdm2.h>
@@ -518,9 +516,9 @@ static void __init msm8930_allocate_memory_regions(void)
msm8930_allocate_fb_region();
}
#ifdef CONFIG_WCD9310_CODEC
#ifdef CONFIG_WCD9304_CODEC
#define TABLA_INTERRUPT_BASE (NR_MSM_IRQS + NR_GPIO_IRQS + NR_PM8921_IRQS)
#define SITAR_INTERRUPT_BASE (NR_MSM_IRQS + NR_GPIO_IRQS + NR_PM8921_IRQS)
/* Micbias setting is based on 8660 CDP/MTP/FLUID requirement
* 4 micbiases are used to power various analog and digital
@@ -531,82 +529,77 @@ static void __init msm8930_allocate_memory_regions(void)
* does not need to be as high as 2.85V. It is choosen for
* microphone sensitivity purpose.
*/
static struct wcd9xxx_pdata tabla_platform_data = {
.slimbus_slave_device = {
.name = "tabla-slave",
.e_addr = {0, 0, 0x10, 0, 0x17, 2},
static struct wcd9xxx_pdata sitar_platform_data = {
.slimbus_slave_device = {
.name = "sitar-slave",
.e_addr = {0, 0, 0x00, 0, 0x17, 2},
},
.irq = MSM_GPIO_TO_INT(62),
.irq_base = TABLA_INTERRUPT_BASE,
.irq_base = SITAR_INTERRUPT_BASE,
.num_irqs = NR_WCD9XXX_IRQS,
/*TODO: Replace this with right PM8038 gpio */
#ifndef MSM8930_PHASE_2
.reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
#endif
.reset_gpio = 42,
.micbias = {
.ldoh_v = TABLA_LDOH_2P85_V,
.ldoh_v = SITAR_LDOH_2P85_V,
.cfilt1_mv = 1800,
.cfilt2_mv = 1800,
.cfilt3_mv = 1800,
.bias1_cfilt_sel = TABLA_CFILT1_SEL,
.bias2_cfilt_sel = TABLA_CFILT2_SEL,
.bias3_cfilt_sel = TABLA_CFILT3_SEL,
.bias4_cfilt_sel = TABLA_CFILT3_SEL,
}
};
static struct slim_device msm_slim_tabla = {
.name = "tabla-slim",
.e_addr = {0, 1, 0x10, 0, 0x17, 2},
.dev = {
.platform_data = &tabla_platform_data,
.bias1_cfilt_sel = SITAR_CFILT1_SEL,
.bias2_cfilt_sel = SITAR_CFILT2_SEL,
},
.regulator = {
{
.name = "CDC_VDD_CP",
.min_uV = 2200000,
.max_uV = 2200000,
.optimum_uA = WCD9XXX_CDC_VDDA_CP_CUR_MAX,
},
{
.name = "CDC_VDDA_RX",
.min_uV = 1800000,
.max_uV = 1800000,
.optimum_uA = WCD9XXX_CDC_VDDA_RX_CUR_MAX,
},
{
.name = "CDC_VDDA_TX",
.min_uV = 1800000,
.max_uV = 1800000,
.optimum_uA = WCD9XXX_CDC_VDDA_TX_CUR_MAX,
},
{
.name = "VDDIO_CDC",
.min_uV = 1800000,
.max_uV = 1800000,
.optimum_uA = WCD9XXX_VDDIO_CDC_CUR_MAX,
},
{
.name = "VDDD_CDC_D",
.min_uV = 1200000,
.max_uV = 1200000,
.optimum_uA = WCD9XXX_VDDD_CDC_D_CUR_MAX,
},
{
.name = "CDC_VDDA_A_1P2V",
.min_uV = 1200000,
.max_uV = 1200000,
.optimum_uA = WCD9XXX_VDDD_CDC_A_CUR_MAX,
},
},
};
static struct wcd9xxx_pdata tabla20_platform_data = {
.slimbus_slave_device = {
.name = "tabla-slave",
.e_addr = {0, 0, 0x60, 0, 0x17, 2},
},
.irq = MSM_GPIO_TO_INT(62),
.irq_base = TABLA_INTERRUPT_BASE,
.num_irqs = NR_WCD9XXX_IRQS,
/*TODO: Replace this with right PM8038 gpio */
#ifndef MSM8930_PHASE_2
.reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
#endif
.micbias = {
.ldoh_v = TABLA_LDOH_2P85_V,
.cfilt1_mv = 1800,
.cfilt2_mv = 1800,
.cfilt3_mv = 1800,
.bias1_cfilt_sel = TABLA_CFILT1_SEL,
.bias2_cfilt_sel = TABLA_CFILT2_SEL,
.bias3_cfilt_sel = TABLA_CFILT3_SEL,
.bias4_cfilt_sel = TABLA_CFILT3_SEL,
}
};
static struct slim_device msm_slim_tabla20 = {
.name = "tabla2x-slim",
.e_addr = {0, 1, 0x60, 0, 0x17, 2},
static struct slim_device msm_slim_sitar = {
.name = "sitar-slim",
.e_addr = {0, 1, 0x00, 0, 0x17, 2},
.dev = {
.platform_data = &tabla20_platform_data,
.platform_data = &sitar_platform_data,
},
};
#endif
static struct slim_boardinfo msm_slim_devices[] = {
#ifdef CONFIG_WCD9310_CODEC
#ifdef CONFIG_WCD9304_CODEC
{
.bus_num = 1,
.slim_slave = &msm_slim_tabla,
},
{
.bus_num = 1,
.slim_slave = &msm_slim_tabla20,
.slim_slave = &msm_slim_sitar,
},
#endif
/* add more slimbus slaves as needed */

10
drivers/mfd/Kconfig
View File

@@ -879,6 +879,16 @@ config MFD_PM8XXX_BATT_ALARM
voltage leaves the accepatable range which then calls a notifier call
chain.
config WCD9304_CODEC
tristate "WCD9304 Codec"
select SLIMBUS
select MFD_CORE
default n
help
Enables the WCD9304 core driver. The core driver provides
read/write capability to registers which are part of the
WCD9304 core and gives the ability to use the WCD9304 codec.
config WCD9310_CODEC
tristate "WCD9310 Codec"
select SLIMBUS

1
drivers/mfd/Makefile
View File

@@ -70,6 +70,7 @@ obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
obj-$(CONFIG_MCP_UCB1200_TS) += ucb1x00-ts.o
obj-$(CONFIG_WCD9310_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
obj-$(CONFIG_WCD9304_CODEC) += wcd9xxx-core.o wcd9xxx-irq.o wcd9xxx-slimslave.o
ifeq ($(CONFIG_SA1100_ASSABET),y)
obj-$(CONFIG_MCP_UCB1200) += ucb1x00-assabet.o

65
drivers/mfd/wcd9xxx-core.c
View File

@@ -239,6 +239,12 @@ static struct mfd_cell tabla_devs[] = {
},
};
static struct mfd_cell sitar_devs[] = {
{
.name = "sitar_codec",
},
};
static void wcd9xxx_bring_up(struct wcd9xxx *wcd9xxx)
{
wcd9xxx_reg_write(wcd9xxx, WCD9XXX_A_LEAKAGE_CTL, 0x4);
@@ -322,14 +328,22 @@ static int wcd9xxx_device_init(struct wcd9xxx *wcd9xxx, int irq)
WCD9XXX_A_CHIP_VERSION) & 0x1F;
pr_info("%s : Codec version %u initialized\n",
__func__, wcd9xxx->version);
pr_info("idbyte_0[%08x] idbyte_1[%08x] idbyte_2[%08x] idbyte_3[%08x]\n",
idbyte_0, idbyte_1, idbyte_2, idbyte_3);
if (TABLA_IS_1_X(wcd9xxx->version)) {
wcd9xxx_dev = tabla1x_devs;
wcd9xxx_dev_size = ARRAY_SIZE(tabla1x_devs);
if (!strncmp(wcd9xxx->slim->name, "tabla", 5)) {
if (TABLA_IS_1_X(wcd9xxx->version)) {
wcd9xxx_dev = tabla1x_devs;
wcd9xxx_dev_size = ARRAY_SIZE(tabla1x_devs);
} else {
wcd9xxx_dev = tabla_devs;
wcd9xxx_dev_size = ARRAY_SIZE(tabla_devs);
}
} else {
wcd9xxx_dev = tabla_devs;
wcd9xxx_dev_size = ARRAY_SIZE(tabla_devs);
wcd9xxx_dev = sitar_devs;
wcd9xxx_dev_size = ARRAY_SIZE(sitar_devs);
}
ret = mfd_add_devices(wcd9xxx->dev, -1,
wcd9xxx_dev, wcd9xxx_dev_size,
NULL, 0);
@@ -704,6 +718,7 @@ static int __devinit wcd9xxx_i2c_probe(struct i2c_client *client,
ret = -EIO;
goto fail;
}
dev_set_drvdata(&client->dev, wcd9xxx);
wcd9xxx->dev = &client->dev;
wcd9xxx->reset_gpio = pdata->reset_gpio;
@@ -862,12 +877,6 @@ static int wcd9xxx_slim_probe(struct slim_device *slim)
pr_err("%s: error, initializing device failed\n", __func__);
goto err_slim_add;
}
/*
if (!strncmp(wcd9xxx->slim->name, "tabla", 5)) {
wcd9xxx->num_rx_port = 7;
wcd9xxx->num_tx_port = 10;
}
*/
wcd9xxx_init_slimslave(wcd9xxx, wcd9xxx_pgd_la);
#ifdef CONFIG_DEBUG_FS
debugCodec = wcd9xxx;
@@ -944,7 +953,10 @@ static int wcd9xxx_slim_resume(struct slim_device *sldev)
static int wcd9xxx_i2c_resume(struct i2c_client *i2cdev)
{
struct wcd9xxx *wcd9xxx = dev_get_drvdata(&i2cdev->dev);
return wcd9xxx_resume(wcd9xxx);
if (wcd9xxx)
return wcd9xxx_resume(wcd9xxx);
else
return 0;
}
static int wcd9xxx_suspend(struct wcd9xxx *wcd9xxx, pm_message_t pmesg)
@@ -998,9 +1010,28 @@ static int wcd9xxx_slim_suspend(struct slim_device *sldev, pm_message_t pmesg)
static int wcd9xxx_i2c_suspend(struct i2c_client *i2cdev, pm_message_t pmesg)
{
struct wcd9xxx *wcd9xxx = dev_get_drvdata(&i2cdev->dev);
return wcd9xxx_suspend(wcd9xxx, pmesg);
if (wcd9xxx)
return wcd9xxx_suspend(wcd9xxx, pmesg);
else
return 0;
}
static const struct slim_device_id sitar_slimtest_id[] = {
{"sitar-slim", 0},
{}
};
static struct slim_driver sitar_slim_driver = {
.driver = {
.name = "sitar-slim",
.owner = THIS_MODULE,
},
.probe = wcd9xxx_slim_probe,
.remove = wcd9xxx_slim_remove,
.id_table = sitar_slimtest_id,
.resume = wcd9xxx_slim_resume,
.suspend = wcd9xxx_slim_suspend,
};
static const struct slim_device_id slimtest_id[] = {
{"tabla-slim", 0},
{}
@@ -1063,7 +1094,7 @@ static struct i2c_driver tabla_i2c_driver = {
static int __init wcd9xxx_init(void)
{
int ret1, ret2, ret3;
int ret1, ret2, ret3, ret4;
ret1 = slim_driver_register(&tabla_slim_driver);
if (ret1 != 0)
@@ -1077,7 +1108,11 @@ static int __init wcd9xxx_init(void)
if (ret3 != 0)
pr_err("failed to add the I2C driver\n");
return (ret1 && ret2 && ret3) ? -1 : 0;
ret4 = slim_driver_register(&sitar_slim_driver);
if (ret1 != 0)
pr_err("Failed to register sitar SB driver: %d\n", ret4);
return (ret1 && ret2 && ret3 && ret4) ? -1 : 0;
}
module_init(wcd9xxx_init);

742
include/linux/mfd/wcd9xxx/wcd9304_registers.h Normal file
View File

@@ -0,0 +1,742 @@
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef SITAR_CODEC_DIGITAL_H
#define SITAR_CODEC_DIGITAL_H
#define SITAR_A_PIN_CTL_OE0 (0x10)
#define SITAR_A_PIN_CTL_OE0__POR (0x00000000)
#define SITAR_A_PIN_CTL_OE1 (0x11)
#define SITAR_A_PIN_CTL_OE1__POR (0x00000000)
#define SITAR_A_PIN_CTL_DATA0 (0x12)
#define SITAR_A_PIN_CTL_DATA0__POR (0x00000000)
#define SITAR_A_PIN_CTL_DATA1 (0x13)
#define SITAR_A_PIN_CTL_DATA1__POR (0x00000000)
#define SITAR_A_HDRIVE_GENERIC (0x18)
#define SITAR_A_HDRIVE_GENERIC__POR (0x00000000)
#define SITAR_A_HDRIVE_OVERRIDE (0x19)
#define SITAR_A_HDRIVE_OVERRIDE__POR (0x00000008)
#define SITAR_A_ANA_CSR_WAIT_STATE (0x20)
#define SITAR_A_ANA_CSR_WAIT_STATE__POR (0x00000044)
#define SITAR_A_PROCESS_MONITOR_CTL0 (0x40)
#define SITAR_A_PROCESS_MONITOR_CTL0__POR (0x00000080)
#define SITAR_A_PROCESS_MONITOR_CTL1 (0x41)
#define SITAR_A_PROCESS_MONITOR_CTL1__POR (0x00000000)
#define SITAR_A_PROCESS_MONITOR_CTL2 (0x42)
#define SITAR_A_PROCESS_MONITOR_CTL2__POR (0x00000000)
#define SITAR_A_PROCESS_MONITOR_CTL3 (0x43)
#define SITAR_A_PROCESS_MONITOR_CTL3__POR (0x00000001)
#define SITAR_A_QFUSE_CTL (0x48)
#define SITAR_A_QFUSE_CTL__POR (0x00000000)
#define SITAR_A_QFUSE_STATUS (0x49)
#define SITAR_A_QFUSE_STATUS__POR (0x00000000)
#define SITAR_A_QFUSE_DATA_OUT0 (0x4A)
#define SITAR_A_QFUSE_DATA_OUT0__POR (0x00000000)
#define SITAR_A_QFUSE_DATA_OUT1 (0x4B)
#define SITAR_A_QFUSE_DATA_OUT1__POR (0x00000000)
#define SITAR_A_QFUSE_DATA_OUT2 (0x4C)
#define SITAR_A_QFUSE_DATA_OUT2__POR (0x00000000)
#define SITAR_A_QFUSE_DATA_OUT3 (0x4D)
#define SITAR_A_QFUSE_DATA_OUT3__POR (0x00000000)
#define SITAR_A_QFUSE_DATA_OUT4 (0x4E)
#define SITAR_A_QFUSE_DATA_OUT4__POR (0x00000000)
#define SITAR_A_QFUSE_DATA_OUT5 (0x4F)
#define SITAR_A_QFUSE_DATA_OUT5__POR (0x00000000)
#define SITAR_A_QFUSE_DATA_OUT6 (0x50)
#define SITAR_A_QFUSE_DATA_OUT6__POR (0x00000000)
#define SITAR_A_QFUSE_DATA_OUT7 (0x51)
#define SITAR_A_QFUSE_DATA_OUT7__POR (0x00000000)
#define SITAR_A_CDC_CTL (0x80)
#define SITAR_A_CDC_CTL__POR (0x00000000)
#define SITAR_A_LEAKAGE_CTL (0x88)
#define SITAR_A_LEAKAGE_CTL__POR (0x00000004)
#define SITAR_A_INTR_MODE (0x90)
#define SITAR_A_INTR_MODE__POR (0x00000000)
#define SITAR_A_INTR_MASK0 (0x94)
#define SITAR_A_INTR_MASK0__POR (0x000000ff)
#define SITAR_A_INTR_MASK1 (0x95)
#define SITAR_A_INTR_MASK1__POR (0x000000ff)
#define SITAR_A_INTR_MASK2 (0x96)
#define SITAR_A_INTR_MASK2__POR (0x000000ff)
#define SITAR_A_INTR_STATUS0 (0x98)
#define SITAR_A_INTR_STATUS0__POR (0x00000000)
#define SITAR_A_INTR_STATUS1 (0x99)
#define SITAR_A_INTR_STATUS1__POR (0x00000000)
#define SITAR_A_INTR_STATUS2 (0x9A)
#define SITAR_A_INTR_STATUS2__POR (0x00000000)
#define SITAR_A_INTR_CLEAR0 (0x9C)
#define SITAR_A_INTR_CLEAR0__POR (0x00000000)
#define SITAR_A_INTR_CLEAR1 (0x9D)
#define SITAR_A_INTR_CLEAR1__POR (0x00000000)
#define SITAR_A_INTR_CLEAR2 (0x9E)
#define SITAR_A_INTR_CLEAR2__POR (0x00000000)
#define SITAR_A_INTR_LEVEL0 (0xA0)
#define SITAR_A_INTR_LEVEL0__POR (0x00000001)
#define SITAR_A_INTR_LEVEL1 (0xA1)
#define SITAR_A_INTR_LEVEL1__POR (0x00000000)
#define SITAR_A_INTR_LEVEL2 (0xA2)
#define SITAR_A_INTR_LEVEL2__POR (0x00000000)
#define SITAR_A_INTR_TEST0 (0xA4)
#define SITAR_A_INTR_TEST0__POR (0x00000000)
#define SITAR_A_INTR_TEST1 (0xA5)
#define SITAR_A_INTR_TEST1__POR (0x00000000)
#define SITAR_A_INTR_TEST2 (0xA6)
#define SITAR_A_INTR_TEST2__POR (0x00000000)
#define SITAR_A_INTR_SET0 (0xA8)
#define SITAR_A_INTR_SET0__POR (0x00000000)
#define SITAR_A_INTR_SET1 (0xA9)
#define SITAR_A_INTR_SET1__POR (0x00000000)
#define SITAR_A_INTR_SET2 (0xAA)
#define SITAR_A_INTR_SET2__POR (0x00000000)
#define SITAR_A_CDC_TX_I2S_SCK_MODE (0xC0)
#define SITAR_A_CDC_TX_I2S_SCK_MODE__POR (0x00000000)
#define SITAR_A_CDC_TX_I2S_WS_MODE (0xC1)
#define SITAR_A_CDC_TX_I2S_WS_MODE__POR (0x00000000)
#define SITAR_A_CDC_DMIC_DATA0_MODE (0xC4)
#define SITAR_A_CDC_DMIC_DATA0_MODE__POR (0x00000000)
#define SITAR_A_CDC_DMIC_CLK0_MODE (0xC5)
#define SITAR_A_CDC_DMIC_CLK0_MODE__POR (0x00000000)
#define SITAR_A_CDC_DMIC_DATA1_MODE (0xC6)
#define SITAR_A_CDC_DMIC_DATA1_MODE__POR (0x00000000)
#define SITAR_A_CDC_DMIC_CLK1_MODE (0xC7)
#define SITAR_A_CDC_DMIC_CLK1_MODE__POR (0x00000000)
#define SITAR_A_CDC_TX_I2S_SD0_MODE (0xC8)
#define SITAR_A_CDC_TX_I2S_SD0_MODE__POR (0x00000000)
#define SITAR_A_CDC_INTR_MODE (0xC9)
#define SITAR_A_CDC_INTR_MODE__POR (0x00000000)
#define SITAR_A_CDC_RX_I2S_SD0_MODE (0xCA)
#define SITAR_A_CDC_RX_I2S_SD0_MODE__POR (0x00000000)
#define SITAR_A_CDC_RX_I2S_SD1_MODE (0xCB)
#define SITAR_A_CDC_RX_I2S_SD1_MODE__POR (0x00000000)
#define SITAR_A_BIAS_REF_CTL (0x100)
#define SITAR_A_BIAS_REF_CTL__POR (0x0000001c)
#define SITAR_A_BIAS_CENTRAL_BG_CTL (0x101)
#define SITAR_A_BIAS_CENTRAL_BG_CTL__POR (0x00000050)
#define SITAR_A_BIAS_PRECHRG_CTL (0x102)
#define SITAR_A_BIAS_PRECHRG_CTL__POR (0x00000007)
#define SITAR_A_BIAS_CURR_CTL_1 (0x103)
#define SITAR_A_BIAS_CURR_CTL_1__POR (0x00000052)
#define SITAR_A_BIAS_CURR_CTL_2 (0x104)
#define SITAR_A_BIAS_CURR_CTL_2__POR (0x00000000)
#define SITAR_A_BIAS_OSC_BG_CTL (0x105)
#define SITAR_A_BIAS_OSC_BG_CTL__POR (0x00000016)
#define SITAR_A_CLK_BUFF_EN1 (0x108)
#define SITAR_A_CLK_BUFF_EN1__POR (0x00000004)
#define SITAR_A_CLK_BUFF_EN2 (0x109)
#define SITAR_A_CLK_BUFF_EN2__POR (0x00000002)
#define SITAR_A_LDO_H_MODE_1 (0x110)
#define SITAR_A_LDO_H_MODE_1__POR (0x00000065)
#define SITAR_A_LDO_H_MODE_2 (0x111)
#define SITAR_A_LDO_H_MODE_2__POR (0x000000a8)
#define SITAR_A_LDO_H_LOOP_CTL (0x112)
#define SITAR_A_LDO_H_LOOP_CTL__POR (0x0000006b)
#define SITAR_A_LDO_H_COMP_1 (0x113)
#define SITAR_A_LDO_H_COMP_1__POR (0x00000084)
#define SITAR_A_LDO_H_COMP_2 (0x114)
#define SITAR_A_LDO_H_COMP_2__POR (0x000000e0)
#define SITAR_A_LDO_H_BIAS_1 (0x115)
#define SITAR_A_LDO_H_BIAS_1__POR (0x0000006d)
#define SITAR_A_LDO_H_BIAS_2 (0x116)
#define SITAR_A_LDO_H_BIAS_2__POR (0x000000a5)
#define SITAR_A_LDO_H_BIAS_3 (0x117)
#define SITAR_A_LDO_H_BIAS_3__POR (0x00000060)
#define SITAR_A_MICB_CFILT_1_CTL (0x128)
#define SITAR_A_MICB_CFILT_1_CTL__POR (0x00000040)
#define SITAR_A_MICB_CFILT_1_VAL (0x129)
#define SITAR_A_MICB_CFILT_1_VAL__POR (0x00000080)
#define SITAR_A_MICB_CFILT_1_PRECHRG (0x12A)
#define SITAR_A_MICB_CFILT_1_PRECHRG__POR (0x00000038)
#define SITAR_A_MICB_1_CTL (0x12B)
#define SITAR_A_MICB_1_CTL__POR (0x00000016)
#define SITAR_A_MICB_1_INT_RBIAS (0x12C)
#define SITAR_A_MICB_1_INT_RBIAS__POR (0x00000024)
#define SITAR_A_MICB_1_MBHC (0x12D)
#define SITAR_A_MICB_1_MBHC__POR (0x00000001)
#define SITAR_A_MICB_CFILT_2_CTL (0x12E)
#define SITAR_A_MICB_CFILT_2_CTL__POR (0x00000040)
#define SITAR_A_MICB_CFILT_2_VAL (0x12F)
#define SITAR_A_MICB_CFILT_2_VAL__POR (0x00000080)
#define SITAR_A_MICB_CFILT_2_PRECHRG (0x130)
#define SITAR_A_MICB_CFILT_2_PRECHRG__POR (0x00000038)
#define SITAR_A_MICB_2_CTL (0x131)
#define SITAR_A_MICB_2_CTL__POR (0x00000016)
#define SITAR_A_MICB_2_INT_RBIAS (0x132)
#define SITAR_A_MICB_2_INT_RBIAS__POR (0x00000024)
#define SITAR_A_MICB_2_MBHC (0x133)
#define SITAR_A_MICB_2_MBHC__POR (0x00000002)
#define SITAR_A_TX_COM_BIAS (0x14C)
#define SITAR_A_TX_COM_BIAS__POR (0x000000e0)
#define SITAR_A_MBHC_SCALING_MUX_1 (0x14E)
#define SITAR_A_MBHC_SCALING_MUX_1__POR (0x00000000)
#define SITAR_A_MBHC_SCALING_MUX_2 (0x14F)
#define SITAR_A_MBHC_SCALING_MUX_2__POR (0x00000080)
#define SITAR_A_TX_SUP_SWITCH_CTRL_1 (0x151)
#define SITAR_A_TX_SUP_SWITCH_CTRL_1__POR (0x00000000)
#define SITAR_A_TX_SUP_SWITCH_CTRL_2 (0x152)
#define SITAR_A_TX_SUP_SWITCH_CTRL_2__POR (0x00000080)
#define SITAR_A_TX_1_2_EN (0x153)
#define SITAR_A_TX_1_2_EN__POR (0x00000000)
#define SITAR_A_TX_1_2_TEST_EN (0x154)
#define SITAR_A_TX_1_2_TEST_EN__POR (0x000000cc)
#define SITAR_A_TX_1_2_ADC_CH1 (0x155)
#define SITAR_A_TX_1_2_ADC_CH1__POR (0x00000044)
#define SITAR_A_TX_1_2_ADC_CH2 (0x156)
#define SITAR_A_TX_1_2_ADC_CH2__POR (0x00000044)
#define SITAR_A_TX_1_2_ATEST_REFCTRL (0x157)
#define SITAR_A_TX_1_2_ATEST_REFCTRL__POR (0x00000000)
#define SITAR_A_TX_1_2_TEST_CTL (0x158)
#define SITAR_A_TX_1_2_TEST_CTL__POR (0x00000038)
#define SITAR_A_TX_1_2_TEST_BLOCK_EN (0x159)
#define SITAR_A_TX_1_2_TEST_BLOCK_EN__POR (0x000000fc)
#define SITAR_A_TX_1_2_TXFE_CLKDIV (0x15A)
#define SITAR_A_TX_1_2_TXFE_CLKDIV__POR (0x000000ee)
#define SITAR_A_TX_1_2_SAR_ERR_CH1 (0x15B)
#define SITAR_A_TX_1_2_SAR_ERR_CH1__POR (0x00000000)
#define SITAR_A_TX_1_2_SAR_ERR_CH2 (0x15C)
#define SITAR_A_TX_1_2_SAR_ERR_CH2__POR (0x00000000)
#define SITAR_A_TX_3_EN (0x15D)
#define SITAR_A_TX_3_EN__POR (0x00000000)
#define SITAR_A_TX_3_TEST_EN (0x15E)
#define SITAR_A_TX_3_TEST_EN__POR (0x000000cc)
#define SITAR_A_TX_3_ADC (0x15F)
#define SITAR_A_TX_3_ADC__POR (0x00000044)
#define SITAR_A_TX_3_MBHC_ATEST_REFCTRL (0x161)
#define SITAR_A_TX_3_MBHC_ATEST_REFCTRL__POR (0x00000000)
#define SITAR_A_TX_3_TEST_CTL (0x162)
#define SITAR_A_TX_3_TEST_CTL__POR (0x00000038)
#define SITAR_A_TX_3_TEST_BLOCK_EN (0x163)
#define SITAR_A_TX_3_TEST_BLOCK_EN__POR (0x000000fc)
#define SITAR_A_TX_3_TXFE_CKDIV (0x164)
#define SITAR_A_TX_3_TXFE_CKDIV__POR (0x000000ee)
#define SITAR_A_TX_3_SAR_ERR (0x165)
#define SITAR_A_TX_3_SAR_ERR__POR (0x00000000)
#define SITAR_A_TX_4_MBHC_EN (0x171)
#define SITAR_A_TX_4_MBHC_EN__POR (0x0000000c)
#define SITAR_A_TX_4_MBHC_ADC (0x173)
#define SITAR_A_TX_4_MBHC_ADC__POR (0x00000044)
#define SITAR_A_TX_4_MBHC_TEST_CTL (0x174)
#define SITAR_A_TX_4_MBHC_TEST_CTL__POR (0x00000038)
#define SITAR_A_TX_4_MBHC_SAR_ERR (0x175)
#define SITAR_A_TX_4_MBHC_SAR_ERR__POR (0x00000000)
#define SITAR_A_TX_4_TXFE_CLKDIV (0x176)
#define SITAR_A_TX_4_TXFE_CLKDIV__POR (0x0000001c)
#define SITAR_A_AUX_COM_CTL (0x180)
#define SITAR_A_AUX_COM_CTL__POR (0x00000034)
#define SITAR_A_AUX_COM_ATEST (0x181)
#define SITAR_A_AUX_COM_ATEST__POR (0x00000000)
#define SITAR_A_AUX_L_EN (0x182)
#define SITAR_A_AUX_L_EN__POR (0x00000000)
#define SITAR_A_AUX_L_GAIN (0x183)
#define SITAR_A_AUX_L_GAIN__POR (0x0000001f)
#define SITAR_A_AUX_L_PA_CONN (0x184)
#define SITAR_A_AUX_L_PA_CONN__POR (0x00000000)
#define SITAR_A_AUX_L_PA_CONN_INV (0x185)
#define SITAR_A_AUX_L_PA_CONN_INV__POR (0x00000000)
#define SITAR_A_AUX_R_EN (0x186)
#define SITAR_A_AUX_R_EN__POR (0x00000000)
#define SITAR_A_AUX_R_GAIN (0x187)
#define SITAR_A_AUX_R_GAIN__POR (0x0000001f)
#define SITAR_A_AUX_R_PA_CONN (0x188)
#define SITAR_A_AUX_R_PA_CONN__POR (0x00000000)
#define SITAR_A_AUX_R_PA_CONN_INV (0x189)
#define SITAR_A_AUX_R_PA_CONN_INV__POR (0x00000000)
#define SITAR_A_CP_EN (0x192)
#define SITAR_A_CP_EN__POR (0x000000e6)
#define SITAR_A_CP_CLK (0x193)
#define SITAR_A_CP_CLK__POR (0x00000029)
#define SITAR_A_CP_STATIC (0x194)
#define SITAR_A_CP_STATIC__POR (0x00000010)
#define SITAR_A_CP_DCC1 (0x195)
#define SITAR_A_CP_DCC1__POR (0x00000052)
#define SITAR_A_CP_DCC3 (0x196)
#define SITAR_A_CP_DCC3__POR (0x00000001)
#define SITAR_A_CP_ATEST (0x197)
#define SITAR_A_CP_ATEST__POR (0x00000000)
#define SITAR_A_CP_DTEST (0x198)
#define SITAR_A_CP_DTEST__POR (0x00000000)
#define SITAR_A_RX_COM_TIMER_DIV (0x19E)
#define SITAR_A_RX_COM_TIMER_DIV__POR (0x000000e8)
#define SITAR_A_RX_COM_OCP_CTL (0x19F)
#define SITAR_A_RX_COM_OCP_CTL__POR (0x0000001f)
#define SITAR_A_RX_COM_OCP_COUNT (0x1A0)
#define SITAR_A_RX_COM_OCP_COUNT__POR (0x00000077)
#define SITAR_A_RX_COM_DAC_CTL (0x1A1)
#define SITAR_A_RX_COM_DAC_CTL__POR (0x00000000)
#define SITAR_A_RX_COM_BIAS (0x1A2)
#define SITAR_A_RX_COM_BIAS__POR (0x00000000)
#define SITAR_A_RX_HPH_BIAS_PA (0x1A6)
#define SITAR_A_RX_HPH_BIAS_PA__POR (0x00000057)
#define SITAR_A_RX_HPH_BIAS_LDO (0x1A7)
#define SITAR_A_RX_HPH_BIAS_LDO__POR (0x00000056)
#define SITAR_A_RX_HPH_BIAS_CNP (0x1A8)
#define SITAR_A_RX_HPH_BIAS_CNP__POR (0x0000008a)
#define SITAR_A_RX_HPH_BIAS_WG (0x1A9)
#define SITAR_A_RX_HPH_BIAS_WG__POR (0x00000060)
#define SITAR_A_RX_HPH_OCP_CTL (0x1AA)
#define SITAR_A_RX_HPH_OCP_CTL__POR (0x000000e8)
#define SITAR_A_RX_HPH_CNP_EN (0x1AB)
#define SITAR_A_RX_HPH_CNP_EN__POR (0x00000080)
#define SITAR_A_RX_HPH_CNP_WG_CTL (0x1AC)
#define SITAR_A_RX_HPH_CNP_WG_CTL__POR (0x000000dc)
#define SITAR_A_RX_HPH_CNP_WG_TIME (0x1AD)
#define SITAR_A_RX_HPH_CNP_WG_TIME__POR (0x00000028)
#define SITAR_A_RX_HPH_L_GAIN (0x1AE)
#define SITAR_A_RX_HPH_L_GAIN__POR (0x00000000)
#define SITAR_A_RX_HPH_L_TEST (0x1AF)
#define SITAR_A_RX_HPH_L_TEST__POR (0x00000001)
#define SITAR_A_RX_HPH_L_PA_CTL (0x1B0)
#define SITAR_A_RX_HPH_L_PA_CTL__POR (0x00000040)
#define SITAR_A_RX_HPH_L_DAC_CTL (0x1B1)
#define SITAR_A_RX_HPH_L_DAC_CTL__POR (0x00000000)
#define SITAR_A_RX_HPH_L_ATEST (0x1B2)
#define SITAR_A_RX_HPH_L_ATEST__POR (0x00000000)
#define SITAR_A_RX_HPH_L_STATUS (0x1B3)
#define SITAR_A_RX_HPH_L_STATUS__POR (0x00000004)
#define SITAR_A_RX_HPH_R_GAIN (0x1B4)
#define SITAR_A_RX_HPH_R_GAIN__POR (0x00000000)
#define SITAR_A_RX_HPH_R_TEST (0x1B5)
#define SITAR_A_RX_HPH_R_TEST__POR (0x00000001)
#define SITAR_A_RX_HPH_R_PA_CTL (0x1B6)
#define SITAR_A_RX_HPH_R_PA_CTL__POR (0x00000040)
#define SITAR_A_RX_HPH_R_DAC_CTL (0x1B7)
#define SITAR_A_RX_HPH_R_DAC_CTL__POR (0x00000000)
#define SITAR_A_RX_HPH_R_ATEST (0x1B8)
#define SITAR_A_RX_HPH_R_ATEST__POR (0x00000000)
#define SITAR_A_RX_HPH_R_STATUS (0x1B9)
#define SITAR_A_RX_HPH_R_STATUS__POR (0x00000004)
#define SITAR_A_RX_EAR_BIAS_PA (0x1BA)
#define SITAR_A_RX_EAR_BIAS_PA__POR (0x000000a6)
#define SITAR_A_RX_EAR_BIAS_CMBUFF (0x1BB)
#define SITAR_A_RX_EAR_BIAS_CMBUFF__POR (0x000000a0)
#define SITAR_A_RX_EAR_EN (0x1BC)
#define SITAR_A_RX_EAR_EN__POR (0x00000000)
#define SITAR_A_RX_EAR_GAIN (0x1BD)
#define SITAR_A_RX_EAR_GAIN__POR (0x00000002)
#define SITAR_A_RX_EAR_CMBUFF (0x1BE)
#define SITAR_A_RX_EAR_CMBUFF__POR (0x00000004)
#define SITAR_A_RX_EAR_ICTL (0x1BF)
#define SITAR_A_RX_EAR_ICTL__POR (0x00000040)
#define SITAR_A_RX_EAR_CCOMP (0x1C0)
#define SITAR_A_RX_EAR_CCOMP__POR (0x00000008)
#define SITAR_A_RX_EAR_VCM (0x1C1)
#define SITAR_A_RX_EAR_VCM__POR (0x00000003)
#define SITAR_A_RX_EAR_CNP (0x1C2)
#define SITAR_A_RX_EAR_CNP__POR (0x000000f2)
#define SITAR_A_RX_EAR_ATEST (0x1C3)
#define SITAR_A_RX_EAR_ATEST__POR (0x00000000)
#define SITAR_A_RX_EAR_STATUS (0x1C5)
#define SITAR_A_RX_EAR_STATUS__POR (0x00000004)
#define SITAR_A_RX_LINE_BIAS_PA (0x1C6)
#define SITAR_A_RX_LINE_BIAS_PA__POR (0x000000aa)
#define SITAR_A_RX_LINE_BIAS_LDO (0x1C7)
#define SITAR_A_RX_LINE_BIAS_LDO__POR (0x00000086)
#define SITAR_A_RX_LINE_BIAS_CNP1 (0x1C8)
#define SITAR_A_RX_LINE_BIAS_CNP1__POR (0x00000060)
#define SITAR_A_RX_LINE_COM (0x1C9)
#define SITAR_A_RX_LINE_COM__POR (0x00000000)
#define SITAR_A_RX_LINE_CNP_EN (0x1CA)
#define SITAR_A_RX_LINE_CNP_EN__POR (0x00000080)
#define SITAR_A_RX_LINE_CNP_WG_CTL (0x1CB)
#define SITAR_A_RX_LINE_CNP_WG_CTL__POR (0x000000dc)
#define SITAR_A_RX_LINE_CNP_WG_TIME (0x1CC)
#define SITAR_A_RX_LINE_CNP_WG_TIME__POR (0x00000028)
#define SITAR_A_RX_LINE_1_GAIN (0x1CD)
#define SITAR_A_RX_LINE_1_GAIN__POR (0x00000000)
#define SITAR_A_RX_LINE_1_TEST (0x1CE)
#define SITAR_A_RX_LINE_1_TEST__POR (0x00000001)
#define SITAR_A_RX_LINE_1_DAC_CTL (0x1CF)
#define SITAR_A_RX_LINE_1_DAC_CTL__POR (0x00000000)
#define SITAR_A_RX_LINE_1_STATUS (0x1D0)
#define SITAR_A_RX_LINE_1_STATUS__POR (0x00000004)
#define SITAR_A_RX_LINE_2_GAIN (0x1D1)
#define SITAR_A_RX_LINE_2_GAIN__POR (0x00000000)
#define SITAR_A_RX_LINE_2_TEST (0x1D2)
#define SITAR_A_RX_LINE_2_TEST__POR (0x00000001)
#define SITAR_A_RX_LINE_2_DAC_CTL (0x1D3)
#define SITAR_A_RX_LINE_2_DAC_CTL__POR (0x00000000)
#define SITAR_A_RX_LINE_2_STATUS (0x1D4)
#define SITAR_A_RX_LINE_2_STATUS__POR (0x00000004)
#define SITAR_A_RX_LINE_BIAS_CNP2 (0x1E1)
#define SITAR_A_RX_LINE_BIAS_CNP2__POR (0x0000008a)
#define SITAR_A_RX_LINE_OCP_CTL (0x1E2)
#define SITAR_A_RX_LINE_OCP_CTL__POR (0x000000e8)
#define SITAR_A_RX_LINE_1_PA_CTL (0x1E3)
#define SITAR_A_RX_LINE_1_PA_CTL__POR (0x00000040)
#define SITAR_A_RX_LINE_2_PA_CTL (0x1E4)
#define SITAR_A_RX_LINE_2_PA_CTL__POR (0x00000040)
#define SITAR_A_RX_LINE_CNP_DBG (0x1EC)
#define SITAR_A_RX_LINE_CNP_DBG__POR (0x00000000)
#define SITAR_A_MBHC_HPH (0x1ED)
#define SITAR_A_MBHC_HPH__POR (0x00000048)
#define SITAR_A_RC_OSC_FREQ (0x1F7)
#define SITAR_A_RC_OSC_FREQ__POR (0x00000046)
#define SITAR_A_RC_OSC_TEST (0x1F8)
#define SITAR_A_RC_OSC_TEST__POR (0x0000000a)
#define SITAR_A_RC_OSC_STATUS (0x1F9)
#define SITAR_A_RC_OSC_STATUS__POR (0x0000001c)
#define SITAR_A_RC_OSC_TUNER (0x1FA)
#define SITAR_A_RC_OSC_TUNER__POR (0x00000000)
#define SITAR_A_CDC_ANC1_CTL (0x200)
#define SITAR_A_CDC_ANC1_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_SHIFT (0x201)
#define SITAR_A_CDC_ANC1_SHIFT__POR (0x00000000)
#define SITAR_A_CDC_ANC1_IIR_B1_CTL (0x202)
#define SITAR_A_CDC_ANC1_IIR_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_IIR_B2_CTL (0x203)
#define SITAR_A_CDC_ANC1_IIR_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_IIR_B3_CTL (0x204)
#define SITAR_A_CDC_ANC1_IIR_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_IIR_B4_CTL (0x205)
#define SITAR_A_CDC_ANC1_IIR_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_LPF_B1_CTL (0x206)
#define SITAR_A_CDC_ANC1_LPF_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_LPF_B2_CTL (0x207)
#define SITAR_A_CDC_ANC1_LPF_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_LPF_B3_CTL (0x208)
#define SITAR_A_CDC_ANC1_LPF_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_SPARE (0x209)
#define SITAR_A_CDC_ANC1_SPARE__POR (0x00000000)
#define SITAR_A_CDC_ANC1_SMLPF_CTL (0x20A)
#define SITAR_A_CDC_ANC1_SMLPF_CTL__POR (0x00000000)
#define SITAR_A_CDC_ANC1_DCFLT_CTL (0x20B)
#define SITAR_A_CDC_ANC1_DCFLT_CTL__POR (0x00000000)
#define SITAR_A_CDC_TX1_VOL_CTL_TIMER (0x220)
#define SITAR_A_CDC_TX1_VOL_CTL_TIMER__POR (0x00000000)
#define SITAR_A_CDC_TX1_VOL_CTL_GAIN (0x221)
#define SITAR_A_CDC_TX1_VOL_CTL_GAIN__POR (0x00000000)
#define SITAR_A_CDC_TX1_VOL_CTL_CFG (0x222)
#define SITAR_A_CDC_TX1_VOL_CTL_CFG__POR (0x00000000)
#define SITAR_A_CDC_TX1_MUX_CTL (0x223)
#define SITAR_A_CDC_TX1_MUX_CTL__POR (0x00000008)
#define SITAR_A_CDC_TX1_CLK_FS_CTL (0x224)
#define SITAR_A_CDC_TX1_CLK_FS_CTL__POR (0x00000003)
#define SITAR_A_CDC_TX1_DMIC_CTL (0x225)
#define SITAR_A_CDC_TX1_DMIC_CTL__POR (0x00000000)
#define SITAR_A_CDC_SRC1_PDA_CFG (0x2A0)
#define SITAR_A_CDC_SRC1_PDA_CFG__POR (0x00000000)
#define SITAR_A_CDC_SRC1_FS_CTL (0x2A1)
#define SITAR_A_CDC_SRC1_FS_CTL__POR (0x0000001b)
#define SITAR_A_CDC_RX1_B1_CTL (0x000002B0)
#define SITAR_A_CDC_RX1_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX2_B1_CTL (0x000002B8)
#define SITAR_A_CDC_RX2_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX3_B1_CTL (0x000002C0)
#define SITAR_A_CDC_RX3_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX1_B2_CTL (0x000002B1)
#define SITAR_A_CDC_RX1_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX2_B2_CTL (0x000002B9)
#define SITAR_A_CDC_RX2_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX3_B2_CTL (0x000002C1)
#define SITAR_A_CDC_RX3_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX1_B3_CTL (0x000002B2)
#define SITAR_A_CDC_RX1_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX2_B3_CTL (0x000002BA)
#define SITAR_A_CDC_RX2_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX3_B3_CTL (0x000002C2)
#define SITAR_A_CDC_RX3_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX1_B4_CTL (0x000002B3)
#define SITAR_A_CDC_RX1_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX2_B4_CTL (0x000002BB)
#define SITAR_A_CDC_RX2_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX3_B4_CTL (0x000002C3)
#define SITAR_A_CDC_RX3_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX1_B5_CTL (0x000002B4)
#define SITAR_A_CDC_RX1_B5_CTL__POR (0x00000060)
#define SITAR_A_CDC_RX2_B5_CTL (0x000002BC)
#define SITAR_A_CDC_RX2_B5_CTL__POR (0x00000060)
#define SITAR_A_CDC_RX3_B5_CTL (0x000002C4)
#define SITAR_A_CDC_RX3_B5_CTL__POR (0x00000060)
#define SITAR_A_CDC_RX1_B6_CTL (0x000002B5)
#define SITAR_A_CDC_RX1_B6_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX2_B6_CTL (0x000002BD)
#define SITAR_A_CDC_RX2_B6_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX3_B6_CTL (0x000002C5)
#define SITAR_A_CDC_RX3_B6_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX1_VOL_CTL_B1_CTL (0x2B6)
#define SITAR_A_CDC_RX1_VOL_CTL_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_RX1_VOL_CTL_B2_CTL (0x2B7)
#define SITAR_A_CDC_RX1_VOL_CTL_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_ANC_RESET_CTL (0x300)
#define SITAR_A_CDC_CLK_ANC_RESET_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_RX_RESET_CTL (0x301)
#define SITAR_A_CDC_CLK_RX_RESET_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_TX_RESET_B1_CTL (0x302)
#define SITAR_A_CDC_CLK_TX_RESET_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_TX_RESET_B2_CTL (0x303)
#define SITAR_A_CDC_CLK_TX_RESET_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_DMIC_CTL (0x304)
#define SITAR_A_CDC_CLK_DMIC_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_RX_I2S_CTL (0x305)
#define SITAR_A_CDC_CLK_RX_I2S_CTL__POR (0x00000003)
#define SITAR_A_CDC_CLK_TX_I2S_CTL (0x306)
#define SITAR_A_CDC_CLK_TX_I2S_CTL__POR (0x00000003)
#define SITAR_A_CDC_CLK_OTHR_RESET_CTL (0x307)
#define SITAR_A_CDC_CLK_OTHR_RESET_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL (0x308)
#define SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_OTHR_CTL (0x30A)
#define SITAR_A_CDC_CLK_OTHR_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL (0x30B)
#define SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_ANC_CLK_EN_CTL (0x30C)
#define SITAR_A_CDC_CLK_ANC_CLK_EN_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_RX_B1_CTL (0x30D)
#define SITAR_A_CDC_CLK_RX_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_RX_B2_CTL (0x30E)
#define SITAR_A_CDC_CLK_RX_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_MCLK_CTL (0x30F)
#define SITAR_A_CDC_CLK_MCLK_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_PDM_CTL (0x310)
#define SITAR_A_CDC_CLK_PDM_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_SD_CTL (0x311)
#define SITAR_A_CDC_CLK_SD_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLK_LP_CTL (0x312)
#define SITAR_A_CDC_CLK_LP_CTL__POR (0x00000000)
#define SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL (0x320)
#define SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR (0x00000007)
#define SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL (0x321)
#define SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR (0x00000013)
#define SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL (0x322)
#define SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR (0x0000001b)
#define SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL (0x323)
#define SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR (0x0000007f)
#define SITAR_A_CDC_CLSG_GAIN_THRESH_CTL (0x324)
#define SITAR_A_CDC_CLSG_GAIN_THRESH_CTL__POR (0x00000026)
#define SITAR_A_CDC_CLSG_TIMER_B1_CFG (0x325)
#define SITAR_A_CDC_CLSG_TIMER_B1_CFG__POR (0x0000000a)
#define SITAR_A_CDC_CLSG_TIMER_B2_CFG (0x326)
#define SITAR_A_CDC_CLSG_TIMER_B2_CFG__POR (0x00000000)
#define SITAR_A_CDC_CLSG_CTL (0x327)
#define SITAR_A_CDC_CLSG_CTL__POR (0x00000013)
#define SITAR_A_CDC_IIR1_GAIN_B1_CTL (0x340)
#define SITAR_A_CDC_IIR1_GAIN_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_GAIN_B2_CTL (0x341)
#define SITAR_A_CDC_IIR1_GAIN_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_GAIN_B3_CTL (0x342)
#define SITAR_A_CDC_IIR1_GAIN_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_GAIN_B4_CTL (0x343)
#define SITAR_A_CDC_IIR1_GAIN_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_GAIN_B5_CTL (0x344)
#define SITAR_A_CDC_IIR1_GAIN_B5_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_GAIN_B6_CTL (0x345)
#define SITAR_A_CDC_IIR1_GAIN_B6_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_GAIN_B7_CTL (0x346)
#define SITAR_A_CDC_IIR1_GAIN_B7_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_GAIN_B8_CTL (0x347)
#define SITAR_A_CDC_IIR1_GAIN_B8_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_CTL (0x348)
#define SITAR_A_CDC_IIR1_CTL__POR (0x00000040)
#define SITAR_A_CDC_IIR1_GAIN_TIMER_CTL (0x349)
#define SITAR_A_CDC_IIR1_GAIN_TIMER_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_COEF_B1_CTL (0x34A)
#define SITAR_A_CDC_IIR1_COEF_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_COEF_B2_CTL (0x34B)
#define SITAR_A_CDC_IIR1_COEF_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_COEF_B3_CTL (0x34C)
#define SITAR_A_CDC_IIR1_COEF_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_COEF_B4_CTL (0x34D)
#define SITAR_A_CDC_IIR1_COEF_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_IIR1_COEF_B5_CTL (0x34E)
#define SITAR_A_CDC_IIR1_COEF_B5_CTL__POR (0x00000000)
#define SITAR_A_CDC_TOP_GAIN_UPDATE (0x360)
#define SITAR_A_CDC_TOP_GAIN_UPDATE__POR (0x00000000)
#define SITAR_A_CDC_TOP_RDAC_DOUT_CTL (0x361)
#define SITAR_A_CDC_TOP_RDAC_DOUT_CTL__POR (0x00000000)
#define SITAR_A_CDC_DEBUG_B1_CTL (0x368)
#define SITAR_A_CDC_DEBUG_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_DEBUG_B2_CTL (0x369)
#define SITAR_A_CDC_DEBUG_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_DEBUG_B3_CTL (0x36A)
#define SITAR_A_CDC_DEBUG_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_DEBUG_B4_CTL (0x36B)
#define SITAR_A_CDC_DEBUG_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_DEBUG_B5_CTL (0x36C)
#define SITAR_A_CDC_DEBUG_B5_CTL__POR (0x00000000)
#define SITAR_A_CDC_DEBUG_B6_CTL (0x36D)
#define SITAR_A_CDC_DEBUG_B6_CTL__POR (0x00000000)
#define SITAR_A_CDC_DEBUG_B7_CTL (0x36E)
#define SITAR_A_CDC_DEBUG_B7_CTL__POR (0x00000000)
#define SITAR_A_CDC_COMP1_B1_CTL (0x370)
#define SITAR_A_CDC_COMP1_B1_CTL__POR (0x00000030)
#define SITAR_A_CDC_COMP1_B2_CTL (0x371)
#define SITAR_A_CDC_COMP1_B2_CTL__POR (0x000000b5)
#define SITAR_A_CDC_COMP1_B3_CTL (0x372)
#define SITAR_A_CDC_COMP1_B3_CTL__POR (0x00000028)
#define SITAR_A_CDC_COMP1_B4_CTL (0x373)
#define SITAR_A_CDC_COMP1_B4_CTL__POR (0x0000003c)
#define SITAR_A_CDC_COMP1_B5_CTL (0x374)
#define SITAR_A_CDC_COMP1_B5_CTL__POR (0x0000001f)
#define SITAR_A_CDC_COMP1_B6_CTL (0x375)
#define SITAR_A_CDC_COMP1_B6_CTL__POR (0x00000000)
#define SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS (0x376)
#define SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS__POR (0x00000003)
#define SITAR_A_CDC_COMP1_FS_CFG (0x377)
#define SITAR_A_CDC_COMP1_FS_CFG__POR (0x0000001b)
#define SITAR_A_CDC_CONN_RX1_B1_CTL (0x380)
#define SITAR_A_CDC_CONN_RX1_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX1_B2_CTL (0x381)
#define SITAR_A_CDC_CONN_RX1_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX1_B3_CTL (0x382)
#define SITAR_A_CDC_CONN_RX1_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX2_B1_CTL (0x383)
#define SITAR_A_CDC_CONN_RX2_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX2_B2_CTL (0x384)
#define SITAR_A_CDC_CONN_RX2_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX2_B3_CTL (0x385)
#define SITAR_A_CDC_CONN_RX2_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX3_B1_CTL (0x386)
#define SITAR_A_CDC_CONN_RX3_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX3_B2_CTL (0x387)
#define SITAR_A_CDC_CONN_RX3_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX3_B3_CTL (0x388)
#define SITAR_A_CDC_CONN_RX3_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_ANC_B1_CTL (0x391)
#define SITAR_A_CDC_CONN_ANC_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_ANC_B2_CTL (0x392)
#define SITAR_A_CDC_CONN_ANC_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_TX_B1_CTL (0x393)
#define SITAR_A_CDC_CONN_TX_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_TX_B2_CTL (0x394)
#define SITAR_A_CDC_CONN_TX_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_EQ1_B1_CTL (0x397)
#define SITAR_A_CDC_CONN_EQ1_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_EQ1_B2_CTL (0x398)
#define SITAR_A_CDC_CONN_EQ1_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_EQ1_B3_CTL (0x399)
#define SITAR_A_CDC_CONN_EQ1_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_EQ1_B4_CTL (0x39A)
#define SITAR_A_CDC_CONN_EQ1_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_EQ2_B1_CTL (0x39B)
#define SITAR_A_CDC_CONN_EQ2_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_EQ2_B2_CTL (0x39C)
#define SITAR_A_CDC_CONN_EQ2_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_EQ2_B3_CTL (0x39D)
#define SITAR_A_CDC_CONN_EQ2_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_EQ2_B4_CTL (0x39E)
#define SITAR_A_CDC_CONN_EQ2_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_SRC1_B1_CTL (0x39F)
#define SITAR_A_CDC_CONN_SRC1_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_SRC1_B2_CTL (0x3A0)
#define SITAR_A_CDC_CONN_SRC1_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_SRC2_B1_CTL (0x3A1)
#define SITAR_A_CDC_CONN_SRC2_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_SRC2_B2_CTL (0x3A2)
#define SITAR_A_CDC_CONN_SRC2_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_TX_SB_B1_CTL (0x3A3)
#define SITAR_A_CDC_CONN_TX_SB_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_TX_SB_B2_CTL (0x3A4)
#define SITAR_A_CDC_CONN_TX_SB_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_TX_SB_B3_CTL (0x3A5)
#define SITAR_A_CDC_CONN_TX_SB_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_TX_SB_B4_CTL (0x3A6)
#define SITAR_A_CDC_CONN_TX_SB_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_TX_SB_B5_CTL (0x3A7)
#define SITAR_A_CDC_CONN_TX_SB_B5_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX_SB_B1_CTL (0x3AE)
#define SITAR_A_CDC_CONN_RX_SB_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_RX_SB_B2_CTL (0x3AF)
#define SITAR_A_CDC_CONN_RX_SB_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_CLSG_CTL (0x3B0)
#define SITAR_A_CDC_CONN_CLSG_CTL__POR (0x00000000)
#define SITAR_A_CDC_CONN_SPARE (0x3B1)
#define SITAR_A_CDC_CONN_SPARE__POR (0x00000000)
#define SITAR_A_CDC_MBHC_EN_CTL (0x3C0)
#define SITAR_A_CDC_MBHC_EN_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_FIR_B1_CFG (0x3C1)
#define SITAR_A_CDC_MBHC_FIR_B1_CFG__POR (0x00000000)
#define SITAR_A_CDC_MBHC_FIR_B2_CFG (0x3C2)
#define SITAR_A_CDC_MBHC_FIR_B2_CFG__POR (0x00000006)
#define SITAR_A_CDC_MBHC_TIMER_B1_CTL (0x3C3)
#define SITAR_A_CDC_MBHC_TIMER_B1_CTL__POR (0x00000003)
#define SITAR_A_CDC_MBHC_TIMER_B2_CTL (0x3C4)
#define SITAR_A_CDC_MBHC_TIMER_B2_CTL__POR (0x00000009)
#define SITAR_A_CDC_MBHC_TIMER_B3_CTL (0x3C5)
#define SITAR_A_CDC_MBHC_TIMER_B3_CTL__POR (0x0000001e)
#define SITAR_A_CDC_MBHC_TIMER_B4_CTL (0x3C6)
#define SITAR_A_CDC_MBHC_TIMER_B4_CTL__POR (0x00000045)
#define SITAR_A_CDC_MBHC_TIMER_B5_CTL (0x3C7)
#define SITAR_A_CDC_MBHC_TIMER_B5_CTL__POR (0x00000004)
#define SITAR_A_CDC_MBHC_TIMER_B6_CTL (0x3C8)
#define SITAR_A_CDC_MBHC_TIMER_B6_CTL__POR (0x00000078)
#define SITAR_A_CDC_MBHC_B1_STATUS (0x3C9)
#define SITAR_A_CDC_MBHC_B1_STATUS__POR (0x00000000)
#define SITAR_A_CDC_MBHC_B2_STATUS (0x3CA)
#define SITAR_A_CDC_MBHC_B2_STATUS__POR (0x00000000)
#define SITAR_A_CDC_MBHC_B3_STATUS (0x3CB)
#define SITAR_A_CDC_MBHC_B3_STATUS__POR (0x00000000)
#define SITAR_A_CDC_MBHC_B4_STATUS (0x3CC)
#define SITAR_A_CDC_MBHC_B4_STATUS__POR (0x00000000)
#define SITAR_A_CDC_MBHC_B5_STATUS (0x3CD)
#define SITAR_A_CDC_MBHC_B5_STATUS__POR (0x00000000)
#define SITAR_A_CDC_MBHC_B1_CTL (0x3CE)
#define SITAR_A_CDC_MBHC_B1_CTL__POR (0x000000c0)
#define SITAR_A_CDC_MBHC_B2_CTL (0x3CF)
#define SITAR_A_CDC_MBHC_B2_CTL__POR (0x0000005d)
#define SITAR_A_CDC_MBHC_VOLT_B1_CTL (0x3D0)
#define SITAR_A_CDC_MBHC_VOLT_B1_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_VOLT_B2_CTL (0x3D1)
#define SITAR_A_CDC_MBHC_VOLT_B2_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_VOLT_B3_CTL (0x3D2)
#define SITAR_A_CDC_MBHC_VOLT_B3_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_VOLT_B4_CTL (0x3D3)
#define SITAR_A_CDC_MBHC_VOLT_B4_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_VOLT_B5_CTL (0x3D4)
#define SITAR_A_CDC_MBHC_VOLT_B5_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_VOLT_B6_CTL (0x3D5)
#define SITAR_A_CDC_MBHC_VOLT_B6_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_VOLT_B7_CTL (0x3D6)
#define SITAR_A_CDC_MBHC_VOLT_B7_CTL__POR (0x000000ff)
#define SITAR_A_CDC_MBHC_VOLT_B8_CTL (0x3D7)
#define SITAR_A_CDC_MBHC_VOLT_B8_CTL__POR (0x00000007)
#define SITAR_A_CDC_MBHC_VOLT_B9_CTL (0x3D8)
#define SITAR_A_CDC_MBHC_VOLT_B9_CTL__POR (0x000000ff)
#define SITAR_A_CDC_MBHC_VOLT_B10_CTL (0x3D9)
#define SITAR_A_CDC_MBHC_VOLT_B10_CTL__POR (0x0000007f)
#define SITAR_A_CDC_MBHC_VOLT_B11_CTL (0x3DA)
#define SITAR_A_CDC_MBHC_VOLT_B11_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_VOLT_B12_CTL (0x3DB)
#define SITAR_A_CDC_MBHC_VOLT_B12_CTL__POR (0x00000080)
#define SITAR_A_CDC_MBHC_CLK_CTL (0x3DC)
#define SITAR_A_CDC_MBHC_CLK_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_INT_CTL (0x3DD)
#define SITAR_A_CDC_MBHC_INT_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_DEBUG_CTL (0x3DE)
#define SITAR_A_CDC_MBHC_DEBUG_CTL__POR (0x00000000)
#define SITAR_A_CDC_MBHC_SPARE (0x3DF)
#define SITAR_A_CDC_MBHC_SPARE__POR (0x00000000)
/* SLIMBUS Slave Registers */
#define SITAR_SLIM_PGD_PORT_INT_EN0 (0x30)
#define SITAR_SLIM_PGD_PORT_INT_STATUS0 (0x34)
#define SITAR_SLIM_PGD_PORT_INT_CLR0 (0x38)
#define SITAR_SLIM_PGD_PORT_INT_SOURCE0 (0x60)
/* Macros for Packing Register Writes into a U32 */
#define SITAR_PACKED_REG_SIZE sizeof(u32)
#define SITAR_CODEC_PACK_ENTRY(reg, mask, val) ((val & 0xff)|\
((mask & 0xff) << 8)|((reg & 0xffff) << 16))
#define SITAR_CODEC_UNPACK_ENTRY(packed, reg, mask, val) \
do { \
((reg) = ((packed >> 16) & (0xffff))); \
((mask) = ((packed >> 8) & (0xff))); \
((val) = ((packed) & (0xff))); \
} while (0);
#endif

3
sound/soc/codecs/Kconfig
View File

@@ -250,6 +250,9 @@ config SND_SOC_UDA134X
config SND_SOC_UDA1380
tristate
config SND_SOC_WCD9304
tristate
config SND_SOC_WCD9310
tristate

2
sound/soc/codecs/Makefile
View File

@@ -38,6 +38,7 @@ snd-soc-twl4030-objs := twl4030.o
snd-soc-twl6040-objs := twl6040.o
snd-soc-uda134x-objs := uda134x.o
snd-soc-uda1380-objs := uda1380.o
snd-soc-wcd9304-objs := wcd9304.o wcd9304-tables.o
snd-soc-wcd9310-objs := wcd9310.o wcd9310-tables.o
snd-soc-wl1273-objs := wl1273.o
snd-soc-wm1250-ev1-objs := wm1250-ev1.o
@@ -132,6 +133,7 @@ obj-$(CONFIG_SND_SOC_TWL4030) += snd-soc-twl4030.o
obj-$(CONFIG_SND_SOC_TWL6040) += snd-soc-twl6040.o
obj-$(CONFIG_SND_SOC_UDA134X) += snd-soc-uda134x.o
obj-$(CONFIG_SND_SOC_UDA1380) += snd-soc-uda1380.o
obj-$(CONFIG_SND_SOC_WCD9304) += snd-soc-wcd9304.o
obj-$(CONFIG_SND_SOC_WCD9310) += snd-soc-wcd9310.o
obj-$(CONFIG_SND_SOC_WL1273) += snd-soc-wl1273.o
obj-$(CONFIG_SND_SOC_WM1250_EV1) += snd-soc-wm1250-ev1.o

720
sound/soc/codecs/wcd9304-tables.c Normal file
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/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/mfd/wcd9xxx/wcd9xxx_registers.h>
#include <linux/mfd/wcd9xxx/wcd9304_registers.h>
#include "wcd9304.h"
const u8 sitar_reg_defaults[SITAR_CACHE_SIZE] = {
[WCD9XXX_A_CHIP_CTL] = WCD9XXX_A_CHIP_CTL__POR,
[WCD9XXX_A_CHIP_STATUS] = WCD9XXX_A_CHIP_STATUS__POR,
[WCD9XXX_A_CHIP_ID_BYTE_0] = WCD9XXX_A_CHIP_ID_BYTE_0__POR,
[WCD9XXX_A_CHIP_ID_BYTE_1] = WCD9XXX_A_CHIP_ID_BYTE_1__POR,
[WCD9XXX_A_CHIP_ID_BYTE_2] = WCD9XXX_A_CHIP_ID_BYTE_2__POR,
[WCD9XXX_A_CHIP_ID_BYTE_3] = WCD9XXX_A_CHIP_ID_BYTE_3__POR,
[WCD9XXX_A_CHIP_VERSION] = WCD9XXX_A_CHIP_VERSION__POR,
[WCD9XXX_A_SB_VERSION] = WCD9XXX_A_SB_VERSION__POR,
[WCD9XXX_A_SLAVE_ID_1] = WCD9XXX_A_SLAVE_ID_1__POR,
[WCD9XXX_A_SLAVE_ID_2] = WCD9XXX_A_SLAVE_ID_2__POR,
[WCD9XXX_A_SLAVE_ID_3] = WCD9XXX_A_SLAVE_ID_3__POR,
[SITAR_A_PIN_CTL_OE0] = SITAR_A_PIN_CTL_OE0__POR,
[SITAR_A_PIN_CTL_OE1] = SITAR_A_PIN_CTL_OE1__POR,
[SITAR_A_PIN_CTL_DATA0] = SITAR_A_PIN_CTL_DATA0__POR,
[SITAR_A_PIN_CTL_DATA1] = SITAR_A_PIN_CTL_DATA1__POR,
[SITAR_A_HDRIVE_GENERIC] = SITAR_A_HDRIVE_GENERIC__POR,
[SITAR_A_HDRIVE_OVERRIDE] = SITAR_A_HDRIVE_OVERRIDE__POR,
[SITAR_A_ANA_CSR_WAIT_STATE] = SITAR_A_ANA_CSR_WAIT_STATE__POR,
[SITAR_A_PROCESS_MONITOR_CTL0] = SITAR_A_PROCESS_MONITOR_CTL0__POR,
[SITAR_A_PROCESS_MONITOR_CTL1] = SITAR_A_PROCESS_MONITOR_CTL1__POR,
[SITAR_A_PROCESS_MONITOR_CTL2] = SITAR_A_PROCESS_MONITOR_CTL2__POR,
[SITAR_A_PROCESS_MONITOR_CTL3] = SITAR_A_PROCESS_MONITOR_CTL3__POR,
[SITAR_A_QFUSE_CTL] = SITAR_A_QFUSE_CTL__POR,
[SITAR_A_QFUSE_STATUS] = SITAR_A_QFUSE_STATUS__POR,
[SITAR_A_QFUSE_DATA_OUT0] = SITAR_A_QFUSE_DATA_OUT0__POR,
[SITAR_A_QFUSE_DATA_OUT1] = SITAR_A_QFUSE_DATA_OUT1__POR,
[SITAR_A_QFUSE_DATA_OUT2] = SITAR_A_QFUSE_DATA_OUT2__POR,
[SITAR_A_QFUSE_DATA_OUT3] = SITAR_A_QFUSE_DATA_OUT3__POR,
[SITAR_A_CDC_CTL] = SITAR_A_CDC_CTL__POR,
[SITAR_A_LEAKAGE_CTL] = SITAR_A_LEAKAGE_CTL__POR,
[SITAR_A_INTR_MODE] = SITAR_A_INTR_MODE__POR,
[SITAR_A_INTR_MASK0] = SITAR_A_INTR_MASK0__POR,
[SITAR_A_INTR_MASK1] = SITAR_A_INTR_MASK1__POR,
[SITAR_A_INTR_MASK2] = SITAR_A_INTR_MASK2__POR,
[SITAR_A_INTR_STATUS0] = SITAR_A_INTR_STATUS0__POR,
[SITAR_A_INTR_STATUS1] = SITAR_A_INTR_STATUS1__POR,
[SITAR_A_INTR_STATUS2] = SITAR_A_INTR_STATUS2__POR,
[SITAR_A_INTR_CLEAR0] = SITAR_A_INTR_CLEAR0__POR,
[SITAR_A_INTR_CLEAR1] = SITAR_A_INTR_CLEAR1__POR,
[SITAR_A_INTR_CLEAR2] = SITAR_A_INTR_CLEAR2__POR,
[SITAR_A_INTR_LEVEL0] = SITAR_A_INTR_LEVEL0__POR,
[SITAR_A_INTR_LEVEL1] = SITAR_A_INTR_LEVEL1__POR,
[SITAR_A_INTR_LEVEL2] = SITAR_A_INTR_LEVEL2__POR,
[SITAR_A_INTR_TEST0] = SITAR_A_INTR_TEST0__POR,
[SITAR_A_INTR_TEST1] = SITAR_A_INTR_TEST1__POR,
[SITAR_A_INTR_TEST2] = SITAR_A_INTR_TEST2__POR,
[SITAR_A_INTR_SET0] = SITAR_A_INTR_SET0__POR,
[SITAR_A_INTR_SET1] = SITAR_A_INTR_SET1__POR,
[SITAR_A_INTR_SET2] = SITAR_A_INTR_SET2__POR,
[SITAR_A_CDC_TX_I2S_SCK_MODE] = SITAR_A_CDC_TX_I2S_SCK_MODE__POR,
[SITAR_A_CDC_TX_I2S_WS_MODE] = SITAR_A_CDC_TX_I2S_WS_MODE__POR,
[SITAR_A_CDC_DMIC_DATA0_MODE] = SITAR_A_CDC_DMIC_DATA0_MODE__POR,
[SITAR_A_CDC_DMIC_CLK0_MODE] = SITAR_A_CDC_DMIC_CLK0_MODE__POR,
[SITAR_A_CDC_DMIC_DATA1_MODE] = SITAR_A_CDC_DMIC_DATA1_MODE__POR,
[SITAR_A_CDC_DMIC_CLK1_MODE] = SITAR_A_CDC_DMIC_CLK1_MODE__POR,
[SITAR_A_CDC_TX_I2S_SD0_MODE] = SITAR_A_CDC_TX_I2S_SD0_MODE__POR,
[SITAR_A_CDC_INTR_MODE] = SITAR_A_CDC_INTR_MODE__POR,
[SITAR_A_CDC_RX_I2S_SD0_MODE] = SITAR_A_CDC_RX_I2S_SD0_MODE__POR,
[SITAR_A_CDC_RX_I2S_SD1_MODE] = SITAR_A_CDC_RX_I2S_SD1_MODE__POR,
[SITAR_A_BIAS_REF_CTL] = SITAR_A_BIAS_REF_CTL__POR,
[SITAR_A_BIAS_CENTRAL_BG_CTL] = SITAR_A_BIAS_CENTRAL_BG_CTL__POR,
[SITAR_A_BIAS_PRECHRG_CTL] = SITAR_A_BIAS_PRECHRG_CTL__POR,
[SITAR_A_BIAS_CURR_CTL_1] = SITAR_A_BIAS_CURR_CTL_1__POR,
[SITAR_A_BIAS_CURR_CTL_2] = SITAR_A_BIAS_CURR_CTL_2__POR,
[SITAR_A_BIAS_OSC_BG_CTL] = SITAR_A_BIAS_OSC_BG_CTL__POR,
[SITAR_A_CLK_BUFF_EN1] = SITAR_A_CLK_BUFF_EN1__POR,
[SITAR_A_CLK_BUFF_EN2] = SITAR_A_CLK_BUFF_EN2__POR,
[SITAR_A_LDO_H_MODE_1] = SITAR_A_LDO_H_MODE_1__POR,
[SITAR_A_LDO_H_MODE_2] = SITAR_A_LDO_H_MODE_2__POR,
[SITAR_A_LDO_H_LOOP_CTL] = SITAR_A_LDO_H_LOOP_CTL__POR,
[SITAR_A_LDO_H_COMP_1] = SITAR_A_LDO_H_COMP_1__POR,
[SITAR_A_LDO_H_COMP_2] = SITAR_A_LDO_H_COMP_2__POR,
[SITAR_A_LDO_H_BIAS_1] = SITAR_A_LDO_H_BIAS_1__POR,
[SITAR_A_LDO_H_BIAS_2] = SITAR_A_LDO_H_BIAS_2__POR,
[SITAR_A_LDO_H_BIAS_3] = SITAR_A_LDO_H_BIAS_3__POR,
[SITAR_A_MICB_CFILT_1_CTL] = SITAR_A_MICB_CFILT_1_CTL__POR,
[SITAR_A_MICB_CFILT_1_VAL] = SITAR_A_MICB_CFILT_1_VAL__POR,
[SITAR_A_MICB_CFILT_1_PRECHRG] = SITAR_A_MICB_CFILT_1_PRECHRG__POR,
[SITAR_A_MICB_1_CTL] = SITAR_A_MICB_1_CTL__POR,
[SITAR_A_MICB_1_INT_RBIAS] = SITAR_A_MICB_1_INT_RBIAS__POR,
[SITAR_A_MICB_1_MBHC] = SITAR_A_MICB_1_MBHC__POR,
[SITAR_A_MICB_CFILT_2_CTL] = SITAR_A_MICB_CFILT_2_CTL__POR,
[SITAR_A_MICB_CFILT_2_VAL] = SITAR_A_MICB_CFILT_2_VAL__POR,
[SITAR_A_MICB_CFILT_2_PRECHRG] = SITAR_A_MICB_CFILT_2_PRECHRG__POR,
[SITAR_A_MICB_2_CTL] = SITAR_A_MICB_2_CTL__POR,
[SITAR_A_MICB_2_INT_RBIAS] = SITAR_A_MICB_2_INT_RBIAS__POR,
[SITAR_A_MICB_2_MBHC] = SITAR_A_MICB_2_MBHC__POR,
[SITAR_A_TX_COM_BIAS] = SITAR_A_TX_COM_BIAS__POR,
[SITAR_A_MBHC_SCALING_MUX_1] = SITAR_A_MBHC_SCALING_MUX_1__POR,
[SITAR_A_MBHC_SCALING_MUX_2] = SITAR_A_MBHC_SCALING_MUX_2__POR,
[SITAR_A_TX_SUP_SWITCH_CTRL_1] = SITAR_A_TX_SUP_SWITCH_CTRL_1__POR,
[SITAR_A_TX_SUP_SWITCH_CTRL_2] = SITAR_A_TX_SUP_SWITCH_CTRL_2__POR,
[SITAR_A_TX_1_2_EN] = SITAR_A_TX_1_2_EN__POR,
[SITAR_A_TX_1_2_TEST_EN] = SITAR_A_TX_1_2_TEST_EN__POR,
[SITAR_A_TX_1_2_ADC_CH1] = SITAR_A_TX_1_2_ADC_CH1__POR,
[SITAR_A_TX_1_2_ADC_CH2] = SITAR_A_TX_1_2_ADC_CH2__POR,
[SITAR_A_TX_1_2_ATEST_REFCTRL] = SITAR_A_TX_1_2_ATEST_REFCTRL__POR,
[SITAR_A_TX_1_2_TEST_CTL] = SITAR_A_TX_1_2_TEST_CTL__POR,
[SITAR_A_TX_1_2_TEST_BLOCK_EN] = SITAR_A_TX_1_2_TEST_BLOCK_EN__POR,
[SITAR_A_TX_1_2_TXFE_CLKDIV] = SITAR_A_TX_1_2_TXFE_CLKDIV__POR,
[SITAR_A_TX_1_2_SAR_ERR_CH1] = SITAR_A_TX_1_2_SAR_ERR_CH1__POR,
[SITAR_A_TX_1_2_SAR_ERR_CH2] = SITAR_A_TX_1_2_SAR_ERR_CH2__POR,
[SITAR_A_TX_3_EN] = SITAR_A_TX_3_EN__POR,
[SITAR_A_TX_3_TEST_EN] = SITAR_A_TX_3_TEST_EN__POR,
[SITAR_A_TX_3_ADC] = SITAR_A_TX_3_ADC__POR,
[SITAR_A_TX_3_MBHC_ATEST_REFCTRL] =
SITAR_A_TX_3_MBHC_ATEST_REFCTRL__POR,
[SITAR_A_TX_3_TEST_CTL] = SITAR_A_TX_3_TEST_CTL__POR,
[SITAR_A_TX_3_TEST_BLOCK_EN] = SITAR_A_TX_3_TEST_BLOCK_EN__POR,
[SITAR_A_TX_3_TXFE_CKDIV] = SITAR_A_TX_3_TXFE_CKDIV__POR,
[SITAR_A_TX_3_SAR_ERR] = SITAR_A_TX_3_SAR_ERR__POR,
[SITAR_A_TX_4_MBHC_EN] = SITAR_A_TX_4_MBHC_EN__POR,
[SITAR_A_TX_4_MBHC_ADC] = SITAR_A_TX_4_MBHC_ADC__POR,
[SITAR_A_TX_4_MBHC_TEST_CTL] = SITAR_A_TX_4_MBHC_TEST_CTL__POR,
[SITAR_A_TX_4_MBHC_SAR_ERR] = SITAR_A_TX_4_MBHC_SAR_ERR__POR,
[SITAR_A_TX_4_TXFE_CLKDIV] = SITAR_A_TX_4_TXFE_CLKDIV__POR,
[SITAR_A_AUX_COM_CTL] = SITAR_A_AUX_COM_CTL__POR,
[SITAR_A_AUX_COM_ATEST] = SITAR_A_AUX_COM_ATEST__POR,
[SITAR_A_AUX_L_EN] = SITAR_A_AUX_L_EN__POR,
[SITAR_A_AUX_L_GAIN] = SITAR_A_AUX_L_GAIN__POR,
[SITAR_A_AUX_L_PA_CONN] = SITAR_A_AUX_L_PA_CONN__POR,
[SITAR_A_AUX_L_PA_CONN_INV] = SITAR_A_AUX_L_PA_CONN_INV__POR,
[SITAR_A_AUX_R_EN] = SITAR_A_AUX_R_EN__POR,
[SITAR_A_AUX_R_GAIN] = SITAR_A_AUX_R_GAIN__POR,
[SITAR_A_AUX_R_PA_CONN] = SITAR_A_AUX_R_PA_CONN__POR,
[SITAR_A_AUX_R_PA_CONN_INV] = SITAR_A_AUX_R_PA_CONN_INV__POR,
[SITAR_A_CP_EN] = SITAR_A_CP_EN__POR,
[SITAR_A_CP_CLK] = SITAR_A_CP_CLK__POR,
[SITAR_A_CP_STATIC] = SITAR_A_CP_STATIC__POR,
[SITAR_A_CP_DCC1] = SITAR_A_CP_DCC1__POR,
[SITAR_A_CP_DCC3] = SITAR_A_CP_DCC3__POR,
[SITAR_A_CP_ATEST] = SITAR_A_CP_ATEST__POR,
[SITAR_A_CP_DTEST] = SITAR_A_CP_DTEST__POR,
[SITAR_A_RX_COM_TIMER_DIV] = SITAR_A_RX_COM_TIMER_DIV__POR,
[SITAR_A_RX_COM_OCP_CTL] = SITAR_A_RX_COM_OCP_CTL__POR,
[SITAR_A_RX_COM_OCP_COUNT] = SITAR_A_RX_COM_OCP_COUNT__POR,
[SITAR_A_RX_COM_DAC_CTL] = SITAR_A_RX_COM_DAC_CTL__POR,
[SITAR_A_RX_COM_BIAS] = SITAR_A_RX_COM_BIAS__POR,
[SITAR_A_RX_HPH_BIAS_PA] = SITAR_A_RX_HPH_BIAS_PA__POR,
[SITAR_A_RX_HPH_BIAS_LDO] = SITAR_A_RX_HPH_BIAS_LDO__POR,
[SITAR_A_RX_HPH_BIAS_CNP] = SITAR_A_RX_HPH_BIAS_CNP__POR,
[SITAR_A_RX_HPH_BIAS_WG] = SITAR_A_RX_HPH_BIAS_WG__POR,
[SITAR_A_RX_HPH_OCP_CTL] = SITAR_A_RX_HPH_OCP_CTL__POR,
[SITAR_A_RX_HPH_CNP_EN] = SITAR_A_RX_HPH_CNP_EN__POR,
[SITAR_A_RX_HPH_CNP_WG_CTL] = SITAR_A_RX_HPH_CNP_WG_CTL__POR,
[SITAR_A_RX_HPH_CNP_WG_TIME] = SITAR_A_RX_HPH_CNP_WG_TIME__POR,
[SITAR_A_RX_HPH_L_GAIN] = SITAR_A_RX_HPH_L_GAIN__POR,
[SITAR_A_RX_HPH_L_TEST] = SITAR_A_RX_HPH_L_TEST__POR,
[SITAR_A_RX_HPH_L_PA_CTL] = SITAR_A_RX_HPH_L_PA_CTL__POR,
[SITAR_A_RX_HPH_L_DAC_CTL] = SITAR_A_RX_HPH_L_DAC_CTL__POR,
[SITAR_A_RX_HPH_L_ATEST] = SITAR_A_RX_HPH_L_ATEST__POR,
[SITAR_A_RX_HPH_L_STATUS] = SITAR_A_RX_HPH_L_STATUS__POR,
[SITAR_A_RX_HPH_R_GAIN] = SITAR_A_RX_HPH_R_GAIN__POR,
[SITAR_A_RX_HPH_R_TEST] = SITAR_A_RX_HPH_R_TEST__POR,
[SITAR_A_RX_HPH_R_PA_CTL] = SITAR_A_RX_HPH_R_PA_CTL__POR,
[SITAR_A_RX_HPH_R_DAC_CTL] = SITAR_A_RX_HPH_R_DAC_CTL__POR,
[SITAR_A_RX_HPH_R_ATEST] = SITAR_A_RX_HPH_R_ATEST__POR,
[SITAR_A_RX_HPH_R_STATUS] = SITAR_A_RX_HPH_R_STATUS__POR,
[SITAR_A_RX_EAR_BIAS_PA] = SITAR_A_RX_EAR_BIAS_PA__POR,
[SITAR_A_RX_EAR_BIAS_CMBUFF] = SITAR_A_RX_EAR_BIAS_CMBUFF__POR,
[SITAR_A_RX_EAR_EN] = SITAR_A_RX_EAR_EN__POR,
[SITAR_A_RX_EAR_GAIN] = SITAR_A_RX_EAR_GAIN__POR,
[SITAR_A_RX_EAR_CMBUFF] = SITAR_A_RX_EAR_CMBUFF__POR,
[SITAR_A_RX_EAR_ICTL] = SITAR_A_RX_EAR_ICTL__POR,
[SITAR_A_RX_EAR_CCOMP] = SITAR_A_RX_EAR_CCOMP__POR,
[SITAR_A_RX_EAR_VCM] = SITAR_A_RX_EAR_VCM__POR,
[SITAR_A_RX_EAR_CNP] = SITAR_A_RX_EAR_CNP__POR,
[SITAR_A_RX_EAR_ATEST] = SITAR_A_RX_EAR_ATEST__POR,
[SITAR_A_RX_EAR_STATUS] = SITAR_A_RX_EAR_STATUS__POR,
[SITAR_A_RX_LINE_BIAS_PA] = SITAR_A_RX_LINE_BIAS_PA__POR,
[SITAR_A_RX_LINE_BIAS_LDO] = SITAR_A_RX_LINE_BIAS_LDO__POR,
[SITAR_A_RX_LINE_BIAS_CNP1] = SITAR_A_RX_LINE_BIAS_CNP1__POR,
[SITAR_A_RX_LINE_COM] = SITAR_A_RX_LINE_COM__POR,
[SITAR_A_RX_LINE_CNP_EN] = SITAR_A_RX_LINE_CNP_EN__POR,
[SITAR_A_RX_LINE_CNP_WG_CTL] = SITAR_A_RX_LINE_CNP_WG_CTL__POR,
[SITAR_A_RX_LINE_CNP_WG_TIME] = SITAR_A_RX_LINE_CNP_WG_TIME__POR,
[SITAR_A_RX_LINE_1_GAIN] = SITAR_A_RX_LINE_1_GAIN__POR,
[SITAR_A_RX_LINE_1_TEST] = SITAR_A_RX_LINE_1_TEST__POR,
[SITAR_A_RX_LINE_1_DAC_CTL] = SITAR_A_RX_LINE_1_DAC_CTL__POR,
[SITAR_A_RX_LINE_1_STATUS] = SITAR_A_RX_LINE_1_STATUS__POR,
[SITAR_A_RX_LINE_2_GAIN] = SITAR_A_RX_LINE_2_GAIN__POR,
[SITAR_A_RX_LINE_2_TEST] = SITAR_A_RX_LINE_2_TEST__POR,
[SITAR_A_RX_LINE_2_DAC_CTL] = SITAR_A_RX_LINE_2_DAC_CTL__POR,
[SITAR_A_RX_LINE_2_STATUS] = SITAR_A_RX_LINE_2_STATUS__POR,
[SITAR_A_RX_LINE_BIAS_CNP2] = SITAR_A_RX_LINE_BIAS_CNP2__POR,
[SITAR_A_RX_LINE_OCP_CTL] = SITAR_A_RX_LINE_OCP_CTL__POR,
[SITAR_A_RX_LINE_1_PA_CTL] = SITAR_A_RX_LINE_1_PA_CTL__POR,
[SITAR_A_RX_LINE_2_PA_CTL] = SITAR_A_RX_LINE_2_PA_CTL__POR,
[SITAR_A_RX_LINE_CNP_DBG] = SITAR_A_RX_LINE_CNP_DBG__POR,
[SITAR_A_MBHC_HPH] = SITAR_A_MBHC_HPH__POR,
[SITAR_A_RC_OSC_FREQ] = SITAR_A_RC_OSC_FREQ__POR,
[SITAR_A_RC_OSC_TEST] = SITAR_A_RC_OSC_TEST__POR,
[SITAR_A_RC_OSC_STATUS] = SITAR_A_RC_OSC_STATUS__POR,
[SITAR_A_RC_OSC_TUNER] = SITAR_A_RC_OSC_TUNER__POR,
[SITAR_A_CDC_ANC1_CTL] = SITAR_A_CDC_ANC1_CTL__POR,
[SITAR_A_CDC_ANC1_SHIFT] = SITAR_A_CDC_ANC1_SHIFT__POR,
[SITAR_A_CDC_ANC1_IIR_B1_CTL] = SITAR_A_CDC_ANC1_IIR_B1_CTL__POR,
[SITAR_A_CDC_ANC1_IIR_B2_CTL] = SITAR_A_CDC_ANC1_IIR_B2_CTL__POR,
[SITAR_A_CDC_ANC1_IIR_B3_CTL] = SITAR_A_CDC_ANC1_IIR_B3_CTL__POR,
[SITAR_A_CDC_ANC1_IIR_B4_CTL] = SITAR_A_CDC_ANC1_IIR_B4_CTL__POR,
[SITAR_A_CDC_ANC1_LPF_B1_CTL] = SITAR_A_CDC_ANC1_LPF_B1_CTL__POR,
[SITAR_A_CDC_ANC1_LPF_B2_CTL] = SITAR_A_CDC_ANC1_LPF_B2_CTL__POR,
[SITAR_A_CDC_ANC1_LPF_B3_CTL] = SITAR_A_CDC_ANC1_LPF_B3_CTL__POR,
[SITAR_A_CDC_ANC1_SPARE] = SITAR_A_CDC_ANC1_SPARE__POR,
[SITAR_A_CDC_ANC1_SMLPF_CTL] = SITAR_A_CDC_ANC1_SMLPF_CTL__POR,
[SITAR_A_CDC_ANC1_DCFLT_CTL] = SITAR_A_CDC_ANC1_DCFLT_CTL__POR,
[SITAR_A_CDC_TX1_VOL_CTL_TIMER] = SITAR_A_CDC_TX1_VOL_CTL_TIMER__POR,
[SITAR_A_CDC_TX1_VOL_CTL_GAIN] = SITAR_A_CDC_TX1_VOL_CTL_GAIN__POR,
[SITAR_A_CDC_TX1_VOL_CTL_CFG] = SITAR_A_CDC_TX1_VOL_CTL_CFG__POR,
[SITAR_A_CDC_TX1_MUX_CTL] = SITAR_A_CDC_TX1_MUX_CTL__POR,
[SITAR_A_CDC_TX1_CLK_FS_CTL] = SITAR_A_CDC_TX1_CLK_FS_CTL__POR,
[SITAR_A_CDC_TX1_DMIC_CTL] = SITAR_A_CDC_TX1_DMIC_CTL__POR,
[SITAR_A_CDC_SRC1_PDA_CFG] = SITAR_A_CDC_SRC1_PDA_CFG__POR,
[SITAR_A_CDC_SRC1_FS_CTL] = SITAR_A_CDC_SRC1_FS_CTL__POR,
[SITAR_A_CDC_RX1_B1_CTL] = SITAR_A_CDC_RX1_B1_CTL__POR,
[SITAR_A_CDC_RX1_B2_CTL] = SITAR_A_CDC_RX1_B2_CTL__POR,
[SITAR_A_CDC_RX1_B3_CTL] = SITAR_A_CDC_RX1_B3_CTL__POR,
[SITAR_A_CDC_RX1_B4_CTL] = SITAR_A_CDC_RX1_B4_CTL__POR,
[SITAR_A_CDC_RX1_B5_CTL] = SITAR_A_CDC_RX1_B5_CTL__POR,
[SITAR_A_CDC_RX1_B6_CTL] = SITAR_A_CDC_RX1_B6_CTL__POR,
[SITAR_A_CDC_RX1_VOL_CTL_B1_CTL] = SITAR_A_CDC_RX1_VOL_CTL_B1_CTL__POR,
[SITAR_A_CDC_RX1_VOL_CTL_B2_CTL] = SITAR_A_CDC_RX1_VOL_CTL_B2_CTL__POR,
[SITAR_A_CDC_CLK_ANC_RESET_CTL] = SITAR_A_CDC_CLK_ANC_RESET_CTL__POR,
[SITAR_A_CDC_CLK_RX_RESET_CTL] = SITAR_A_CDC_CLK_RX_RESET_CTL__POR,
[SITAR_A_CDC_CLK_TX_RESET_B1_CTL] =
SITAR_A_CDC_CLK_TX_RESET_B1_CTL__POR,
[SITAR_A_CDC_CLK_TX_RESET_B2_CTL] =
SITAR_A_CDC_CLK_TX_RESET_B2_CTL__POR,
[SITAR_A_CDC_CLK_DMIC_CTL] = SITAR_A_CDC_CLK_DMIC_CTL__POR,
[SITAR_A_CDC_CLK_RX_I2S_CTL] = SITAR_A_CDC_CLK_RX_I2S_CTL__POR,
[SITAR_A_CDC_CLK_TX_I2S_CTL] = SITAR_A_CDC_CLK_TX_I2S_CTL__POR,
[SITAR_A_CDC_CLK_OTHR_RESET_CTL] = SITAR_A_CDC_CLK_OTHR_RESET_CTL__POR,
[SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL] =
SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL__POR,
[SITAR_A_CDC_CLK_OTHR_CTL] = SITAR_A_CDC_CLK_OTHR_CTL__POR,
[SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL] =
SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL__POR,
[SITAR_A_CDC_CLK_ANC_CLK_EN_CTL] = SITAR_A_CDC_CLK_ANC_CLK_EN_CTL__POR,
[SITAR_A_CDC_CLK_RX_B1_CTL] = SITAR_A_CDC_CLK_RX_B1_CTL__POR,
[SITAR_A_CDC_CLK_RX_B2_CTL] = SITAR_A_CDC_CLK_RX_B2_CTL__POR,
[SITAR_A_CDC_CLK_MCLK_CTL] = SITAR_A_CDC_CLK_MCLK_CTL__POR,
[SITAR_A_CDC_CLK_PDM_CTL] = SITAR_A_CDC_CLK_PDM_CTL__POR,
[SITAR_A_CDC_CLK_SD_CTL] = SITAR_A_CDC_CLK_SD_CTL__POR,
[SITAR_A_CDC_CLK_LP_CTL] = SITAR_A_CDC_CLK_LP_CTL__POR,
[SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL] =
SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL__POR,
[SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL] =
SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL__POR,
[SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL] =
SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL__POR,
[SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL] =
SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL__POR,
[SITAR_A_CDC_CLSG_GAIN_THRESH_CTL] =
SITAR_A_CDC_CLSG_GAIN_THRESH_CTL__POR,
[SITAR_A_CDC_CLSG_TIMER_B1_CFG] = SITAR_A_CDC_CLSG_TIMER_B1_CFG__POR,
[SITAR_A_CDC_CLSG_TIMER_B2_CFG] = SITAR_A_CDC_CLSG_TIMER_B2_CFG__POR,
[SITAR_A_CDC_CLSG_CTL] = SITAR_A_CDC_CLSG_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_B1_CTL] = SITAR_A_CDC_IIR1_GAIN_B1_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_B2_CTL] = SITAR_A_CDC_IIR1_GAIN_B2_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_B3_CTL] = SITAR_A_CDC_IIR1_GAIN_B3_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_B4_CTL] = SITAR_A_CDC_IIR1_GAIN_B4_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_B5_CTL] = SITAR_A_CDC_IIR1_GAIN_B5_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_B6_CTL] = SITAR_A_CDC_IIR1_GAIN_B6_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_B7_CTL] = SITAR_A_CDC_IIR1_GAIN_B7_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_B8_CTL] = SITAR_A_CDC_IIR1_GAIN_B8_CTL__POR,
[SITAR_A_CDC_IIR1_CTL] = SITAR_A_CDC_IIR1_CTL__POR,
[SITAR_A_CDC_IIR1_GAIN_TIMER_CTL] =
SITAR_A_CDC_IIR1_GAIN_TIMER_CTL__POR,
[SITAR_A_CDC_IIR1_COEF_B1_CTL] = SITAR_A_CDC_IIR1_COEF_B1_CTL__POR,
[SITAR_A_CDC_IIR1_COEF_B2_CTL] = SITAR_A_CDC_IIR1_COEF_B2_CTL__POR,
[SITAR_A_CDC_IIR1_COEF_B3_CTL] = SITAR_A_CDC_IIR1_COEF_B3_CTL__POR,
[SITAR_A_CDC_IIR1_COEF_B4_CTL] = SITAR_A_CDC_IIR1_COEF_B4_CTL__POR,
[SITAR_A_CDC_IIR1_COEF_B5_CTL] = SITAR_A_CDC_IIR1_COEF_B5_CTL__POR,
[SITAR_A_CDC_TOP_GAIN_UPDATE] = SITAR_A_CDC_TOP_GAIN_UPDATE__POR,
[SITAR_A_CDC_TOP_RDAC_DOUT_CTL] = SITAR_A_CDC_TOP_RDAC_DOUT_CTL__POR,
[SITAR_A_CDC_DEBUG_B1_CTL] = SITAR_A_CDC_DEBUG_B1_CTL__POR,
[SITAR_A_CDC_DEBUG_B2_CTL] = SITAR_A_CDC_DEBUG_B2_CTL__POR,
[SITAR_A_CDC_DEBUG_B3_CTL] = SITAR_A_CDC_DEBUG_B3_CTL__POR,
[SITAR_A_CDC_DEBUG_B4_CTL] = SITAR_A_CDC_DEBUG_B4_CTL__POR,
[SITAR_A_CDC_DEBUG_B5_CTL] = SITAR_A_CDC_DEBUG_B5_CTL__POR,
[SITAR_A_CDC_DEBUG_B6_CTL] = SITAR_A_CDC_DEBUG_B6_CTL__POR,
[SITAR_A_CDC_DEBUG_B7_CTL] = SITAR_A_CDC_DEBUG_B7_CTL__POR,
[SITAR_A_CDC_COMP1_B1_CTL] = SITAR_A_CDC_COMP1_B1_CTL__POR,
[SITAR_A_CDC_COMP1_B2_CTL] = SITAR_A_CDC_COMP1_B2_CTL__POR,
[SITAR_A_CDC_COMP1_B3_CTL] = SITAR_A_CDC_COMP1_B3_CTL__POR,
[SITAR_A_CDC_COMP1_B4_CTL] = SITAR_A_CDC_COMP1_B4_CTL__POR,
[SITAR_A_CDC_COMP1_B5_CTL] = SITAR_A_CDC_COMP1_B5_CTL__POR,
[SITAR_A_CDC_COMP1_B6_CTL] = SITAR_A_CDC_COMP1_B6_CTL__POR,
[SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS] =
SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS__POR,
[SITAR_A_CDC_COMP1_FS_CFG] = SITAR_A_CDC_COMP1_FS_CFG__POR,
[SITAR_A_CDC_CONN_RX1_B1_CTL] = SITAR_A_CDC_CONN_RX1_B1_CTL__POR,
[SITAR_A_CDC_CONN_RX1_B2_CTL] = SITAR_A_CDC_CONN_RX1_B2_CTL__POR,
[SITAR_A_CDC_CONN_RX1_B3_CTL] = SITAR_A_CDC_CONN_RX1_B3_CTL__POR,
[SITAR_A_CDC_CONN_RX2_B1_CTL] = SITAR_A_CDC_CONN_RX2_B1_CTL__POR,
[SITAR_A_CDC_CONN_RX2_B2_CTL] = SITAR_A_CDC_CONN_RX2_B2_CTL__POR,
[SITAR_A_CDC_CONN_RX2_B3_CTL] = SITAR_A_CDC_CONN_RX2_B3_CTL__POR,
[SITAR_A_CDC_CONN_RX3_B1_CTL] = SITAR_A_CDC_CONN_RX3_B1_CTL__POR,
[SITAR_A_CDC_CONN_RX3_B2_CTL] = SITAR_A_CDC_CONN_RX3_B2_CTL__POR,
[SITAR_A_CDC_CONN_RX3_B3_CTL] = SITAR_A_CDC_CONN_RX3_B3_CTL__POR,
[SITAR_A_CDC_CONN_ANC_B1_CTL] = SITAR_A_CDC_CONN_ANC_B1_CTL__POR,
[SITAR_A_CDC_CONN_ANC_B2_CTL] = SITAR_A_CDC_CONN_ANC_B2_CTL__POR,
[SITAR_A_CDC_CONN_TX_B1_CTL] = SITAR_A_CDC_CONN_TX_B1_CTL__POR,
[SITAR_A_CDC_CONN_TX_B2_CTL] = SITAR_A_CDC_CONN_TX_B2_CTL__POR,
[SITAR_A_CDC_CONN_EQ1_B1_CTL] = SITAR_A_CDC_CONN_EQ1_B1_CTL__POR,
[SITAR_A_CDC_CONN_EQ1_B2_CTL] = SITAR_A_CDC_CONN_EQ1_B2_CTL__POR,
[SITAR_A_CDC_CONN_EQ1_B3_CTL] = SITAR_A_CDC_CONN_EQ1_B3_CTL__POR,
[SITAR_A_CDC_CONN_EQ1_B4_CTL] = SITAR_A_CDC_CONN_EQ1_B4_CTL__POR,
[SITAR_A_CDC_CONN_EQ2_B1_CTL] = SITAR_A_CDC_CONN_EQ2_B1_CTL__POR,
[SITAR_A_CDC_CONN_EQ2_B2_CTL] = SITAR_A_CDC_CONN_EQ2_B2_CTL__POR,
[SITAR_A_CDC_CONN_EQ2_B3_CTL] = SITAR_A_CDC_CONN_EQ2_B3_CTL__POR,
[SITAR_A_CDC_CONN_EQ2_B4_CTL] = SITAR_A_CDC_CONN_EQ2_B4_CTL__POR,
[SITAR_A_CDC_CONN_SRC1_B1_CTL] = SITAR_A_CDC_CONN_SRC1_B1_CTL__POR,
[SITAR_A_CDC_CONN_SRC1_B2_CTL] = SITAR_A_CDC_CONN_SRC1_B2_CTL__POR,
[SITAR_A_CDC_CONN_SRC2_B1_CTL] = SITAR_A_CDC_CONN_SRC2_B1_CTL__POR,
[SITAR_A_CDC_CONN_SRC2_B2_CTL] = SITAR_A_CDC_CONN_SRC2_B2_CTL__POR,
[SITAR_A_CDC_CONN_TX_SB_B1_CTL] = SITAR_A_CDC_CONN_TX_SB_B1_CTL__POR,
[SITAR_A_CDC_CONN_TX_SB_B2_CTL] = SITAR_A_CDC_CONN_TX_SB_B2_CTL__POR,
[SITAR_A_CDC_CONN_TX_SB_B3_CTL] = SITAR_A_CDC_CONN_TX_SB_B3_CTL__POR,
[SITAR_A_CDC_CONN_TX_SB_B4_CTL] = SITAR_A_CDC_CONN_TX_SB_B4_CTL__POR,
[SITAR_A_CDC_CONN_TX_SB_B5_CTL] = SITAR_A_CDC_CONN_TX_SB_B5_CTL__POR,
[SITAR_A_CDC_CONN_RX_SB_B1_CTL] = SITAR_A_CDC_CONN_RX_SB_B1_CTL__POR,
[SITAR_A_CDC_CONN_RX_SB_B2_CTL] = SITAR_A_CDC_CONN_RX_SB_B2_CTL__POR,
[SITAR_A_CDC_CONN_CLSG_CTL] = SITAR_A_CDC_CONN_CLSG_CTL__POR,
[SITAR_A_CDC_CONN_SPARE] = SITAR_A_CDC_CONN_SPARE__POR,
[SITAR_A_CDC_MBHC_EN_CTL] = SITAR_A_CDC_MBHC_EN_CTL__POR,
[SITAR_A_CDC_MBHC_FIR_B1_CFG] = SITAR_A_CDC_MBHC_FIR_B1_CFG__POR,
[SITAR_A_CDC_MBHC_FIR_B2_CFG] = SITAR_A_CDC_MBHC_FIR_B2_CFG__POR,
[SITAR_A_CDC_MBHC_TIMER_B1_CTL] = SITAR_A_CDC_MBHC_TIMER_B1_CTL__POR,
[SITAR_A_CDC_MBHC_TIMER_B2_CTL] = SITAR_A_CDC_MBHC_TIMER_B2_CTL__POR,
[SITAR_A_CDC_MBHC_TIMER_B3_CTL] = SITAR_A_CDC_MBHC_TIMER_B3_CTL__POR,
[SITAR_A_CDC_MBHC_TIMER_B4_CTL] = SITAR_A_CDC_MBHC_TIMER_B4_CTL__POR,
[SITAR_A_CDC_MBHC_TIMER_B5_CTL] = SITAR_A_CDC_MBHC_TIMER_B5_CTL__POR,
[SITAR_A_CDC_MBHC_TIMER_B6_CTL] = SITAR_A_CDC_MBHC_TIMER_B6_CTL__POR,
[SITAR_A_CDC_MBHC_B1_STATUS] = SITAR_A_CDC_MBHC_B1_STATUS__POR,
[SITAR_A_CDC_MBHC_B2_STATUS] = SITAR_A_CDC_MBHC_B2_STATUS__POR,
[SITAR_A_CDC_MBHC_B3_STATUS] = SITAR_A_CDC_MBHC_B3_STATUS__POR,
[SITAR_A_CDC_MBHC_B4_STATUS] = SITAR_A_CDC_MBHC_B4_STATUS__POR,
[SITAR_A_CDC_MBHC_B5_STATUS] = SITAR_A_CDC_MBHC_B5_STATUS__POR,
[SITAR_A_CDC_MBHC_B1_CTL] = SITAR_A_CDC_MBHC_B1_CTL__POR,
[SITAR_A_CDC_MBHC_B2_CTL] = SITAR_A_CDC_MBHC_B2_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B1_CTL] = SITAR_A_CDC_MBHC_VOLT_B1_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B2_CTL] = SITAR_A_CDC_MBHC_VOLT_B2_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B3_CTL] = SITAR_A_CDC_MBHC_VOLT_B3_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B4_CTL] = SITAR_A_CDC_MBHC_VOLT_B4_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B5_CTL] = SITAR_A_CDC_MBHC_VOLT_B5_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B6_CTL] = SITAR_A_CDC_MBHC_VOLT_B6_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B7_CTL] = SITAR_A_CDC_MBHC_VOLT_B7_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B8_CTL] = SITAR_A_CDC_MBHC_VOLT_B8_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B9_CTL] = SITAR_A_CDC_MBHC_VOLT_B9_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B10_CTL] = SITAR_A_CDC_MBHC_VOLT_B10_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B11_CTL] = SITAR_A_CDC_MBHC_VOLT_B11_CTL__POR,
[SITAR_A_CDC_MBHC_VOLT_B12_CTL] = SITAR_A_CDC_MBHC_VOLT_B12_CTL__POR,
[SITAR_A_CDC_MBHC_CLK_CTL] = SITAR_A_CDC_MBHC_CLK_CTL__POR,
[SITAR_A_CDC_MBHC_INT_CTL] = SITAR_A_CDC_MBHC_INT_CTL__POR,
[SITAR_A_CDC_MBHC_DEBUG_CTL] = SITAR_A_CDC_MBHC_DEBUG_CTL__POR,
[SITAR_A_CDC_MBHC_SPARE] = SITAR_A_CDC_MBHC_SPARE__POR,
};
const u8 sitar_reg_readable[SITAR_CACHE_SIZE] = {
[WCD9XXX_A_CHIP_CTL] = 1,
[WCD9XXX_A_CHIP_STATUS] = 1,
[WCD9XXX_A_CHIP_ID_BYTE_0] = 1,
[WCD9XXX_A_CHIP_ID_BYTE_1] = 1,
[WCD9XXX_A_CHIP_ID_BYTE_2] = 1,
[WCD9XXX_A_CHIP_ID_BYTE_3] = 1,
[WCD9XXX_A_CHIP_VERSION] = 1,
[WCD9XXX_A_SB_VERSION] = 1,
[WCD9XXX_A_SLAVE_ID_1] = 1,
[WCD9XXX_A_SLAVE_ID_2] = 1,
[WCD9XXX_A_SLAVE_ID_3] = 1,
[SITAR_A_PIN_CTL_OE0] = 1,
[SITAR_A_PIN_CTL_OE1] = 1,
[SITAR_A_PIN_CTL_DATA0] = 1,
[SITAR_A_PIN_CTL_DATA1] = 1,
[SITAR_A_HDRIVE_GENERIC] = 1,
[SITAR_A_HDRIVE_OVERRIDE] = 1,
[SITAR_A_ANA_CSR_WAIT_STATE] = 1,
[SITAR_A_PROCESS_MONITOR_CTL0] = 1,
[SITAR_A_PROCESS_MONITOR_CTL1] = 1,
[SITAR_A_PROCESS_MONITOR_CTL2] = 1,
[SITAR_A_PROCESS_MONITOR_CTL3] = 1,
[SITAR_A_QFUSE_CTL] = 1,
[SITAR_A_QFUSE_STATUS] = 1,
[SITAR_A_QFUSE_DATA_OUT0] = 1,
[SITAR_A_QFUSE_DATA_OUT1] = 1,
[SITAR_A_QFUSE_DATA_OUT2] = 1,
[SITAR_A_QFUSE_DATA_OUT3] = 1,
[SITAR_A_CDC_CTL] = 1,
[SITAR_A_LEAKAGE_CTL] = 1,
[SITAR_A_INTR_MODE] = 1,
[SITAR_A_INTR_MASK0] = 1,
[SITAR_A_INTR_MASK1] = 1,
[SITAR_A_INTR_MASK2] = 1,
[SITAR_A_INTR_STATUS0] = 1,
[SITAR_A_INTR_STATUS1] = 1,
[SITAR_A_INTR_STATUS2] = 1,
[SITAR_A_INTR_LEVEL0] = 1,
[SITAR_A_INTR_LEVEL1] = 1,
[SITAR_A_INTR_LEVEL2] = 1,
[SITAR_A_INTR_TEST0] = 1,
[SITAR_A_INTR_TEST1] = 1,
[SITAR_A_INTR_TEST2] = 1,
[SITAR_A_INTR_SET0] = 1,
[SITAR_A_INTR_SET1] = 1,
[SITAR_A_INTR_SET2] = 1,
[SITAR_A_CDC_TX_I2S_SCK_MODE] = 1,
[SITAR_A_CDC_TX_I2S_WS_MODE] = 1,
[SITAR_A_CDC_DMIC_DATA0_MODE] = 1,
[SITAR_A_CDC_DMIC_CLK0_MODE] = 1,
[SITAR_A_CDC_DMIC_DATA1_MODE] = 1,
[SITAR_A_CDC_DMIC_CLK1_MODE] = 1,
[SITAR_A_CDC_TX_I2S_SD0_MODE] = 1,
[SITAR_A_CDC_INTR_MODE] = 1,
[SITAR_A_CDC_RX_I2S_SD0_MODE] = 1,
[SITAR_A_CDC_RX_I2S_SD1_MODE] = 1,
[SITAR_A_BIAS_REF_CTL] = 1,
[SITAR_A_BIAS_CENTRAL_BG_CTL] = 1,
[SITAR_A_BIAS_PRECHRG_CTL] = 1,
[SITAR_A_BIAS_CURR_CTL_1] = 1,
[SITAR_A_BIAS_CURR_CTL_2] = 1,
[SITAR_A_BIAS_OSC_BG_CTL] = 1,
[SITAR_A_CLK_BUFF_EN1] = 1,
[SITAR_A_CLK_BUFF_EN2] = 1,
[SITAR_A_LDO_H_MODE_1] = 1,
[SITAR_A_LDO_H_MODE_2] = 1,
[SITAR_A_LDO_H_LOOP_CTL] = 1,
[SITAR_A_LDO_H_COMP_1] = 1,
[SITAR_A_LDO_H_COMP_2] = 1,
[SITAR_A_LDO_H_BIAS_1] = 1,
[SITAR_A_LDO_H_BIAS_2] = 1,
[SITAR_A_LDO_H_BIAS_3] = 1,
[SITAR_A_MICB_CFILT_1_CTL] = 1,
[SITAR_A_MICB_CFILT_1_VAL] = 1,
[SITAR_A_MICB_CFILT_1_PRECHRG] = 1,
[SITAR_A_MICB_1_CTL] = 1,
[SITAR_A_MICB_1_INT_RBIAS] = 1,
[SITAR_A_MICB_1_MBHC] = 1,
[SITAR_A_MICB_CFILT_2_CTL] = 1,
[SITAR_A_MICB_CFILT_2_VAL] = 1,
[SITAR_A_MICB_CFILT_2_PRECHRG] = 1,
[SITAR_A_MICB_2_CTL] = 1,
[SITAR_A_MICB_2_INT_RBIAS] = 1,
[SITAR_A_MICB_2_MBHC] = 1,
[SITAR_A_TX_COM_BIAS] = 1,
[SITAR_A_MBHC_SCALING_MUX_1] = 1,
[SITAR_A_MBHC_SCALING_MUX_2] = 1,
[SITAR_A_TX_SUP_SWITCH_CTRL_1] = 1,
[SITAR_A_TX_SUP_SWITCH_CTRL_2] = 1,
[SITAR_A_TX_1_2_EN] = 1,
[SITAR_A_TX_1_2_TEST_EN] = 1,
[SITAR_A_TX_1_2_ADC_CH1] = 1,
[SITAR_A_TX_1_2_ADC_CH2] = 1,
[SITAR_A_TX_1_2_ATEST_REFCTRL] = 1,
[SITAR_A_TX_1_2_TEST_CTL] = 1,
[SITAR_A_TX_1_2_TEST_BLOCK_EN] = 1,
[SITAR_A_TX_1_2_TXFE_CLKDIV] = 1,
[SITAR_A_TX_1_2_SAR_ERR_CH1] = 1,
[SITAR_A_TX_1_2_SAR_ERR_CH2] = 1,
[SITAR_A_TX_3_EN] = 1,
[SITAR_A_TX_3_TEST_EN] = 1,
[SITAR_A_TX_3_ADC] = 1,
[SITAR_A_TX_3_MBHC_ATEST_REFCTRL] = 1,
[SITAR_A_TX_3_TEST_CTL] = 1,
[SITAR_A_TX_3_TEST_BLOCK_EN] = 1,
[SITAR_A_TX_3_TXFE_CKDIV] = 1,
[SITAR_A_TX_3_SAR_ERR] = 1,
[SITAR_A_TX_4_MBHC_EN] = 1,
[SITAR_A_TX_4_MBHC_ADC] = 1,
[SITAR_A_TX_4_MBHC_TEST_CTL] = 1,
[SITAR_A_TX_4_MBHC_SAR_ERR] = 1,
[SITAR_A_TX_4_TXFE_CLKDIV] = 1,
[SITAR_A_AUX_COM_CTL] = 1,
[SITAR_A_AUX_COM_ATEST] = 1,
[SITAR_A_AUX_L_EN] = 1,
[SITAR_A_AUX_L_GAIN] = 1,
[SITAR_A_AUX_L_PA_CONN] = 1,
[SITAR_A_AUX_L_PA_CONN_INV] = 1,
[SITAR_A_AUX_R_EN] = 1,
[SITAR_A_AUX_R_GAIN] = 1,
[SITAR_A_AUX_R_PA_CONN] = 1,
[SITAR_A_AUX_R_PA_CONN_INV] = 1,
[SITAR_A_CP_EN] = 1,
[SITAR_A_CP_CLK] = 1,
[SITAR_A_CP_STATIC] = 1,
[SITAR_A_CP_DCC1] = 1,
[SITAR_A_CP_DCC3] = 1,
[SITAR_A_CP_ATEST] = 1,
[SITAR_A_CP_DTEST] = 1,
[SITAR_A_RX_COM_TIMER_DIV] = 1,
[SITAR_A_RX_COM_OCP_CTL] = 1,
[SITAR_A_RX_COM_OCP_COUNT] = 1,
[SITAR_A_RX_COM_DAC_CTL] = 1,
[SITAR_A_RX_COM_BIAS] = 1,
[SITAR_A_RX_HPH_BIAS_PA] = 1,
[SITAR_A_RX_HPH_BIAS_LDO] = 1,
[SITAR_A_RX_HPH_BIAS_CNP] = 1,
[SITAR_A_RX_HPH_BIAS_WG] = 1,
[SITAR_A_RX_HPH_OCP_CTL] = 1,
[SITAR_A_RX_HPH_CNP_EN] = 1,
[SITAR_A_RX_HPH_CNP_WG_CTL] = 1,
[SITAR_A_RX_HPH_CNP_WG_TIME] = 1,
[SITAR_A_RX_HPH_L_GAIN] = 1,
[SITAR_A_RX_HPH_L_TEST] = 1,
[SITAR_A_RX_HPH_L_PA_CTL] = 1,
[SITAR_A_RX_HPH_L_DAC_CTL] = 1,
[SITAR_A_RX_HPH_L_ATEST] = 1,
[SITAR_A_RX_HPH_L_STATUS] = 1,
[SITAR_A_RX_HPH_R_GAIN] = 1,
[SITAR_A_RX_HPH_R_TEST] = 1,
[SITAR_A_RX_HPH_R_PA_CTL] = 1,
[SITAR_A_RX_HPH_R_DAC_CTL] = 1,
[SITAR_A_RX_HPH_R_ATEST] = 1,
[SITAR_A_RX_HPH_R_STATUS] = 1,
[SITAR_A_RX_EAR_BIAS_PA] = 1,
[SITAR_A_RX_EAR_BIAS_CMBUFF] = 1,
[SITAR_A_RX_EAR_EN] = 1,
[SITAR_A_RX_EAR_GAIN] = 1,
[SITAR_A_RX_EAR_CMBUFF] = 1,
[SITAR_A_RX_EAR_ICTL] = 1,
[SITAR_A_RX_EAR_CCOMP] = 1,
[SITAR_A_RX_EAR_VCM] = 1,
[SITAR_A_RX_EAR_CNP] = 1,
[SITAR_A_RX_EAR_ATEST] = 1,
[SITAR_A_RX_EAR_STATUS] = 1,
[SITAR_A_RX_LINE_BIAS_PA] = 1,
[SITAR_A_RX_LINE_BIAS_LDO] = 1,
[SITAR_A_RX_LINE_BIAS_CNP1] = 1,
[SITAR_A_RX_LINE_COM] = 1,
[SITAR_A_RX_LINE_CNP_EN] = 1,
[SITAR_A_RX_LINE_CNP_WG_CTL] = 1,
[SITAR_A_RX_LINE_CNP_WG_TIME] = 1,
[SITAR_A_RX_LINE_1_GAIN] = 1,
[SITAR_A_RX_LINE_1_TEST] = 1,
[SITAR_A_RX_LINE_1_DAC_CTL] = 1,
[SITAR_A_RX_LINE_1_STATUS] = 1,
[SITAR_A_RX_LINE_2_GAIN] = 1,
[SITAR_A_RX_LINE_2_TEST] = 1,
[SITAR_A_RX_LINE_2_DAC_CTL] = 1,
[SITAR_A_RX_LINE_2_STATUS] = 1,
[SITAR_A_RX_LINE_BIAS_CNP2] = 1,
[SITAR_A_RX_LINE_OCP_CTL] = 1,
[SITAR_A_RX_LINE_1_PA_CTL] = 1,
[SITAR_A_RX_LINE_2_PA_CTL] = 1,
[SITAR_A_RX_LINE_CNP_DBG] = 1,
[SITAR_A_MBHC_HPH] = 1,
[SITAR_A_RC_OSC_FREQ] = 1,
[SITAR_A_RC_OSC_TEST] = 1,
[SITAR_A_RC_OSC_STATUS] = 1,
[SITAR_A_RC_OSC_TUNER] = 1,
[SITAR_A_CDC_ANC1_CTL] = 1,
[SITAR_A_CDC_ANC1_SHIFT] = 1,
[SITAR_A_CDC_ANC1_IIR_B1_CTL] = 1,
[SITAR_A_CDC_ANC1_IIR_B2_CTL] = 1,
[SITAR_A_CDC_ANC1_IIR_B3_CTL] = 1,
[SITAR_A_CDC_ANC1_IIR_B4_CTL] = 1,
[SITAR_A_CDC_ANC1_LPF_B1_CTL] = 1,
[SITAR_A_CDC_ANC1_LPF_B2_CTL] = 1,
[SITAR_A_CDC_ANC1_LPF_B3_CTL] = 1,
[SITAR_A_CDC_ANC1_SPARE] = 1,
[SITAR_A_CDC_ANC1_SMLPF_CTL] = 1,
[SITAR_A_CDC_ANC1_DCFLT_CTL] = 1,
[SITAR_A_CDC_TX1_VOL_CTL_TIMER] = 1,
[SITAR_A_CDC_TX1_VOL_CTL_GAIN] = 1,
[SITAR_A_CDC_TX1_VOL_CTL_CFG] = 1,
[SITAR_A_CDC_TX1_MUX_CTL] = 1,
[SITAR_A_CDC_TX1_CLK_FS_CTL] = 1,
[SITAR_A_CDC_TX1_DMIC_CTL] = 1,
[SITAR_A_CDC_SRC1_PDA_CFG] = 1,
[SITAR_A_CDC_SRC1_FS_CTL] = 1,
[SITAR_A_CDC_RX1_B1_CTL] = 1,
[SITAR_A_CDC_RX1_B2_CTL] = 1,
[SITAR_A_CDC_RX1_B3_CTL] = 1,
[SITAR_A_CDC_RX1_B4_CTL] = 1,
[SITAR_A_CDC_RX1_B5_CTL] = 1,
[SITAR_A_CDC_RX1_B6_CTL] = 1,
[SITAR_A_CDC_RX1_VOL_CTL_B1_CTL] = 1,
[SITAR_A_CDC_RX1_VOL_CTL_B2_CTL] = 1,
[SITAR_A_CDC_CLK_ANC_RESET_CTL] = 1,
[SITAR_A_CDC_CLK_RX_RESET_CTL] = 1,
[SITAR_A_CDC_CLK_TX_RESET_B1_CTL] = 1,
[SITAR_A_CDC_CLK_TX_RESET_B2_CTL] = 1,
[SITAR_A_CDC_CLK_DMIC_CTL] = 1,
[SITAR_A_CDC_CLK_RX_I2S_CTL] = 1,
[SITAR_A_CDC_CLK_TX_I2S_CTL] = 1,
[SITAR_A_CDC_CLK_OTHR_RESET_CTL] = 1,
[SITAR_A_CDC_CLK_TX_CLK_EN_B1_CTL] = 1,
[SITAR_A_CDC_CLK_OTHR_CTL] = 1,
[SITAR_A_CDC_CLK_RDAC_CLK_EN_CTL] = 1,
[SITAR_A_CDC_CLK_ANC_CLK_EN_CTL] = 1,
[SITAR_A_CDC_CLK_RX_B1_CTL] = 1,
[SITAR_A_CDC_CLK_RX_B2_CTL] = 1,
[SITAR_A_CDC_CLK_MCLK_CTL] = 1,
[SITAR_A_CDC_CLK_PDM_CTL] = 1,
[SITAR_A_CDC_CLK_SD_CTL] = 1,
[SITAR_A_CDC_CLK_LP_CTL] = 1,
[SITAR_A_CDC_CLSG_FREQ_THRESH_B1_CTL] = 1,
[SITAR_A_CDC_CLSG_FREQ_THRESH_B2_CTL] = 1,
[SITAR_A_CDC_CLSG_FREQ_THRESH_B3_CTL] = 1,
[SITAR_A_CDC_CLSG_FREQ_THRESH_B4_CTL] = 1,
[SITAR_A_CDC_CLSG_GAIN_THRESH_CTL] = 1,
[SITAR_A_CDC_CLSG_TIMER_B1_CFG] = 1,
[SITAR_A_CDC_CLSG_TIMER_B2_CFG] = 1,
[SITAR_A_CDC_CLSG_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_B1_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_B2_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_B3_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_B4_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_B5_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_B6_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_B7_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_B8_CTL] = 1,
[SITAR_A_CDC_IIR1_CTL] = 1,
[SITAR_A_CDC_IIR1_GAIN_TIMER_CTL] = 1,
[SITAR_A_CDC_IIR1_COEF_B1_CTL] = 1,
[SITAR_A_CDC_IIR1_COEF_B2_CTL] = 1,
[SITAR_A_CDC_IIR1_COEF_B3_CTL] = 1,
[SITAR_A_CDC_IIR1_COEF_B4_CTL] = 1,
[SITAR_A_CDC_IIR1_COEF_B5_CTL] = 1,
[SITAR_A_CDC_TOP_GAIN_UPDATE] = 1,
[SITAR_A_CDC_TOP_RDAC_DOUT_CTL] = 1,
[SITAR_A_CDC_DEBUG_B1_CTL] = 1,
[SITAR_A_CDC_DEBUG_B2_CTL] = 1,
[SITAR_A_CDC_DEBUG_B3_CTL] = 1,
[SITAR_A_CDC_DEBUG_B4_CTL] = 1,
[SITAR_A_CDC_DEBUG_B5_CTL] = 1,
[SITAR_A_CDC_DEBUG_B6_CTL] = 1,
[SITAR_A_CDC_DEBUG_B7_CTL] = 1,
[SITAR_A_CDC_COMP1_B1_CTL] = 1,
[SITAR_A_CDC_COMP1_B2_CTL] = 1,
[SITAR_A_CDC_COMP1_B3_CTL] = 1,
[SITAR_A_CDC_COMP1_B4_CTL] = 1,
[SITAR_A_CDC_COMP1_B5_CTL] = 1,
[SITAR_A_CDC_COMP1_B6_CTL] = 1,
[SITAR_A_CDC_COMP1_SHUT_DOWN_STATUS] = 1,
[SITAR_A_CDC_COMP1_FS_CFG] = 1,
[SITAR_A_CDC_CONN_RX1_B1_CTL] = 1,
[SITAR_A_CDC_CONN_RX1_B2_CTL] = 1,
[SITAR_A_CDC_CONN_RX1_B3_CTL] = 1,
[SITAR_A_CDC_CONN_RX2_B1_CTL] = 1,
[SITAR_A_CDC_CONN_RX2_B2_CTL] = 1,
[SITAR_A_CDC_CONN_RX2_B3_CTL] = 1,
[SITAR_A_CDC_CONN_RX3_B1_CTL] = 1,
[SITAR_A_CDC_CONN_RX3_B2_CTL] = 1,
[SITAR_A_CDC_CONN_RX3_B3_CTL] = 1,
[SITAR_A_CDC_CONN_ANC_B1_CTL] = 1,
[SITAR_A_CDC_CONN_ANC_B2_CTL] = 1,
[SITAR_A_CDC_CONN_TX_B1_CTL] = 1,
[SITAR_A_CDC_CONN_TX_B2_CTL] = 1,
[SITAR_A_CDC_CONN_EQ1_B1_CTL] = 1,
[SITAR_A_CDC_CONN_EQ1_B2_CTL] = 1,
[SITAR_A_CDC_CONN_EQ1_B3_CTL] = 1,
[SITAR_A_CDC_CONN_EQ1_B4_CTL] = 1,
[SITAR_A_CDC_CONN_EQ2_B1_CTL] = 1,
[SITAR_A_CDC_CONN_EQ2_B2_CTL] = 1,
[SITAR_A_CDC_CONN_EQ2_B3_CTL] = 1,
[SITAR_A_CDC_CONN_EQ2_B4_CTL] = 1,
[SITAR_A_CDC_CONN_SRC1_B1_CTL] = 1,
[SITAR_A_CDC_CONN_SRC1_B2_CTL] = 1,
[SITAR_A_CDC_CONN_SRC2_B1_CTL] = 1,
[SITAR_A_CDC_CONN_SRC2_B2_CTL] = 1,
[SITAR_A_CDC_CONN_TX_SB_B1_CTL] = 1,
[SITAR_A_CDC_CONN_TX_SB_B2_CTL] = 1,
[SITAR_A_CDC_CONN_TX_SB_B3_CTL] = 1,
[SITAR_A_CDC_CONN_TX_SB_B4_CTL] = 1,
[SITAR_A_CDC_CONN_TX_SB_B5_CTL] = 1,
[SITAR_A_CDC_CONN_RX_SB_B1_CTL] = 1,
[SITAR_A_CDC_CONN_RX_SB_B2_CTL] = 1,
[SITAR_A_CDC_CONN_CLSG_CTL] = 1,
[SITAR_A_CDC_CONN_SPARE] = 1,
[SITAR_A_CDC_MBHC_EN_CTL] = 1,
[SITAR_A_CDC_MBHC_FIR_B1_CFG] = 1,
[SITAR_A_CDC_MBHC_FIR_B2_CFG] = 1,
[SITAR_A_CDC_MBHC_TIMER_B1_CTL] = 1,
[SITAR_A_CDC_MBHC_TIMER_B2_CTL] = 1,
[SITAR_A_CDC_MBHC_TIMER_B3_CTL] = 1,
[SITAR_A_CDC_MBHC_TIMER_B4_CTL] = 1,
[SITAR_A_CDC_MBHC_TIMER_B5_CTL] = 1,
[SITAR_A_CDC_MBHC_TIMER_B6_CTL] = 1,
[SITAR_A_CDC_MBHC_B1_STATUS] = 1,
[SITAR_A_CDC_MBHC_B2_STATUS] = 1,
[SITAR_A_CDC_MBHC_B3_STATUS] = 1,
[SITAR_A_CDC_MBHC_B4_STATUS] = 1,
[SITAR_A_CDC_MBHC_B5_STATUS] = 1,
[SITAR_A_CDC_MBHC_B1_CTL] = 1,
[SITAR_A_CDC_MBHC_B2_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B1_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B2_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B3_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B4_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B5_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B6_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B7_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B8_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B9_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B10_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B11_CTL] = 1,
[SITAR_A_CDC_MBHC_VOLT_B12_CTL] = 1,
[SITAR_A_CDC_MBHC_CLK_CTL] = 1,
[SITAR_A_CDC_MBHC_INT_CTL] = 1,
[SITAR_A_CDC_MBHC_DEBUG_CTL] = 1,
[SITAR_A_CDC_MBHC_SPARE] = 1,
};

3593
sound/soc/codecs/wcd9304.c Normal file
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File diff suppressed because it is too large Load Diff

72
sound/soc/codecs/wcd9304.h Normal file
View File

@@ -0,0 +1,72 @@
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <sound/soc.h>
#include <linux/mfd/wcd9xxx/wcd9xxx-slimslave.h>
#define SITAR_VERSION_1_0 0x00
#define SITAR_NUM_REGISTERS 0x3E0
#define SITAR_MAX_REGISTER (SITAR_NUM_REGISTERS-1)
#define SITAR_CACHE_SIZE SITAR_NUM_REGISTERS
#define SITAR_REG_VAL(reg, val) {reg, 0, val}
/* Local to the core only */
#define SITAR_SLIM_MAX_RX_PORTS 5
#define SITAR_SLIM_MAX_TX_PORTS 5
extern const u8 sitar_reg_readable[SITAR_CACHE_SIZE];
extern const u8 sitar_reg_defaults[SITAR_CACHE_SIZE];
enum sitar_micbias_num {
SITAR_MICBIAS1,
SITAR_MICBIAS2,
};
enum sitar_pid_current {
SITAR_PID_MIC_2P5_UA,
SITAR_PID_MIC_5_UA,
SITAR_PID_MIC_10_UA,
SITAR_PID_MIC_20_UA,
};
struct sitar_mbhc_calibration {
enum sitar_micbias_num bias;
int tldoh;
int bg_fast_settle;
enum sitar_pid_current mic_current;
int mic_pid;
enum sitar_pid_current hph_current;
int setup_plug_removal_delay;
int shutdown_plug_removal;
};
struct sitar_reg_mask_val {
u16 reg;
u8 mask;
u8 val;
};
extern int sitar_hs_detect(struct snd_soc_codec *codec,
struct snd_soc_jack *headset_jack, struct snd_soc_jack *button_jack,
struct sitar_mbhc_calibration *calibration);
#ifndef anc_header_dec
struct anc_header {
u32 reserved[3];
u32 num_anc_slots;
};
#define anc_header_dec
#endif
extern int sitar_mclk_enable(struct snd_soc_codec *codec, int mclk_enable);

1
sound/soc/msm/Kconfig
View File

@@ -126,6 +126,7 @@ config SND_SOC_MSM8960
select SND_SOC_QDSP6
select SND_SOC_MSM_STUB
select SND_SOC_WCD9310
select SND_SOC_WCD9304
select SND_SOC_MSM_HOSTLESS_PCM
select SND_SOC_MSM_QDSP6_HDMI_AUDIO
default n

2
sound/soc/msm/Makefile
View File

@@ -62,7 +62,7 @@ obj-$(CONFIG_SND_SOC_VOICE) += msm-pcm-voice.o msm-pcm-voip.o
snd-soc-qdsp6-objs += msm-pcm-lpa.o msm-pcm-afe.o
obj-$(CONFIG_SND_SOC_QDSP6) += snd-soc-qdsp6.o
snd-soc-msm8960-objs := msm8960.o apq8064.o
snd-soc-msm8960-objs := msm8960.o apq8064.o msm8930.o
obj-$(CONFIG_SND_SOC_MSM8960) += snd-soc-msm8960.o
# Generic MSM drivers

1083
sound/soc/msm/msm8930.c Normal file
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File diff suppressed because it is too large Load Diff

4
sound/soc/msm/msm8960.c
View File

@@ -1391,7 +1391,7 @@ static int __init msm8960_audio_init(void)
{
int ret;
if (!cpu_is_msm8960() && !cpu_is_msm8930()) {
if (!cpu_is_msm8960()) {
pr_err("%s: Not the right machine type\n", __func__);
return -ENODEV ;
}
@@ -1455,7 +1455,7 @@ module_init(msm8960_audio_init);
static void __exit msm8960_audio_exit(void)
{
if (!cpu_is_msm8960() && !cpu_is_msm8930()) {
if (!cpu_is_msm8960()) {
pr_err("%s: Not the right machine type\n", __func__);
return ;
}