qup_i2c: Fix for multiple write transactions
When a transaction consists of multiple write requests, combine them only when the addresses of the writes are the same. Change-Id: I35089d7b3936acf2de28f075734da84069b83fb3 Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
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@@ -477,7 +477,7 @@ qup_issue_write(struct qup_i2c_dev *dev, struct i2c_msg *msg, int rem,
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addr) << 16),
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addr) << 16),
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dev->base + QUP_OUT_FIFO_BASE);
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dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev, *carry_over | QUP_OUT_DATA << 16 |
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qup_verify_fifo(dev, *carry_over | QUP_OUT_START << 16 |
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addr << 16, (uint32_t)dev->base +
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addr << 16, (uint32_t)dev->base +
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QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
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QUP_OUT_FIFO_BASE + (*idx) - 2, 0);
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} else
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} else
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@@ -541,14 +541,15 @@ qup_issue_write(struct qup_i2c_dev *dev, struct i2c_msg *msg, int rem,
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QUP_OUT_FIFO_BASE + (*idx), 0);
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QUP_OUT_FIFO_BASE + (*idx), 0);
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*idx += 2;
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*idx += 2;
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} else if (next->flags == 0 && dev->pos == msg->len - 1
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} else if (next->flags == 0 && dev->pos == msg->len - 1
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&& *idx < (dev->wr_sz*2)) {
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&& *idx < (dev->wr_sz*2) &&
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(next->addr != msg->addr)) {
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/* Last byte of an intermittent write */
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/* Last byte of an intermittent write */
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writel_relaxed((last_entry |
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writel_relaxed((QUP_OUT_STOP |
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msg->buf[dev->pos]),
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msg->buf[dev->pos]),
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dev->base + QUP_OUT_FIFO_BASE);
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dev->base + QUP_OUT_FIFO_BASE);
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qup_verify_fifo(dev,
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qup_verify_fifo(dev,
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last_entry | msg->buf[dev->pos],
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QUP_OUT_STOP | msg->buf[dev->pos],
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(uint32_t)dev->base +
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(uint32_t)dev->base +
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QUP_OUT_FIFO_BASE + (*idx), 0);
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QUP_OUT_FIFO_BASE + (*idx), 0);
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*idx += 2;
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*idx += 2;
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@@ -605,7 +606,7 @@ qup_set_wr_mode(struct qup_i2c_dev *dev, int rem)
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struct i2c_msg *next = NULL;
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struct i2c_msg *next = NULL;
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if (rem > 1)
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if (rem > 1)
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next = dev->msg + 1;
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next = dev->msg + 1;
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while (rem > 1 && next->flags == 0) {
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while (rem > 1 && next->flags == 0 && (next->addr == dev->msg->addr)) {
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len += next->len + 1;
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len += next->len + 1;
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next = next + 1;
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next = next + 1;
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rem--;
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rem--;
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