From d997b3b7a98d7fa1b99fc3b69c74bd638f2ab8c6 Mon Sep 17 00:00:00 2001 From: Harini Jayaraman Date: Tue, 11 Oct 2011 14:25:29 -0600 Subject: [PATCH] qup_i2c: Fix delay when polling for write ready We wait for FIFO number of bytes to ensure that the I2C state machine is not idle. Change-Id: I24d2a22ac261bd1b53ca57a83c812c3c9f0fbdc4 Signed-off-by: Harini Jayaraman --- drivers/i2c/busses/i2c-qup.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/i2c/busses/i2c-qup.c b/drivers/i2c/busses/i2c-qup.c index 8f2a94248b2..c6bbb0dfc8d 100644 --- a/drivers/i2c/busses/i2c-qup.c +++ b/drivers/i2c/busses/i2c-qup.c @@ -335,8 +335,15 @@ qup_i2c_poll_writeready(struct qup_i2c_dev *dev, int rem) else /* 1-bit delay before we check for bus busy */ udelay(dev->one_bit_t); } - if (retries++ == 1000) - udelay(100); + if (retries++ == 1000) { + /* + * Wait for FIFO number of bytes to be absolutely sure + * that I2C write state machine is not idle. Each byte + * takes 9 clock cycles. (8 bits + 1 ack) + */ + usleep_range((dev->one_bit_t * (dev->out_fifo_sz * 9)), + (dev->one_bit_t * (dev->out_fifo_sz * 9))); + } } qup_print_status(dev); return -ETIMEDOUT; @@ -1076,7 +1083,7 @@ qup_i2c_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dev); - dev->one_bit_t = USEC_PER_SEC/pdata->clk_freq; + dev->one_bit_t = (USEC_PER_SEC/pdata->clk_freq) + 1; dev->pdata = pdata; dev->clk_ctl = 0; dev->pos = 0;