From d9fa3d511cce224e595ccde1c6ae24199a2d5a67 Mon Sep 17 00:00:00 2001 From: Harsh Vardhan Dwivedi Date: Wed, 18 Apr 2012 17:19:11 -0600 Subject: [PATCH] msm: kgsl: Use default hardcoded value for CP's ROQ queue size The command processor FIFO depth is different for A330 and A2xx GPUs. It is best to let each GPU use the default value which is hardcoded in the respective GPU. Change-Id: I5db6a1c0671d0ad4253dcad7f386429d78a4bd62 Signed-off-by: Harsh Vardhan Dwivedi --- drivers/gpu/msm/adreno_ringbuffer.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/msm/adreno_ringbuffer.c b/drivers/gpu/msm/adreno_ringbuffer.c index be0fc1df280..5f16ff76fae 100644 --- a/drivers/gpu/msm/adreno_ringbuffer.c +++ b/drivers/gpu/msm/adreno_ringbuffer.c @@ -339,7 +339,6 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram) if (status != 0) return status; - adreno_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000C0804); rb->rptr = 0; rb->wptr = 0;