From fa679d9a8ab3f43a9564c727a228e25b30f6320b Mon Sep 17 00:00:00 2001 From: Ramesh Masavarapu Date: Thu, 13 Oct 2011 23:42:59 -0700 Subject: [PATCH] crypto: Adding crypto MSM9615. Added the configuration settings for supporting MSM9615. -MSM9615 does not have TZ(trust zone) hence DM configurations are done when checking the target. -MSM9615 does not support PMEM and hence pmem related functions are featurized under PMEM feature - CONFIG_ANDROID_PMEM - Added changes to Kconfig to have QCE40 built for MSM9615. Change-Id: If2946463cc1869f5b0014c68d8e19816cedc8a3a Signed-off-by: Ramesh Masavarapu --- arch/arm/mach-msm/board-9615.c | 121 +++++++++++++++++++++++++++++++++ arch/arm/mach-msm/clock-9615.c | 9 +++ drivers/crypto/Kconfig | 11 +-- drivers/crypto/msm/qce40.c | 42 +++++++++++- drivers/crypto/msm/qcedev.c | 17 ++++- 5 files changed, 192 insertions(+), 8 deletions(-) diff --git a/arch/arm/mach-msm/board-9615.c b/arch/arm/mach-msm/board-9615.c index c009bdfda5c..87ff55928d5 100644 --- a/arch/arm/mach-msm/board-9615.c +++ b/arch/arm/mach-msm/board-9615.c @@ -39,6 +39,16 @@ static struct platform_device *common_devices[] = { &msm9615_device_tsens, &msm_device_nand, &msm_rpm_device, + +#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \ + defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) + &qcrypto_device, +#endif + +#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \ + defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE) + &qcedev_device, +#endif }; static struct pm8xxx_irq_platform_data pm8xxx_irq_pdata __devinitdata = { @@ -196,6 +206,117 @@ struct msm_gpiomux_config msm9615_gsbi_configs[] __initdata = { }, }; +#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \ + defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \ + defined(CONFIG_CRYPTO_DEV_QCEDEV) || \ + defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE) + +#define QCE_SIZE 0x10000 +#define QCE_0_BASE 0x18500000 + +#define QCE_HW_KEY_SUPPORT 0 +#define QCE_SHA_HMAC_SUPPORT 1 +#define QCE_SHARE_CE_RESOURCE 1 +#define QCE_CE_SHARED 0 + +static struct resource qcrypto_resources[] = { + [0] = { + .start = QCE_0_BASE, + .end = QCE_0_BASE + QCE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "crypto_channels", + .start = DMOV_CE_IN_CHAN, + .end = DMOV_CE_OUT_CHAN, + .flags = IORESOURCE_DMA, + }, + [2] = { + .name = "crypto_crci_in", + .start = DMOV_CE_IN_CRCI, + .end = DMOV_CE_IN_CRCI, + .flags = IORESOURCE_DMA, + }, + [3] = { + .name = "crypto_crci_out", + .start = DMOV_CE_OUT_CRCI, + .end = DMOV_CE_OUT_CRCI, + .flags = IORESOURCE_DMA, + }, +}; + +static struct resource qcedev_resources[] = { + [0] = { + .start = QCE_0_BASE, + .end = QCE_0_BASE + QCE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .name = "crypto_channels", + .start = DMOV_CE_IN_CHAN, + .end = DMOV_CE_OUT_CHAN, + .flags = IORESOURCE_DMA, + }, + [2] = { + .name = "crypto_crci_in", + .start = DMOV_CE_IN_CRCI, + .end = DMOV_CE_IN_CRCI, + .flags = IORESOURCE_DMA, + }, + [3] = { + .name = "crypto_crci_out", + .start = DMOV_CE_OUT_CRCI, + .end = DMOV_CE_OUT_CRCI, + .flags = IORESOURCE_DMA, + }, +}; + +#endif + +#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \ + defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) + +static struct msm_ce_hw_support qcrypto_ce_hw_suppport = { + .ce_shared = QCE_CE_SHARED, + .shared_ce_resource = QCE_SHARE_CE_RESOURCE, + .hw_key_support = QCE_HW_KEY_SUPPORT, + .sha_hmac = QCE_SHA_HMAC_SUPPORT, +}; + +static struct platform_device qcrypto_device = { + .name = "qcrypto", + .id = 0, + .num_resources = ARRAY_SIZE(qcrypto_resources), + .resource = qcrypto_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &qcrypto_ce_hw_suppport, + }, +}; +#endif + +#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \ + defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE) + +static struct msm_ce_hw_support qcedev_ce_hw_suppport = { + .ce_shared = QCE_CE_SHARED, + .shared_ce_resource = QCE_SHARE_CE_RESOURCE, + .hw_key_support = QCE_HW_KEY_SUPPORT, + .sha_hmac = QCE_SHA_HMAC_SUPPORT, +}; + +static struct platform_device qcedev_device = { + .name = "qce", + .id = 0, + .num_resources = ARRAY_SIZE(qcedev_resources), + .resource = qcedev_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + .platform_data = &qcedev_ce_hw_suppport, + }, +}; +#endif + #if (defined(CONFIG_MMC_MSM_SDC1_SUPPORT)\ || defined(CONFIG_MMC_MSM_SDC2_SUPPORT)) diff --git a/arch/arm/mach-msm/clock-9615.c b/arch/arm/mach-msm/clock-9615.c index a5db9b287ba..9b9ac4a48db 100644 --- a/arch/arm/mach-msm/clock-9615.c +++ b/arch/arm/mach-msm/clock-9615.c @@ -1576,6 +1576,15 @@ static struct clk_lookup msm_clocks_9615[] = { CLK_LOOKUP("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL), CLK_LOOKUP("mem_clk", ebi1_adm_clk.c, "msm_dmov"), + CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qce.0"), + CLK_LOOKUP("iface_clk", ce1_p_clk.c, "qcrypto.0"), + CLK_LOOKUP("core_clk", ce1_core_clk.c, "qce.0"), + CLK_LOOKUP("core_clk", ce1_core_clk.c, "qcrypto.0"), + + /* TODO: Make this real when RPM's ready. */ + CLK_DUMMY("ebi1_msmbus_clk", ebi1_msmbus_clk.c, NULL, OFF), + CLK_DUMMY("mem_clk", ebi1_adm_clk.c, "msm_dmov", OFF), + }; static void set_fsm_mode(void __iomem *mode_reg) diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 8850516ec21..8088e4443c5 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -309,20 +309,21 @@ config CRYPTO_DEV_QCRYPTO config CRYPTO_DEV_QCE tristate "Qualcomm Crypto Engine (QCE) module" - select CRYPTO_DEV_QCE40 if ARCH_MSM8960 + select CRYPTO_DEV_QCE40 if ARCH_MSM8960 || ARCH_MSM9615 default n help - This driver supports Qualcomm Crypto Engine in MSM7x30 MSM8660 - MSM8x55 and MSM8960 + This driver supports Qualcomm Crypto Engine in MSM7x30, MSM8660 + MSM8x55, MSM8960 and MSM9615 To compile this driver as a module, choose M here: the For MSM7x30 MSM8660 and MSM8x55 the module is called qce - For MSM8960 the module is called qce40 + For MSM8960 and MSM9615 the module is called qce40 config CRYPTO_DEV_QCEDEV tristate "QCEDEV Interface to CE module" default n help - This driver supports Qualcomm QCEDEV Crypto in MSM7x30 MSM8660, MSM8960. + This driver supports Qualcomm QCEDEV Crypto in MSM7x30, MSM8660, + MSM8960 and MSM9615. This exposes the interface to the QCE hardware accelerator via IOCTLs To compile this driver as a module, choose M here: the module will be called qcedev. diff --git a/drivers/crypto/msm/qce40.c b/drivers/crypto/msm/qce40.c index 90a78891883..4ef2e086aaa 100644 --- a/drivers/crypto/msm/qce40.c +++ b/drivers/crypto/msm/qce40.c @@ -29,6 +29,7 @@ #include #include #include +#include #include "qce.h" #include "qce40.h" @@ -149,6 +150,12 @@ static int _probe_ce_engine(struct qce_device *pce_dev) pce_dev->ce_dm.ce_block_size = 16; } } + /* + * This is a temporary change - until Data Mover changes its + * configuration from 16 byte crci to 64 byte crci. + */ + if (cpu_is_msm9615()) + pce_dev->ce_dm.ce_block_size = 16; dev_info(pce_dev->pdev, "IO base 0x%x\n, ce_in channel %d , " @@ -161,6 +168,23 @@ static int _probe_ce_engine(struct qce_device *pce_dev) return 0; }; +#ifdef CONFIG_ARCH_MSM9615 +static void config_ce_engine(struct qce_device *pce_dev) +{ + unsigned int val = 0; + + val = (1 << CRYPTO_MASK_DOUT_INTR) | (1 << CRYPTO_MASK_DIN_INTR) | + (1 << CRYPTO_MASK_OP_DONE_INTR) | + (1 << CRYPTO_MASK_ERR_INTR); + + writel_relaxed(val, pce_dev->iobase + CRYPTO_CONFIG_REG); +} +#else +static void config_ce_engine(struct qce_device *pce_dev) +{ + +} +#endif static void _check_probe_done_call_back(struct msm_dmov_cmd *cmd_ptr, unsigned int result, struct msm_dmov_errdata *err) @@ -185,6 +209,22 @@ static int _init_ce_engine(struct qce_device *pce_dev) clk_reset(pce_dev->ce_core_clk, CLK_RESET_ASSERT); clk_reset(pce_dev->ce_core_clk, CLK_RESET_DEASSERT); + /* + * Ensure previous instruction (any writes to CLK registers) + * to toggle the CLK reset lines was completed before configuring + * ce engine. The ce engine configuration settings should not be lost + * becasue of clk reset. + */ + mb(); + + /* Configure the CE Engine */ + config_ce_engine(pce_dev); + + /* + * Ensure ce configuration is completed. + */ + mb(); + pce_dev->ce_dm.chan_ce_in_cmd->complete_func = _check_probe_done_call_back; pce_dev->ce_dm.chan_ce_in_cmd->cmdptr = @@ -2529,4 +2569,4 @@ EXPORT_SYMBOL(qce_hw_support); MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Mona Hossain "); MODULE_DESCRIPTION("Crypto Engine driver"); -MODULE_VERSION("2.11"); +MODULE_VERSION("2.12"); diff --git a/drivers/crypto/msm/qcedev.c b/drivers/crypto/msm/qcedev.c index dcc98a00770..9d315d21fd6 100644 --- a/drivers/crypto/msm/qcedev.c +++ b/drivers/crypto/msm/qcedev.c @@ -1229,6 +1229,7 @@ static int qcedev_hash_final(struct qcedev_async_req *areq, return qcedev_hmac_final(areq, handle); } +#ifdef CONFIG_ANDROID_PMEM static int qcedev_pmem_ablk_cipher_max_xfer(struct qcedev_async_req *areq, struct qcedev_handle *handle) { @@ -1438,6 +1439,18 @@ static int qcedev_pmem_ablk_cipher(struct qcedev_async_req *qcedev_areq, return err; } +#else +static int qcedev_pmem_ablk_cipher_max_xfer(struct qcedev_async_req *areq, + struct qcedev_handle *handle) +{ + return -EPERM; +} +static int qcedev_pmem_ablk_cipher(struct qcedev_async_req *qcedev_areq, + struct qcedev_handle *handle) +{ + return -EPERM; +} +#endif/*CONFIG_ANDROID_PMEM*/ static int qcedev_vbuf_ablk_cipher_max_xfer(struct qcedev_async_req *areq, int *di, struct qcedev_handle *handle, @@ -1837,7 +1850,7 @@ static long qcedev_ioctl(struct file *file, unsigned cmd, unsigned long arg) podev)) return -EINVAL; - if (qcedev_areq.cipher_op_req.use_pmem == QCEDEV_USE_PMEM) + if ((qcedev_areq.cipher_op_req.use_pmem) && (QCEDEV_USE_PMEM)) err = qcedev_pmem_ablk_cipher(&qcedev_areq, handle); else err = qcedev_vbuf_ablk_cipher(&qcedev_areq, handle); @@ -2156,7 +2169,7 @@ static void qcedev_exit(void) MODULE_LICENSE("GPL v2"); MODULE_AUTHOR("Mona Hossain "); MODULE_DESCRIPTION("Qualcomm DEV Crypto driver"); -MODULE_VERSION("1.23"); +MODULE_VERSION("1.24"); module_init(qcedev_init); module_exit(qcedev_exit);