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Merge "ARM: gic: Add spinlocks for SGIR/AIR/EOI for 8625" into msm-3.0

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2012-05-02 07:47:22 -07:00
committed by QuIC Gerrit Code Review
parent bce732ffc5 6639886be3
commit ff93f25e9c
1 changed files with 45 additions and 1 deletions
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46
arch/arm/common/gic.c
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@@ -214,6 +214,9 @@ static int gic_suspend_one(struct gic_chip_data *gic)
void __iomem *base = gic_data_dist_base(gic);
for (i = 0; i * 32 < gic->max_irq; i++) {
#ifdef CONFIG_ARCH_MSM8625
raw_spin_lock(&irq_controller_lock);
#endif
gic->enabled_irqs[i]
= readl_relaxed(base + GIC_DIST_ENABLE_SET + i * 4);
/* disable all of them */
@@ -221,6 +224,9 @@ static int gic_suspend_one(struct gic_chip_data *gic)
/* enable the wakeup set */
writel_relaxed(gic->wakeup_irqs[i],
base + GIC_DIST_ENABLE_SET + i * 4);
#ifdef CONFIG_ARCH_MSM8625
raw_spin_unlock(&irq_controller_lock);
#endif
}
mb();
return 0;
@@ -269,11 +275,17 @@ static void gic_resume_one(struct gic_chip_data *gic)
gic_show_resume_irq(gic);
for (i = 0; i * 32 < gic->max_irq; i++) {
#ifdef CONFIG_ARCH_MSM8625
raw_spin_lock(&irq_controller_lock);
#endif
/* disable all of them */
writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4);
/* enable the enabled set */
writel_relaxed(gic->enabled_irqs[i],
base + GIC_DIST_ENABLE_SET + i * 4);
#ifdef CONFIG_ARCH_MSM8625
raw_spin_unlock(&irq_controller_lock);
#endif
}
mb();
}
@@ -306,8 +318,13 @@ static void gic_eoi_irq(struct irq_data *d)
gic_arch_extn.irq_eoi(d);
raw_spin_unlock(&irq_controller_lock);
}
#ifdef CONFIG_ARCH_MSM8625
raw_spin_lock(&irq_controller_lock);
#endif
writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
#ifdef CONFIG_ARCH_MSM8625
raw_spin_unlock(&irq_controller_lock);
#endif
}
static int gic_set_type(struct irq_data *d, unsigned int type)
@@ -430,7 +447,13 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
void __iomem *cpu_base = gic_data_cpu_base(gic);
do {
#ifdef CONFIG_ARCH_MSM8625
raw_spin_lock(&irq_controller_lock);
#endif
irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
#ifdef CONFIG_ARCH_MSM8625
raw_spin_unlock(&irq_controller_lock);
#endif
irqnr = irqstat & ~0x1c00;
if (likely(irqnr > 15 && irqnr < 1021)) {
@@ -439,7 +462,13 @@ asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
continue;
}
if (irqnr < 16) {
#ifdef CONFIG_ARCH_MSM8625
raw_spin_lock(&irq_controller_lock);
#endif
writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
#ifdef CONFIG_ARCH_MSM8625
raw_spin_unlock(&irq_controller_lock);
#endif
#ifdef CONFIG_SMP
handle_IPI(irqnr, regs);
#endif
@@ -588,6 +617,9 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
#ifdef CONFIG_ARCH_MSM8625
raw_spin_lock(&irq_controller_lock);
#endif
writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
@@ -607,6 +639,9 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
writel_relaxed(0xF, base + GIC_CPU_CTRL);
else
writel_relaxed(1, base + GIC_CPU_CTRL);
#ifdef CONFIG_ARCH_MSM8625
raw_spin_unlock(&irq_controller_lock);
#endif
mb();
}
@@ -944,6 +979,9 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
int cpu;
unsigned long sgir;
unsigned long map = 0;
#ifdef CONFIG_ARCH_MSM8625
unsigned long flags;
#endif
/* Convert our logical CPU mask into a physical one. */
for_each_cpu(cpu, mask)
@@ -959,9 +997,15 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
*/
dsb();
#ifdef CONFIG_ARCH_MSM8625
raw_spin_lock_irqsave(&irq_controller_lock, flags);
#endif
/* this always happens on GIC0 */
writel_relaxed(sgir,
gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
#ifdef CONFIG_ARCH_MSM8625
raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
#endif
mb();
}
#endif