We can stall RCU processing on SMP platforms if a CPU sits in its idle
loop for a long time. This happens because we don't call irq_enter()
and irq_exit() around generic_smp_call_function_interrupt() and
friends. Add the necessary calls, and remove the one from within
ipi_timer(), so that they're all in a common place.
Change-Id: I18aba9978f1a3497d8a960f2f9e3618248eb0107
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Joel King <joelking@codeaurora.org>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
There is no need to manually program GIC for edge trigger PPIs
through board or device file hooks after the introduction of
enable_percpu_irq(.., type) interface. 2nd parameter of this
API needs to be used for programming the right trigger type for the PPI.
Change-Id: I2f33672f565dc94413365fd95f9f92aa07318687
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
The PMU raw spinlock was used without proper initialization
and caused the kernel to dump spinlock bad magic errors.
Change-Id: Ib35b431dc6bdb6cef6a79c01557e372e8417fec0
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
The L1CC PMU interrupt is a PPI, so use the per-CPU
request, free, enable, disable API.
Change-Id: I150dcb6ead34f0548c3fa31cc21bf7ac4d427a96
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
For cases with SPARSE_IRQ enabled, irqs preallocated with
arch_probe_nr_irqs() are already marked as allocated in the
allocated_irqs bitmap. As a consequence, irq chip drivers that
allocate irqs will feel one of two behaviors:
1. An allocation will succeed with the starting irq_base one
more than the preallocated irqs. This will thus waste the
preceeding interrupt resources that were preallocated, unless a
legacy chip driver happens to assume ownership of these by some
platform definition. The GIC driver is a typical primary chip
driver, and abides to the allocation APIs. So this can be a
problem in many trivial usecases.
2. An allocation will fail with < 0. This can also happen in the
GIC driver, which interprets this value as meaning the irq_descs
are already preallocated. But in Device Tree configurations, the
fallback irq_base is -1. This results in an invalid irq_base
value.
Looking forward, we are moving towards a world where preallocation
of irqs is no longer necessary. irq_domain is scoped to handle all
irq_desc allocations in the future. Thus, we should support
configurations where the platform wants to preallocate no irqs.
One easy way to achieve this is to allow for
machine_desc->nr_irqs < 0, which indicates not to preallocate any
interrupts.
Change-Id: Ie793932c58de72c1b91b6e039b77a8e5d64ecc75
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
If an ARM system has multiple cpus in the same socket and the
kernel is booted with maxcpus=1, secondary cpus are possible but
not present due to how platform_smp_prepare_cpus() is called.
Since most typical ARM processors don't actually support physical
hotplug, initialize the present map to be equal to the possible
map in generic ARM SMP code. Also, always call
platform_smp_prepare_cpus() as long as max_cpus is non-zero (0
means no SMP) to allow platform code to do any SMP setup.
After applying this patch it's possible to boot an ARM system
with maxcpus=1 on the command line and then hotplug in secondary
cpus via sysfs. This is more in line with how x86 does things.
Change-Id: Ie97366fe3236670ec9c3cb3b77ab8f7ee4a39fd3
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[stepanm@codeaurora.org: resolved trivial merge conflict]
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The arm kernel uses undefined instructions to implement
BUG/BUG_ON(). This leads to problems where people don't read one
line above the Oops message and see the "kernel BUG at ..."
message and so they wrongly assume the kernel has hit an
undefined instruction.
Instead of printing:
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP
print
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
This should prevent people from thinking the BUG_ON was an
undefined instruction when it was actually intentional.
Change-Id: I3ae77c57d47633b28e22add8764ba52542ce5529
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Align sections to the selected cache line size rather than
assuming a line size of 32 bytes.
Change-Id: Ib8a30cc5abd66036c0fd7366bcdad07dc1047c04
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The linker script assumes a cacheline size of 32 bytes when aligning
the .data..cacheline_aligned and .data..percpu sections.
This patch updates the script to use L1_CACHE_BYTES, which should be set
to 64 on platforms that require it.
Change-Id: I6f760c6945138ab8872df2e15c295847077547c8
Signed-off-by: Will Deacon <will.deacon@arm.com>
[stepanm@codeaurora.org: resolved merge conflict]
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The current check compares against nr_irqs, which is assigned as
machine_desc->nr_irqs if defined. Per the usage in
arch_probe_nr_irqs(), nr_irqs is interpreted to mean the
preallocated irqs when used in a SPARSE_IRQ configuration. So
it's entirely possible that a chip driver will set its IRQ flags
for a IRQ number greater than nr_irqs.
NR_IRQS is still the largest IRQ any system can have, so let's
check for that instead.
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
The VFP state variables were declared as per-CPU variables
but accessed as though they weren't. This caused memory corruption.
Change-Id: I49956973e55217af4f860db0a9a7f7c59eb4118a
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
The definition of __exception_irq_entry for
CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a
circular dependency with it's current home in asm/system.h. Create
asm/exception.h and update all current users.
v4: - rebase to rmk/for-next
v3: - remove redundant includes of linux/ftrace.h
v2: - document the usage restricitions of __exception*
Change-Id: I9efdb6a621bb915ad00b9a133ec93e98182fd483
Cc: Zoltan Devai <zdevai@gmail.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[tsoni@codeaurora.org: Merge fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
The commit 292b293 creates the MSM boot failures, so squash
the commit 28af690 with it to avoid such failures. The commit ddd847
and 0c1991 are required to keep the watchdog and Copper targets working.
commit 292b293ceef2eda1f96f0c90b96e954d7bdabd1c
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Wed Jul 20 16:24:14 2011 +0100
ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit 28af690a284dfcb627bd69d0963db1c0f412cb8c
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri Jul 22 12:52:37 2011 +0100
ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit ddd8478d68f8cf75ee9771667c0cbe2a9d1caeb9
Author: Trilok Soni <tsoni@codeaurora.org>
Date: Tue Dec 6 00:56:01 2011 +0530
msm: watchdog: Use request_percpu_irq() interface
Change-Id: I7c319344f6a7f7a7c70682ac87f5c385e56d130c
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
commit 0c19915e092214a4c17a9920c4c1f3d78610217d
Author: Sathish Ambley <sambley@codeaurora.org>
Date: Fri Dec 9 17:07:37 2011 +0530
arm: arch_timer: Use request_percpu_irq() API
Change-Id: Iee9b218d538f315cd884a47d95bcc0dcc49b0fe1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Change-Id: I7bbba706b1f2e55814be5891ed76063725c2bfb1
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: MSM specific fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
ARM uses its own BUG() handler which makes its output slightly different
from other archtectures.
One of the problems is that the ARM implementation doesn't report the function
with the BUG() in it, but always reports the PC being in __bug(). The generic
implementation doesn't have this problem.
Currently we get something like:
kernel BUG at fs/proc/breakme.c:35!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
...
PC is at __bug+0x20/0x2c
With this patch it displays:
kernel BUG at fs/proc/breakme.c:35!
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP
...
PC is at write_breakme+0xd0/0x1b4
This implementation uses an undefined instruction to implement BUG, and sets up
a bug table containing the relevant information. Many versions of gcc do not
support %c properly for ARM (inserting a # when they shouldn't) so we work
around this using distasteful macro magic.
v1: Initial version to replace existing ARM BUG() implementation with something
more similar to other architectures.
v2: Add Thumb support, remove backtrace whitespace output changes. Change to
use macros instead of requiring the asm %d flag to work (thanks to
Dave Martin <dave.martin@linaro.org>)
v3: Remove old BUG() implementation in favor of this one.
Remove the Backtrace: message (will submit this separately).
Use ARM_EXIT_KEEP() so that some architectures can dump exit text at link time
thanks to Stephen Boyd <sboyd@codeaurora.org> (although since we always
define GENERIC_BUG this might be academic.)
Rebase to linux-2.6.git master.
v4: Allow BUGS in modules (these were not reported correctly in v3)
(thanks to Stephen Boyd <sboyd@codeaurora.org> for suggesting that.)
Remove __bug() as this is no longer needed.
v5: Add %progbits as the section flags.
Change-Id: I9f588a06ddd739138fddfa6a5bf67079796e68eb
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Write a Krait-specific configuration setting when enabling
the MMU.
Change-Id: I539526a4a3fa28b4b466db35c589afecab4ed257
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
The L2CC PMU is shared between all CPU's. In system wide profiling
mode, perf allocates each event for each CPU. This restricts
the number of L2 events that the user can specify.
Instead, change the event filters, such that in system wide mode
we count each event from all CPU's. This way, the user can specify
upto 4 events (which is the current limit in h/w) in system wide
profiling mode.
Task wide profiling mode is unchanged, since we need to filter
according to the CPU on which the task/thread is running.
Change-Id: Ia51fe97cdc19617f8a3cdd53409cb5f94ff2d9b3
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Update the active perf counter data structs with the most recent
values of the counters before going into powercollapse and restore
the corresponding hardware counters with these values when coming
out of it.
This change fixes a bug where the counter outputs show wild swings
when CPU power collapse is enabled.
Change-Id: I9c4ff4d4504df5b50c33a796c605126448c440cb
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
When the cpu is powered down in a low power mode, the gic cpu
interface may be reset, and when the cpu cluster is powered
down, the gic distributor may also be reset.
This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the gic cpu interface registers, and the
CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save
and restore the gic distributor registers.
Change-Id: Ifad58fe6c9068d48b0515e444ae528619e036125
Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
[kumarrav@codeaurora.org: fixup gic.h merge conflict]
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
Fix the following warning seen while linking
WARNING: vmlinux.o(.text+0xc4b8): Section mismatch in reference
from the function arch_timer_register() to the (unknown reference)
.cpuinit.data:(unknown)
The function arch_timer_register() references
the (unknown reference) __cpuinitdata (unknown).
This is often because arch_timer_register lacks a __cpuinitdata
annotation or the annotation of (unknown) is wrong.
Change-Id: I2646e63550b9f46d36a34d9e3b2841c7d6204386
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Hotplug occurs frequently enough on our targets that its messages are
clogging up the logs. There is no need for any messages to be printed
when hotplug is successful.
Change-Id: Icf213ab409ba428f39439f886cdf4c070a48bfbf
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Add the ability to specify events using the register, code, group
format instead of using enumeration values for scorpion L2 cache
raw perf events.
The existing enumeration values are temporarily left in place as they
are used by legacy copies of tools such as QView.
Change-Id: Id3e9fc8e13f61b2a0a811e1cdb458faaf52c5d02
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Adding the L2 cycle counter in the default list of events
has the advantage that the user can do a :
perf stat -e l2-cycles -e cycles ls
and see the outputs for the L2 cycle counter and L1 cycle
counter separately. Previously, it was only accessible via
the raw code "rsfe".
This method also allows us to program the L2 cycle counter
only from one CPU.
The changes in this patch are used by the userspace perf
tool.
Change-Id: I61b85b48f5474fe9f6ffb1a405b60b4332ab60c7
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
When emulating a SWP/SWPB instruction, check the condition
code of the instruction and compare it against CPSR status
bits rather than relying on the architecture to only raise
an undefined instruction exception if the condition checks
are passing.
Change-Id: I9707960b091c3a5af20e396e0b6d5ed2aaf935ff
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Annotate the low level hardware locks which must not be preempted.
In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.
Change-Id: I1c73fd5472b9ab356173637a7819095394004ebf
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
[kumarrav@codeaurora.org: fixup gic.c and cache-l2x0.c merge conflict]
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
Squash following three patches since the patch with 2ef7570 commit
prevents the MSM platforms from booting, which gets solved in the
next commit ca15af1, but adds build failure; which gets solved in the
final commit 78359cb.
commit 2ef75701d1711a1feee2a82b42a2597ddc05f88b
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Thu Jul 21 14:51:13 2011 +0100
ARM: CPU hotplug: fix abuse of irqdesc->node
irqdesc's node member is supposed to mark the numa node number for the
interrupt. Our use of it is non-standard. Remove this, replacing the
functionality with a test of the affinity mask.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
commit ca15af19ac07908c8ca386f6d944a18aa343b868
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Thu Jul 21 15:07:56 2011 +0100
ARM: CPU hotplug: pass in proper affinity mask on IRQ migration
Now that the GIC takes care of selecting a target interrupt from the
affinity mask, we don't need all this complexity in the core code
anymore. Just detect when we need to break affinity.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
commit 78359cb86b8c4c8946f6732eac2757fa5e1d4de4
Author: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Thu Jul 21 15:14:21 2011 +0100
ARM: CPU hotplug: ensure we migrate all IRQs off a downed CPU
Our selection of interrupts to consider for IRQ migration is sub-
standard. We were potentially including per-CPU interrupts in our
migration strategy, but omitting chained interrupts. This caused
some interrupts to remain on a downed CPU.
We were also trying to migrate interrupts which were not migratable,
resulting in an OOPS.
Instead, iterate over all interrupts, skipping per-CPU interrupts
or interrupts whose affinity does not include the downed CPU, and
attempt to set the affinity for every one else if their chip
implements irq_set_affinity().
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Change-Id: I1559f4f9b2aa52ce026505c7e4d5e7cf9bd102af
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: squash the commits to avoid boot & build failures]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Level triggered interrupt is deasserted when a new TVAL is written
only when the interrupt is unmasked. Make sure that the interrupt
is unmasked in CTL register before TVAL is written.
Change-Id: I1bbfe262137fb27c0de68a552b07e285f424b259
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Register interrupts using interrupt action mechanism instead of
gic_request_ppi() which is dependent on an another patch series
that doesn't exist yet.
Add read_current_timer() to support ARCH_HAS_READ_CURRENT_TIMER
and register the delay loop routine.
Change-Id: I2e7309b93a7bdae37103b738d547eb20f86fe9f7
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
* changes:
Perf: Use CPU PM notifiers to save and restore PMU regs
ARM: cpu_pm: Add cpu power management notifiers
ARM: Perfevents: Add mode exclusion support for Krait P2
Perf: Fix detection of Krait implementation events
Some PMU registers have undefined values at reset. Power collapsing
CPU's can cause the PMU state to be messed up. Use the CPU PM notifiers
to save and restore PMU state correctly.
Change-Id: I4d5d73abc3455b38219239527d94d4afc30ed886
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Mode exclusion allows for counting filtered by the mode
the CPU in running in.
e.g.
perf stat -e rXXX:u to count only userspace activity
perf stat -e rXXX:k to count only kernel activity
Change-Id: I6cf6035d3cfe8d3ee8534ffe130eac6e965aa899
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Add perf support for Krait P2 which has different base
addresses and supports counting of VeNUM events.
Change-Id: I39e6a52314f2463dfea0765c68825dd0d84dd04f
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Provide an A15 sched_clock implementation using the virtual counter,
which is thought to be more useful than the physical one in a
virtualised environment, as it can offset the time spent in another
VM or the hypervisor.
Change-Id: Ica870d279dba38304581763654c683cd09f87153
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[sambley@codeaurora.org Fix conflicts due to patched code not
against latest version of arch_timer.c]
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Change-Id: Ibaddc7f174bc168cef579b66ab06b966878ae155
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
* common/android-3.0: (570 commits)
misc: remove kernel debugger core
ARM: common: fiq_debugger: dump sysrq directly to console if enabled
ARM: common: fiq_debugger: add irq context debug functions
net: wireless: bcmdhd: Call init_ioctl() only if was started properly for WEXT
net: wireless: bcmdhd: Call init_ioctl() only if was started properly
net: wireless: bcmdhd: Fix possible memory leak in escan/iscan
cpufreq: interactive governor: default 20ms timer
cpufreq: interactive governor: go to intermediate hi speed before max
cpufreq: interactive governor: scale to max only if at min speed
cpufreq: interactive governor: apply intermediate load on current speed
ARM: idle: update idle ticks before call idle end notifier
input: gpio_input: don't print debounce message unless flag is set
net: wireless: bcm4329: Skip dhd_bus_stop() if bus is already down
net: wireless: bcmdhd: Skip dhd_bus_stop() if bus is already down
net: wireless: bcmdhd: Improve suspend/resume processing
net: wireless: bcmdhd: Check if FW is Ok for internal FW call
tcp: Don't nuke connections for the wrong protocol
ARM: common: fiq_debugger: make uart irq be no_suspend
net: wireless: Skip connect warning for CONFIG_CFG80211_ALLOW_RECONNECT
mm: avoid livelock on !__GFP_FS allocations
...
Conflicts:
arch/arm/mm/cache-l2x0.c
arch/arm/vfp/vfpmodule.c
drivers/mmc/core/host.c
kernel/power/wakelock.c
net/bluetooth/hci_event.c
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
