Replace use of clk_enable() and clk_disable() with calls to
clk_prepare_enable() and clk_disable_unprepare(), respectively.
Change-Id: I1932b6677906003c2c912b2849fdb72655334ff6
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
The SPI driver is modified to support the new QUPe
controller (version 0x2). The SPI functionality of the
controller is very similar to the previous QUPe
controller (version 0x1). This change addresses
some cleanup along with register address modifications and
flow changes.
Change-Id: I15e7084dd54a1144bd85bf75efd7757b545d24f9
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
The chip-select GPIO's pertaining to each slave remains in suspended
configuration until the first transfer is intiated by the slave.
Change-Id: I3aa8555289be7ce457b91a969cf03909be0965d7
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
This error is reproted randomly when the SPI core is put
into RUN state and occurs when the ACPU clock is low.
When the timer expires, we check again to ensure that the
STATE_VALID bit is set before returning.
CRs-fixed: 304672
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
The crci conflict checking code was designed for a system where a crci's
mux could be changed at runtime. In reality, our chips configure these
statically, so it is not necessary.
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Drivers should now use their device names to distinguish between
clocks of the same type rather than the clock name.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
arch/arm/mach-msm/board-qrdc.c
arch/arm/mach-msm/board-qt8660.c
