A driver using fiq functions should be usable on targets
with or without CONFIG_FIQ enabled. Instead of making code
dependent on #ifdef CONFIG_FIQ, add empty stubs for the fiq
functions.
Change-Id: Ie8b1905ba53664d99bd707be3c83291c97eb1066
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
During the SDCC DMA transfer, if DMA transfer time is
long enough to do IDLE power collapse then system may
go into IDLE power collapse and once SDCC DMA transfer
is completed, system wakes up from Idle Power Collapse
due to SDCC DMA interrupt. But delay for waking up
from Idle Power collapse could be as large as 5 ms which
really degrades the overall read & write throughputs
for SD/eMMC/SDIO cards.
For example, following are the performance numbers with
eMMC card on MSM8960 platform with and without Idle Power
Collapse.
Idle Power collapse enabled:
LMDD Read throughput = ~14 MB/s
LMDD Write throughput = ~6 MB/s
Idle Power Collapse disabled:
LMDD Read throughput = ~25 MB/s
LMDD Write throughput = ~8 MB/s
So this change votes against the Idle power collapse by registering
with PM QOS about it's acceptable DMA latency when SDCC transfer is
active. This latency value is one more than the latency of SWFI
which means system can go into SWFI but not in any of the other
low power modes (including Idle power collapse).
CRs-fixed: 327751
Change-Id: Iae5e12cade383544243f17c448346dd5d0faa60e
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
For cases with SPARSE_IRQ enabled, irqs preallocated with
arch_probe_nr_irqs() are already marked as allocated in the
allocated_irqs bitmap. As a consequence, irq chip drivers that
allocate irqs will feel one of two behaviors:
1. An allocation will succeed with the starting irq_base one
more than the preallocated irqs. This will thus waste the
preceeding interrupt resources that were preallocated, unless a
legacy chip driver happens to assume ownership of these by some
platform definition. The GIC driver is a typical primary chip
driver, and abides to the allocation APIs. So this can be a
problem in many trivial usecases.
2. An allocation will fail with < 0. This can also happen in the
GIC driver, which interprets this value as meaning the irq_descs
are already preallocated. But in Device Tree configurations, the
fallback irq_base is -1. This results in an invalid irq_base
value.
Looking forward, we are moving towards a world where preallocation
of irqs is no longer necessary. irq_domain is scoped to handle all
irq_desc allocations in the future. Thus, we should support
configurations where the platform wants to preallocate no irqs.
One easy way to achieve this is to allow for
machine_desc->nr_irqs < 0, which indicates not to preallocate any
interrupts.
Change-Id: Ie793932c58de72c1b91b6e039b77a8e5d64ecc75
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
SPARSE_IRQ gives the freedom to use high, discontiguous IRQ
numbers at very low memory costs. But even with SPARSE_IRQ, the
highest interrupt number of the system is limited by NR_IRQS,
since NR_IRQS defines the number of IRQ_BITMAP_BITS.
NR_IRQS is currently limited to 1024 on ARM, as of the following
commit:
commit 5a5fb7dbe8
Author: Steven Rostedt <srostedt@redhat.com>
Date: Thu Feb 12 10:53:37 2009 -0500
preempt-count: force hardirq-count to max of 10
This implies that architectures having more than 1024 interrupts
cannot manage. Let's remove the constraint on nesting level,
since as the commit above mentions, we're probably bound by stack
size at that point, anyways.
Change-Id: Ic4af331874a8fda66e2c94ef80ad73314badd74d
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
Provide the GIC code with a low level handler that can be used
by platforms using CONFIG_MULTI_IRQ_HANDLER.
Change-Id: Ib0eb0e9968dc1708e4232f7c306359344025f80a
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
The definition of __exception_irq_entry for
CONFIG_FUNCTION_GRAPH_TRACER=y needs linux/ftrace.h, but this creates a
circular dependency with it's current home in asm/system.h. Create
asm/exception.h and update all current users.
v4: - rebase to rmk/for-next
v3: - remove redundant includes of linux/ftrace.h
v2: - document the usage restricitions of __exception*
Change-Id: I9efdb6a621bb915ad00b9a133ec93e98182fd483
Cc: Zoltan Devai <zdevai@gmail.com>
Signed-off-by: Jamie Iles <jamie@jamieiles.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
[tsoni@codeaurora.org: Merge fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
The GIC support code is heavily using the fact that hardware
implementations are exposing banked registers. Unfortunately, it
looks like at least one GIC implementation (EXYNOS) offers both
the distributor and the CPU interfaces at different addresses,
depending on the CPU.
This problem is solved by allowing the distributor and CPU interface
addresses to be per-cpu variables for the platforms that require it.
The EXYNOS code is updated not to mess with the GIC internals while
handling interrupts, and struct gic_chip_data is back to being private.
The DT binding for the gic is updated to allow an optional "cpu-offset"
value, which is used to compute the various base addresses.
Finally, a new config option (GIC_NON_BANKED) is used to control this
feature, so the overhead is only present on kernels compiled with
support for EXYNOS.
Tested on Origen (EXYNOS4) and Panda (OMAP4).
Change-Id: I4c4adf1b3009dd20c7e6942b1d3e8d63999dd667
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[tsoni@codeaurora.org: MSM specific merge fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Commit "ARM: gic: add irq_domain support" (b49b6ff) breaks SPARSE_IRQ
on platforms with GIC. When SPARSE_IRQ is enabled, all NR_IRQS or
mach_desc->nr_irqs will be allocated by arch_probe_nr_irqs(). This caused
irq_alloc_descs to allocate irq_descs after the pre-allocated space.
Make irq_alloc_descs search for an exact irq range and assume it has
been pre-allocated on failure. For DT probing dynamic allocation is used.
DT enabled platforms should set their nr_irqs to NR_IRQ_LEGACY and have all
irq_chips allocate their irq_descs with irq_alloc_descs if SPARSE_IRQ is
enabled.
gic_init irq_start param is changed to be signed with negative meaning do
dynamic Linux irq assigment.
Change-Id: I05b83bd8b72471233c0ea23bc9e8af2916e6b0fa
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
This adds ARM gic interrupt controller initialization using device tree
data.
The initialization function is intended to be called by of_irq_init
function like this:
const static struct of_device_id irq_match[] = {
{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
{}
};
static void __init init_irqs(void)
{
of_irq_init(irq_match);
}
Change-Id: I722c5f7acf2426dac7937f53d3a0bf5a1d1fbae6
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
[tsoni@codeaurora.org: Fix merge conflicts]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Convert the gic interrupt controller to use irq domains in preparation
for device-tree binding and MULTI_IRQ. This allows for translation between
GIC interrupt IDs and Linux irq numbers.
The meaning of irq_offset has changed. It now is just the number of skipped
GIC interrupt IDs for the controller. It will be 16 for primary GIC and 32
for secondary GICs.
Change-Id: Ie94f443aedea16036a6d2c30ff5ea4b3e4cfe9e1
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Jamie Iles <jamie@jamieiles.com>
Tested-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
[tsoni@codeaurora.org: Fix merge conflicts]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
The commit 292b293 creates the MSM boot failures, so squash
the commit 28af690 with it to avoid such failures. The commit ddd847
and 0c1991 are required to keep the watchdog and Copper targets working.
commit 292b293ceef2eda1f96f0c90b96e954d7bdabd1c
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Wed Jul 20 16:24:14 2011 +0100
ARM: gic: consolidate PPI handling
PPI handling is a bit of an odd beast. It uses its own low level
handling code and is hardwired to the local timers (hence lacking
a registration interface).
Instead, switch the low handling to the normal SPI handling code.
PPIs are handled by the handle_percpu_devid_irq flow.
This also allows the removal of some duplicated code.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: David Brown <davidb@codeaurora.org>
Cc: Bryan Huntsman <bryanh@codeaurora.org>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit 28af690a284dfcb627bd69d0963db1c0f412cb8c
Author: Marc Zyngier <marc.zyngier@arm.com>
Date: Fri Jul 22 12:52:37 2011 +0100
ARM: gic, local timers: use the request_percpu_irq() interface
This patch remove the hardcoded link between local timers and PPIs,
and convert the PPI users (TWD, MCT and MSM timers) to the new
*_percpu_irq interface. Also some collateral cleanup
(local_timer_ack() is gone, and the interrupt handler is strictly
private to each driver).
PPIs are now useable for more than just the local timers.
Additional testing by David Brown (msm8250 and msm8660) and
Shawn Guo (imx6q).
Cc: David Brown <davidb@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Acked-by: David Brown <davidb@codeaurora.org>
Tested-by: David Brown <davidb@codeaurora.org>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
commit ddd8478d68f8cf75ee9771667c0cbe2a9d1caeb9
Author: Trilok Soni <tsoni@codeaurora.org>
Date: Tue Dec 6 00:56:01 2011 +0530
msm: watchdog: Use request_percpu_irq() interface
Change-Id: I7c319344f6a7f7a7c70682ac87f5c385e56d130c
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
commit 0c19915e092214a4c17a9920c4c1f3d78610217d
Author: Sathish Ambley <sambley@codeaurora.org>
Date: Fri Dec 9 17:07:37 2011 +0530
arm: arch_timer: Use request_percpu_irq() API
Change-Id: Iee9b218d538f315cd884a47d95bcc0dcc49b0fe1
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Change-Id: I7bbba706b1f2e55814be5891ed76063725c2bfb1
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
[tsoni@codeaurora.org: MSM specific fixes]
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
SD card detect GPIO line can be ACTIVE HIGH or ACTIVE LOW based on the way
the board is designed. This change will allow the polarity information to
be used when determining if a card was inserted or removed for a given
board.
CRs-fixed: 318036
Change-Id: I30b96e840a28030af3141fd722383722a24089c8
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
ARM uses its own BUG() handler which makes its output slightly different
from other archtectures.
One of the problems is that the ARM implementation doesn't report the function
with the BUG() in it, but always reports the PC being in __bug(). The generic
implementation doesn't have this problem.
Currently we get something like:
kernel BUG at fs/proc/breakme.c:35!
Unable to handle kernel NULL pointer dereference at virtual address 00000000
...
PC is at __bug+0x20/0x2c
With this patch it displays:
kernel BUG at fs/proc/breakme.c:35!
Internal error: Oops - undefined instruction: 0 [#1] PREEMPT SMP
...
PC is at write_breakme+0xd0/0x1b4
This implementation uses an undefined instruction to implement BUG, and sets up
a bug table containing the relevant information. Many versions of gcc do not
support %c properly for ARM (inserting a # when they shouldn't) so we work
around this using distasteful macro magic.
v1: Initial version to replace existing ARM BUG() implementation with something
more similar to other architectures.
v2: Add Thumb support, remove backtrace whitespace output changes. Change to
use macros instead of requiring the asm %d flag to work (thanks to
Dave Martin <dave.martin@linaro.org>)
v3: Remove old BUG() implementation in favor of this one.
Remove the Backtrace: message (will submit this separately).
Use ARM_EXIT_KEEP() so that some architectures can dump exit text at link time
thanks to Stephen Boyd <sboyd@codeaurora.org> (although since we always
define GENERIC_BUG this might be academic.)
Rebase to linux-2.6.git master.
v4: Allow BUGS in modules (these were not reported correctly in v3)
(thanks to Stephen Boyd <sboyd@codeaurora.org> for suggesting that.)
Remove __bug() as this is no longer needed.
v5: Add %progbits as the section flags.
Change-Id: I9f588a06ddd739138fddfa6a5bf67079796e68eb
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
When the cpu is powered down in a low power mode, the gic cpu
interface may be reset, and when the cpu cluster is powered
down, the gic distributor may also be reset.
This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save
and restore the gic cpu interface registers, and the
CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save
and restore the gic distributor registers.
Change-Id: Ifad58fe6c9068d48b0515e444ae528619e036125
Original-author: Gary King <gking@nvidia.com>
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-and-Acked-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Vishwanath BS <vishwanath.bs@ti.com>
[kumarrav@codeaurora.org: fixup gic.h merge conflict]
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
Annotate the low level hardware locks which must not be preempted.
In mainline this change documents the low level nature of
the lock - otherwise there's no functional difference. Lockdep
and Sparse checking will work as usual.
Change-Id: I1c73fd5472b9ab356173637a7819095394004ebf
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
[kumarrav@codeaurora.org: fixup gic.c and cache-l2x0.c merge conflict]
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
* changes:
arm: common: Makefile: Add cpaccess
ARM: cpaccess: write-enables kernel space for write
mm: add wrapper function for writing word to kernel text space
The msm specific implementation of io_remap_pfn_range is no
longer applicable to current generation of msm targets.
Remove the implementation to avoid any potential remapping
to a wrong memory type.
Change-Id: I5cd5e0459c594e240f138dcdb37aef7c4698bea1
Signed-off-by: Naveen Ramaraj <nramaraj@codeaurora.org>
Adds a function to encapsulate the locking, removal of write-protection,
word write, cache flush and invalidate and restoration
of write protection. This is a convenience function for callers
needing to update a word in kernel text space.
Change-Id: I9832f0ff659ddc62c55819af5318c94b70f5c11c
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Add support for the A15 generic timer and clocksource.
As the timer generates interrupts on a different PPI depending
on the execution mode (normal or secure), it is possible to
register two different PPIs.
Change-Id: Ibaddc7f174bc168cef579b66ab06b966878ae155
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Since Samsung EXYNOS4210 cannot support register banking in GIC,
so needs to update CPU interface base address.
The 'gic_chip_data' is used for it, this patch moves gic_chip_data
structure declaraton to arch/arm/include/asm/hardware/gic.h to use
it.
Change-Id: I3adb614a72de3fd64f523f03795ae67ee38e9968
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
[kumarrav@codeaurora.org: Add back internal QuIC changes to gic_chip_data]
Signed-off-by: Ravi Kumar <kumarrav@codeaurora.org>
bank_pfn_end macro overflows when physical memory space
configuration ends at 0xFFFFFFFF.
The macro adds start and size together before converting
to a page frame number. Change the macro to convert start
and size first and then add them together.
Change-Id: If091fd860e6cc94f2221164bd79bf34415819e66
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
* common/android-3.0: (570 commits)
misc: remove kernel debugger core
ARM: common: fiq_debugger: dump sysrq directly to console if enabled
ARM: common: fiq_debugger: add irq context debug functions
net: wireless: bcmdhd: Call init_ioctl() only if was started properly for WEXT
net: wireless: bcmdhd: Call init_ioctl() only if was started properly
net: wireless: bcmdhd: Fix possible memory leak in escan/iscan
cpufreq: interactive governor: default 20ms timer
cpufreq: interactive governor: go to intermediate hi speed before max
cpufreq: interactive governor: scale to max only if at min speed
cpufreq: interactive governor: apply intermediate load on current speed
ARM: idle: update idle ticks before call idle end notifier
input: gpio_input: don't print debounce message unless flag is set
net: wireless: bcm4329: Skip dhd_bus_stop() if bus is already down
net: wireless: bcmdhd: Skip dhd_bus_stop() if bus is already down
net: wireless: bcmdhd: Improve suspend/resume processing
net: wireless: bcmdhd: Check if FW is Ok for internal FW call
tcp: Don't nuke connections for the wrong protocol
ARM: common: fiq_debugger: make uart irq be no_suspend
net: wireless: Skip connect warning for CONFIG_CFG80211_ALLOW_RECONNECT
mm: avoid livelock on !__GFP_FS allocations
...
Conflicts:
arch/arm/mm/cache-l2x0.c
arch/arm/vfp/vfpmodule.c
drivers/mmc/core/host.c
kernel/power/wakelock.c
net/bluetooth/hci_event.c
Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
This patch adds support for the Cortex-A15 PMU to the ARMv7
perf-event backend.
Change-Id: I1f7824c901a8c70bf66bdbb3976b506f5addeb6f
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This patch adds support for the Cortex-A5 PMU to the ARMv7 perf-event
backend.
Change-Id: Ib8f02b766145cedf59656adcc0cb8fec47bebe6e
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
With SDCC4, MCI_VERSION register holds the specific version information.
This information can be used to identify the controller version instead
of maintaining platform data in the board files.
CRs-Fixed: 313620
Change-Id: Ib745e83a52ba9e2e5b38d0989abd579d0e748c81
Signed-off-by: Pratibhasagar V <pratibha@codeaurora.org>
Modern ARMv7-A cores can optionally implement these new hardware
features:
- VFPv4:
The latest version of the ARMv7 vector floating-point extensions,
including hardware support for fused multiple accumulate. D16 or D32
variants may be implemented.
- Integer divide:
The SDIV and UDIV instructions provide signed and unsigned integer
division in hardware. When implemented, these instructions may be
available in either both Thumb and ARM, or Thumb only.
This patch adds new HWCAP defines to describe these new features. The
integer divide capabilities are split into two bits for ARM and Thumb
respectively. Whilst HWCAP_IDIVA should never be set if HWCAP_IDIVT is
clear, separating the bits makes it easier to interpret from userspace.
Change-Id: I05216fce45adf90b5a507b534146b28be0e1b7a0
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
The HWCAP numbers are defined as constants, each one being a power of 2.
This has become slightly unwieldy now that we have reached 32k.
This patch changes the HWCAP defines to use (1 << n) instead of coding
the constant directly. The values remain unchanged.
Change-Id: I2037d3bc8a3b928f8175736d459764020f4e4a9c
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
STRICT_MEMORY_RWX write-protects the kernel text section. This
is a problem for tools such as kprobes which need write access
to kernel text space.
This patch introduces a function to temporarily make part of the
kernel text space writeable and another to restore the original state.
They can be called by code which is intentionally writing to
this space, while still leaving the kernel protected from
unintentional writes at other times.
Change-Id: I879009c41771198852952e5e7c3b4d1368f12d5f
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Instead of controlling the GPIO that powers up SD/MMC cards
in SDC1 slot from the board file, make use of the gpio-regulator
driver and control the regulator from the SD/MMC driver.
Change-Id: I820ac334f69fb41a79a074eddfe38930a0d30bb3
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
This allows the platform specific drivers to properly enable
and disable the uart at the appropriate times. On some platforms, just
managing the clock is not enough.
Change-Id: I5feaab04cfe313a4a9470ca274838676b9684201
Signed-off-by: Dima Zavin <dima@android.com>
Due to changes of the order of initialization of
the ARM-specfic memory management code in 3.0, it
is necessary to create a way to call platform specific
code earlier than is currently possible.
Change-Id: I77dae10c85085358f7240889a50b78b07d5af6d1
Signed-off-by: Larry Bassel <lbassel@codeaurora.org>
In order to be able to handle IPI directly from C code instead of
assembly code, introduce handle_IPI(), which is modeled after handle_IRQ().
Change-Id: I5f6ff150899dc05e7935b07a3287f7c7e7804884
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
This patch adds irq_domain infrastructure for translating from
hardware irq numbers to linux irqs. This is particularly important
for architectures adding device tree support because the current
implementation (excluding PowerPC and SPARC) cannot handle
translation for more than a single interrupt controller. irq_domain
supports device tree translation for any number of interrupt
controllers.
This patch converts x86, Microblaze, ARM and MIPS to use irq_domain
for device tree irq translation. x86 is untested beyond compiling it,
irq_domain is enabled for MIPS and Microblaze, but the old behaviour is
preserved until the core code is modified to actually register an
irq_domain yet. On ARM it works and is required for much of the new
ARM device tree board support.
PowerPC has /not/ been converted to use this new infrastructure. It
is still missing some features before it can replace the virq
infrastructure already in powerpc (see documentation on
irq_domain_map/unmap for details). Followup patches will add the
missing pieces and migrate PowerPC to use irq_domain.
SPARC has its own method of managing interrupts from the device tree
and is unaffected by this change.
Change-Id: Ia5fa674a97c85e2fc8e30275753b1494a97bd1d9
Acked-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
This patch adds a DT_MACHINE_START macro to use instead of
MACHINE_START when creating a machine_desc that supports using the
device tree.
Change-Id: I8d499ec0e3575b67f8dd886a9496d9b1940b6368
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Sathish Ambley <sambley@codeaurora.org>
Based on a rough patch by frank.rowand@am.sony.com
Since ARM doesn't have an NMI (fiq's are not always available),
send an IPI to all other CPUs (current cpu prints the stack directly)
to capture a backtrace.
Change-Id: I8b163c8cec05d521b433ae133795865e8a33d4e2
Signed-off-by: Dima Zavin <dima@android.com>
Commit 'ad3b6993' converted ARM smp_cross_call() to take IPI number
as a parameter to handle more event than SGI and do_IPI was suppose
to recover SGI number. But the do_IPI doesn't consider it and it's
getting detected as 'Unknown IPI message 0x1' with ipi numbers are
moved to starts from 'IPI_TIMER=2"
There can be 16 different SGI but only SGI1 is used as IPI so
only that one is handled in do_IPI as IPI_CPU_START.
Added IPI_CPU_START because it wasn't used and thought it's
appropriate. Not sure whether its the right one.
Change-Id: I4dbe7c489d9611fbbb4036c15ac247659fde4119
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Russell King <rmk+kernel at arm.linux.org.uk>
[johlstei@codeaurora.org: fixed bounds check error]
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Introduce optional ticket locks to help ensure fairness in
contended locks, as well as preventing livelock.
CRs-fixed: 302764
Signed-off-by: Brent DeGraaf <bdegraaf@codeaurora.org>
Conflicts:
arch/arm/include/asm/spinlock.h
Add a missing header include to fix a compilation error for
omap2plus_defconfig on msm-3.0 tree.
Change-Id: I9ea45910651ef63258c90035bb9b5480c52ffe01
Signed-off-by: Naveen Ramaraj <nramaraj@codeaurora.org>
This avoids the irq entry assembly corrupting r5, thereby allowing it
to be preserved through to the svc exit code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
On Mon, Jul 11, 2011 at 3:52 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
...
> The __exception annotation on a function causes this to happen:
>
> [<c002406c>] (asm_do_IRQ+0x6c/0x8c) from [<c0024b84>]
> (__irq_svc+0x44/0xcc)
> Exception stack(0xc3897c78 to 0xc3897cc0)
> 7c60:
4022d320 4022e000
> 7c80: 08000075 00001000 c32273c0 c03ce1c0 c2b49b78 4022d000
c2b420b4 00000001
> 7ca0: 00000000 c3897cfc 00000000 c3897cc0 c00afc54 c002edd8
00000013 ffffffff
>
> Where that stack dump represents the pt_regs for the exception which
> happened. Any function found in while unwinding will cause this to
> be printed.
>
> If you insert a C function between the IRQ assembly and asm_do_IRQ,
> the
> dump you get from asm_do_IRQ will be the stack for your function,
> not
> the pt_regs. That makes the feature useless.
>
When __irq_svc - or any of the other exception handling assembly code -
calls the C code, the stack pointer will be pointing at the pt_regs
structure.
All the entry points into C code from the exception handling code are
marked with __exception or __exception_irq_enter to indicate that they
are one of the functions which has pt_regs above them.
Normally, when you've entered asm_do_IRQ() you will have this stack
layout (higher address towards top):
pt_regs
asm_do_IRQ frame
If you insert a C function between the exception assembly code and
asm_do_IRQ, you end up with this stack layout instead:
pt_regs
your function frame
asm_do_IRQ frame
This means when we unwind, we'll get to asm_do_IRQ, and rather than
dumping out the pt_regs, we'll dump out your functions stack frame
instead, because that's what is above the asm_do_IRQ stack frame
rather than the expected pt_regs structure.
The fix is to introduce handle_IRQ() for no exception stack dump, so
it can be called with MULTI_IRQ_HANDLER is selected and a C function
is between the assembly code and the actual IRQ handling code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
