Add /sys/kernel/debug/kgsl/kgsl-3d0/postmortem/ib_enabled to debugfs,
to control whether IBs are dumped by postmortem dump. Add check to
postmortem dump to dump registers if register dump is enabled.
By default ib dump and register dump during postmortem dump are
disabled.
Change-Id: I71b0b0c97be0753f88f6f57a1cbc6b5ee93aaffc
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>
Set the correct GMEM and istore sizes for A320 on APQ8064.
The more GMEM we have the happier we are, so the code will
work with 256K, but it will be better with 512K. For the
instruction store the size is important during GPU snapshot
and postmortem dump. Also, the size of each instruction is
different on A3XX so remove the hard coded constants and
add a GPU specific size variable.
Change-Id: Ic0dedbad01d5a9dc4211a666bc0a065189938841
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
ADRENO_ISTORE_START is valuable information for
a number of functions, so move it from within
adreno_debugfs.c to adreno.h.
Change-Id: Ic0dedbad41445fad2130b7cb28d706283f59b4c2
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
This has not been found to be useful for hang debugging.
Change-Id: Ie8cfb6bcbb8f81d8da903d5062bc75fcc4c3bee4
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
This GPU has a larger instruction store, so more memory
needs to be reserved for saving shader state when context
switching.
The initial vertex and pixel partitioning of the
instruction store also needs to be different.
Change-Id: If60c06467dd30d5bae07302a74eaf2687900b2b8
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
There are times when the adreno device is heavily loaded. Here, a
predetermined wait timeout value will not be useful. The configurability
introduced with this change will help in understanding the behaviour and
to tune the value. Will also be helpful in quickly identifying problems
that arise when the irqs don't fire.
Signed-off-by: Ranjhith Kalisamy <ranjhith@codeaurora.org>
The MH block should be initialized even if the gpu mmu
is not enabled so that AXI error interrupts will still
be generated.
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
