When the chip is soft reset but the PHY is not, the ethernet
link does not come up. The PHY and MAC go out of sync. Reseting
PHY starts auto-negotiation.
Change-Id: I379774908dc8a536080cc1d5600eeda57da28e88
Acked-by: Kaushik Sikdar <ksikdar@qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Added support for RGMII (1G) phys, sysfs/mdio and minor enhancements.
Change-Id: Icffb3965855369430c2d831a7aa1bd1fb73f9951
Acked-by: Kaushik Sikdar <ksikdar@qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
This adds multicast support to the qfec driver. The driver
is Level 2 compliant. It can send and receive multicast traffic.
Acked-by: Kaushik Sikdar <ksikdar@qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
This patch correct configuration of timestamp registers,
adds sysfs cmd and tstamp files to capture system-time
and display current timestamp.
Acked-by: Kaushik Sikdar <ksikdar@qualcomm.com>
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
