After writeback_stop() is called, we continue providing buffers to mdp
until the free queue is completely exhausted. However, client can
deallocate buffers immediately after writeback_stop() is called, this
will trigger page faults from mdp accessing invalid buffers.
Change-Id: Ibe3c8435a5f84eeb61b92ec3277f0dc27f008b02
Signed-off-by: Deva Ramasubramanian <dramasub@codeaurora.org>
Remove the boiler plate workqueue and proxy voting code and move
to the common proxy infrastructure that the core pil code
provides. This has the added benefit of fixing any issues where
suspend happens before the proxy vote is removed.
Change-Id: Idb7a73f21c1112d42e760d7249557b08755ddcbf
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Remove the boiler plate workqueue and proxy voting code and move
to the common proxy infrastructure that the core pil code
provides. This has the added benefit of fixing any issues where
suspend happens before the proxy vote is removed.
Change-Id: I7645b9297a0811e848a780e8963de204104b3997
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Remove the boiler plate workqueue and wakelock code and move to
the common proxy infrastructure that the core pil code provides.
Change-Id: I120006137d2f76cc8a2a71151111608464de3083
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Almost each pil driver needs to proxy vote for certain resources
that the secure code cannot handle. Instead of repeating the same
boiler plate code in each pil driver move the proxy voting and
callback scheduling to the core. A driver is expected to provide
a proxy_vote and proxy_unvote function if proxy voting is
required.
Call the proxy_vote before booting the processor and remove the
proxy vote after the alloted timeout. If the driver doesn't
provide a timeout remove the proxy immediately after the
processor is booted. Also flush any pending works during shutdown
so that proxy votes don't linger.
Change-Id: I13322b5bfb040fd76cdfc0228771d076addf6559
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
A disabled IRQ that is configured as a wakeup interrupt will trigger
a system resume, however since it is disabled, its handler will never
get called and its status register is never cleared. Thus upon
subsequent suspends it causes the system to immediately resume.
This was happening in the EHCI HSIC controller, in which remote wakeup
signaling on the STROBE line is treated as a wakeup IRQ. After the
first successful wakeup sequence, when the HSIC bus goes back into low
power mode the lingering uncleared interrupt prevents a system suspend
from executing successfully. This is fixed by enabling the IRQ in the
system suspend_noirq callback. The IRQ is subsequently disabled in
either the IRQ handler or the resume callback, whichever occurs first.
CRs-fixed: 343414
Change-Id: Ifc1c267408e76b98b8d848abde6eb44df9e0cdc0
Signed-off-by: Jack Pham <jackp@codeaurora.org>
This option enables PMIC interrupt support. Also enable
CONFIG_MSM_QPNP, since it is a dependency of CONFIG_MSM_QPNP_INT.
Change-Id: I432c22631db777c9e9213f7ebf8d506e480e1ed7
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
MSM_QPNP provides the qpnp_get_irq() API that is used by
client drivers using QPNP interrupts.
Change-Id: I4556b07a2c6b8dfeda860ebac57be6eb14f216b1
Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
When the modem crashes, it either sends an SMSM interrupt
with the modem SMSM_RESET bit set, or it triggers the
modem watchdog interrupt to the apps processor. Do not
set the apps SMSM_RESET bit in either case, as this will
trigger other subsystem drivers to restart their
individual subsystems.
CRs-fixed: 345622
Change-Id: I03680eedaa8f522c7727acd1e3fe92564c818d0d
Signed-off-by: Vikram Mulukutla <markivx@codeaurora.org>
Clean up some error paths and simplify the code by
moving to devm_regulator_get().
Change-Id: I00782fd15f505002a044efadb8abdcd4adda6cc6
Signed-off-by: Mayank Rana <mrana@codeaurora.org>
On the RPM turning on the CXO_CLK resource turns on the D0
resource. Voting on the D0 resource doesn't do much besides
toggle the buffer on the PMIC. Since the D0_EN signal coming from
the MSM dictates if the buffer is on or not using the D0 buffer
resource is essentially a nop.
Remap the D0 buffer users to the CXO clock in the clock driver so
that the callers of the API don't have to deal with this problem.
Once the RPM properly separates the D0 buffer from the CXO_CLK
resource we can remove this.
Change-Id: I3d69fab415913489b70555e7e7e871000835f346
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Add a boot parameter to the board display file to support runtime
enablement of HDMI as primary display for APQ8064.
Change-Id: I645fe08df90352ae6344ae6f0fed19fcea3b3f67
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
Organize the code to add IOMMU devices into per-target
blocks to make the code easier to maintain.
Change-Id: I8127b587d087ae2b05d3be5b207cd5e514e7247c
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
During the SDCC DMA transfer, if DMA transfer time is
long enough to do IDLE power collapse then system may
go into IDLE power collapse and once SDCC DMA transfer
is completed, system wakes up from Idle Power Collapse
due to SDCC DMA interrupt. But delay for waking up
from Idle Power collapse could be as large as 5 ms which
really degrades the overall read & write throughputs
for SD/eMMC/SDIO cards.
For example, following are the performance numbers with
eMMC card on MSM8960 platform with and without Idle Power
Collapse.
Idle Power collapse enabled:
LMDD Read throughput = ~14 MB/s
LMDD Write throughput = ~6 MB/s
Idle Power Collapse disabled:
LMDD Read throughput = ~25 MB/s
LMDD Write throughput = ~8 MB/s
So this change votes against the Idle power collapse by registering
with PM QOS about it's acceptable DMA latency when SDCC transfer is
active. This latency value is one more than the latency of SWFI
which means system can go into SWFI but not in any of the other
low power modes (including Idle power collapse).
Change-Id: I2c8de5e9b4204468f9166aea7bcdee5b70ed62b1
Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: Krishna Konda <kkonda@codeaurora.org>
Add new ioctls for per context timestamps.
Timestamp functions (read/write/wait) will now be context
specific rather than only using the global timestamp.
Per context timestamps is a requirement for priority
based queueing.
Change-Id: I5fdfb816480241b9552ecf90ed1bb22db3a652b5
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
We have moved to unification of IO address map for 7x27a/7x30 with 8k.
This now means that the header files(msm_iomap-7x30.h and
msm_iomap-7xxx.h) will included whichever target gets compiled,
so now we cannot keep the macro MSM_DEBUG_UART_PHYS in both the
files which has different physical address.
Thus moving to CONFIG_MSM_DEBUG_UART_PHYS which gets selected
from Kconfig based on the target selected.
Change-Id: I024e685d7ce2f5df0db49c482cd5d8541884e054
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Memory mapped through kgsl_mmu_map_global() is supposed to have
the same gpu address in all pagetables. And the memdesc will
persist beyond the lifetime of any single pagetable.
Therefore, memdesc->gpuaddr should not be zeroed for these
memdescs.
Change-Id: I0f46aaee2b9e87f839e78b7978cdf1bb4239d6f5
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
QSECOM requires a total of 6MB for concurrent
use. The memory is divided between HDCP (3M),
Playready (2M), and QSEECOM (1M).
Increase the QSECOM heap from 3MB to 6MB.
Change-Id: If57641f0dd656f7ea080319490fe476d3a48c059
Signed-off-by: Olav Haugan <ohaugan@codeaurora.org>
Migrate WFD to IOMMU APIs. Commit contains following changes:
- Switch from allocate buffer model to use buffer model in order
to have the flexibility to map buffers into seperate domains.
- Use the ION caching APIs to flush buffers in case they are cached.
Earlier on, we used uncached buffers, hence we didn't have a need
to flush.
Change-Id: I959027ee94a5d6074005f1de420c66cbe55db776
Signed-off-by: Deva Ramasubramanian <dramasub@codeaurora.org>
The first_set_call flag was used to ensure that initial voltage and bus
requests were asserted during the first call to acpuclk_set_rate(),
which would have otherwise returned early if the CPU was already set to
the target speed from init. This was unclean, and depended on
acpuclk_set_rate() being called during boot (before vdd_dig, vdd_mem,
and bus clocks were allowed to scale).
As of commit cfe192bebe, bus bandwidth
and Krait voltage requests are already initialized during init and no
longer rely on the first_set_call flag. If vdd_dig and vdd_mem requests
are also initialized at that same time, we can remove our dependence on
the flag altogether. Do this.
Change-Id: I9adb5865bf90a8a781b82f1d2c5b9154848c90ad
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
External Power Monitor(EPM) uses the external ADS1158 ADC
to measure voltage and current. Each ADS1158 ADC supports
measuring 16 Analog input channels.
APQ8064 has support for 2ADS ADC and can measure upto 32
analog input channels. The power to the EPM uses a
SX1509 I2C expander to enable the ADS ADC. Depending on
the input channel the appropriate chip select is de-asserted
to select the ADS ADC to measure the input signal. The
ADS1158 chip is configured through the SPI interface.
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
Change-Id: Ib9f36606b6b183f75754b7763dbe45455c779327
Fix issue where if a SCO connection is initiated during an AMP
OBEX transfer the fallback to BR-EDR fails and the OBEX connection
is disconnected.
When moving a channel back to BR-EDR L2CAP must allow for receiving
a Move Channel Response with Pending status before receiving the
Response with Success status.
Change-Id: I017bf607fa8ab5d0d582d61538c9a0e5ec25cd26
CRs-fixed: 341363
Signed-off-by: Peter Krystad <pkrystad@codeaurora.org>
Previously, the krait rail voltage is calculated by the maximum
of krait core voltage and the hfpll voltage given a freq level.
However, the hfpll voltage has been taken into account when
the hardware designers provide the krait core voltage value
for each freq level, which means this voltage is good for the
hfpll as well. Therefore, clean up the calculation by just using
the krait core's voltage.
Change-Id: I1706de84aa227e47b3018e84a68194fc90ca5001
Signed-off-by: Tianyi Gou <tgou@codeaurora.org>
When a QMI/RMNET control connection is established, a diag
reset causes a crash due to a NULL pointer dereference. The
SMD channel pointer is set to NULL upon USB cable disconnect,
but a queued work function might still try to access that pointer.
Fix the crash by checking for NULL pointers in both smd_* and in
USB gadget transport functions that could pass a closed handle.
CRs-fixed: 336850
Change-Id: I87cb109f3e7007efe15b5acc81180151dd2ef023
Signed-off-by: Jack Pham <jackp@codeaurora.org>
SD/MMC card erase functionality is available in core
layer. Enable MMC_CAP_ERASE capability from host side
so that users can use erase, trim, secure erase, secure trim
operations based on the card capability.
Change-Id: Icf35cd3038b0a95d653387d42870357c4c3853c0
Signed-off-by: Sujit Reddy Thumma <sthumma@codeaurora.org>
This driver includes voltage regulator configuration,
clock configuration, sensor gpio settings and sensor
register settings to enable preview and snapshot for
Sony IMX091 sensor.
Change-Id: Ib974e78bdb4310350c27eda20e0cc49e4c34916e
Signed-off-by: Sreesudhan Ramakrish Ramkumar <srramku@codeaurora.org>
BLSP-QUP core 9 (also referred as I2C10) is added to Device-Tree
for copper. This core is used by I2C EEPROM.
Change-Id: Ib3af7ae305ef11ac415462504b736d7a9bc87092
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
MDM9615 has identical configuration for the number
of sensors and slope with MSM8960. Add support to
enable the TSENS for calibrated parts.
Change-Id: Ieb1f118ce916ab5a4f079b18b11541d86c3a5560
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
