Enabling of CORE_ON_EN bit in qup_i2c driver is not dependent on soc.
Same code will work for all. Hence remove the SOC specific part from the
function.
CRs-Fixed: 335884
Change-Id: I55054b0c17e1710c1d268322f1a78c42c94b3db8
Signed-off-by: Pankaj Kumar <pakuma@codeaurora.org>
To disable the GSBI QuPE PCLKs it is important to enable
the CORE_ON_EN bit for some targets like 7x27a.
CRs-Fixed: 302634
Change-Id: I309d7aa0de435b18658e3bb1a879368d06610c5e
Signed-off-by: Trilok Soni <tsoni@codeaurora.org>
Replace use of clk_enable() and clk_disable() with calls to
clk_prepare_enable() and clk_disable_unprepare(), respectively.
Change-Id: Ib29b5e4340f1a8cbde85efe3d129470788cbf0cd
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
If slave pulls one of the I2C lines low,I2C bus may lock out
failing I2C transactions for all slaves on the GSBI.
Recovery mechanism is added to recover the I2C lines when this
happens. Also, we allow clients to retry when a connection error
is returned.
Change-Id: I12675d828d0880ded292724416b5407427cdf73c
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
When a transaction consists of multiple write requests, combine them
only when the addresses of the writes are the same.
Change-Id: I35089d7b3936acf2de28f075734da84069b83fb3
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
When a transaction consists of multiple write requests, add up the total
length of the write requests. If there is a read following the writes,
set the read mode appropriately.
Change-Id: I0c15e14fa4732e4e25f5bb885688662a066b8782
Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
We wait for FIFO number of bytes to ensure that the
I2C state machine is not idle.
Change-Id: I24d2a22ac261bd1b53ca57a83c812c3c9f0fbdc4
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
Drivers should now use their device names to distinguish between
clocks of the same type rather than the clock name.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
Conflicts:
arch/arm/mach-msm/board-qrdc.c
arch/arm/mach-msm/board-qt8660.c
If dynamic HW gating is enabled, it's required to have the QUP core
in RESET state before HW gating can take effect.
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
If QUP core is in PAUSE state then the state check returns true
for any other state incorrectly. Also, if the core is in RUN state
and it's being put in RESET, then RESET state check may return true
even if it's not out of RUN (and if VALID bit is set).
State mask is used to verify what state QUP core is in to avoid this
problem.
Signed-off-by: Sagar Dharia <sdharia@codeaurora.org>
