4a084e3e60
Create a board file for 8064 display. Allocate framebuffer memory and add board initialization information for msm_fb, mdp, lvds and rotator devices. Change-Id: Id2323c169f04f8a2a6d753ccdd9899ed3ecbd533 Signed-off-by: Huaibin Yang <huaibiny@codeaurora.org>
1275 lines
32 KiB
C
1275 lines
32 KiB
C
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/i2c.h>
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#include <linux/slimbus/slimbus.h>
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#include <linux/mfd/wcd9310/core.h>
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#include <linux/mfd/wcd9310/pdata.h>
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#include <linux/msm_ssbi.h>
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#include <linux/spi/spi.h>
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#include <linux/dma-mapping.h>
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#include <linux/platform_data/qcom_crypto_device.h>
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#include <linux/ion.h>
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#include <linux/memory.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/hardware/gic.h>
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#include <asm/mach/mmc.h>
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#include <mach/board.h>
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#include <mach/msm_iomap.h>
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#include <mach/ion.h>
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#include <linux/usb/msm_hsusb.h>
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#include <linux/usb/android.h>
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#include <mach/socinfo.h>
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#include <mach/msm_spi.h>
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#include "timer.h"
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#include "devices.h"
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#include <mach/gpio.h>
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#include <mach/gpiomux.h>
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#include <mach/rpm.h>
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#ifdef CONFIG_ANDROID_PMEM
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#include <linux/android_pmem.h>
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#endif
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#include <mach/msm_memtypes.h>
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#include <linux/bootmem.h>
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#include <asm/setup.h>
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#include <mach/dma.h>
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#include <mach/msm_bus_board.h>
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#include <mach/pm.h>
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#include <mach/cpuidle.h>
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#include "msm_watchdog.h"
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#include "board-8064.h"
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#include "acpuclock.h"
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#include "spm.h"
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#include "mpm.h"
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#include "rpm_resources.h"
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#include "pm-boot.h"
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#include "devices-msm8x60.h"
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#define MSM_PMEM_ADSP_SIZE 0x7800000
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#define MSM_PMEM_AUDIO_SIZE 0x2B4000
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#ifdef CONFIG_FB_MSM_HDMI_AS_PRIMARY
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#define MSM_PMEM_SIZE 0x4000000 /* 64 Mbytes */
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#else
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#define MSM_PMEM_SIZE 0x2800000 /* 40 Mbytes */
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#endif
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#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
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#define MSM_PMEM_KERNEL_EBI1_SIZE 0x280000
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#define MSM_ION_SF_SIZE MSM_PMEM_SIZE
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#define MSM_ION_MM_FW_SIZE 0x200000 /* (2MB) */
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#define MSM_ION_MM_SIZE MSM_PMEM_ADSP_SIZE
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#define MSM_ION_QSECOM_SIZE 0x100000 /* (1MB) */
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#define MSM_ION_MFC_SIZE SZ_8K
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#define MSM_ION_AUDIO_SIZE MSM_PMEM_AUDIO_SIZE
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#define MSM_ION_HEAP_NUM 8
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#else
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#define MSM_PMEM_KERNEL_EBI1_SIZE 0x110C000
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#define MSM_ION_HEAP_NUM 1
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#endif
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#ifdef CONFIG_KERNEL_PMEM_EBI_REGION
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static unsigned pmem_kernel_ebi1_size = MSM_PMEM_KERNEL_EBI1_SIZE;
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static int __init pmem_kernel_ebi1_size_setup(char *p)
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{
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pmem_kernel_ebi1_size = memparse(p, NULL);
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return 0;
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}
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early_param("pmem_kernel_ebi1_size", pmem_kernel_ebi1_size_setup);
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#endif
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#ifdef CONFIG_ANDROID_PMEM
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static unsigned pmem_size = MSM_PMEM_SIZE;
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static int __init pmem_size_setup(char *p)
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{
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pmem_size = memparse(p, NULL);
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return 0;
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}
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early_param("pmem_size", pmem_size_setup);
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static unsigned pmem_adsp_size = MSM_PMEM_ADSP_SIZE;
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static int __init pmem_adsp_size_setup(char *p)
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{
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pmem_adsp_size = memparse(p, NULL);
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return 0;
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}
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early_param("pmem_adsp_size", pmem_adsp_size_setup);
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static unsigned pmem_audio_size = MSM_PMEM_AUDIO_SIZE;
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static int __init pmem_audio_size_setup(char *p)
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{
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pmem_audio_size = memparse(p, NULL);
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return 0;
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}
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early_param("pmem_audio_size", pmem_audio_size_setup);
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#endif
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#ifdef CONFIG_ANDROID_PMEM
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#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
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static struct android_pmem_platform_data android_pmem_pdata = {
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.name = "pmem",
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.allocator_type = PMEM_ALLOCATORTYPE_ALLORNOTHING,
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.cached = 1,
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.memory_type = MEMTYPE_EBI1,
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};
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static struct platform_device android_pmem_device = {
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.name = "android_pmem",
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.id = 0,
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.dev = {.platform_data = &android_pmem_pdata},
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};
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static struct android_pmem_platform_data android_pmem_adsp_pdata = {
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.name = "pmem_adsp",
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.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
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.cached = 0,
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.memory_type = MEMTYPE_EBI1,
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};
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static struct platform_device android_pmem_adsp_device = {
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.name = "android_pmem",
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.id = 2,
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.dev = { .platform_data = &android_pmem_adsp_pdata },
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};
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#endif
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static struct android_pmem_platform_data android_pmem_audio_pdata = {
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.name = "pmem_audio",
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.allocator_type = PMEM_ALLOCATORTYPE_BITMAP,
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.cached = 0,
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.memory_type = MEMTYPE_EBI1,
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};
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static struct platform_device android_pmem_audio_device = {
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.name = "android_pmem",
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.id = 4,
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.dev = { .platform_data = &android_pmem_audio_pdata },
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};
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#endif
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static struct memtype_reserve apq8064_reserve_table[] __initdata = {
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[MEMTYPE_SMI] = {
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},
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[MEMTYPE_EBI0] = {
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.flags = MEMTYPE_FLAGS_1M_ALIGN,
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},
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[MEMTYPE_EBI1] = {
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.flags = MEMTYPE_FLAGS_1M_ALIGN,
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},
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};
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static void __init size_pmem_devices(void)
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{
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#ifdef CONFIG_ANDROID_PMEM
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#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
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android_pmem_adsp_pdata.size = pmem_adsp_size;
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android_pmem_pdata.size = pmem_size;
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#endif
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android_pmem_audio_pdata.size = MSM_PMEM_AUDIO_SIZE;
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#endif
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}
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static void __init reserve_memory_for(struct android_pmem_platform_data *p)
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{
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apq8064_reserve_table[p->memory_type].size += p->size;
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}
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static void __init reserve_pmem_memory(void)
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{
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#ifdef CONFIG_ANDROID_PMEM
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#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
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reserve_memory_for(&android_pmem_adsp_pdata);
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reserve_memory_for(&android_pmem_pdata);
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#endif
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reserve_memory_for(&android_pmem_audio_pdata);
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apq8064_reserve_table[MEMTYPE_EBI1].size += pmem_kernel_ebi1_size;
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#endif
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}
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static int apq8064_paddr_to_memtype(unsigned int paddr)
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{
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return MEMTYPE_EBI1;
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}
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#ifdef CONFIG_ION_MSM
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#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
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static struct ion_cp_heap_pdata cp_mm_ion_pdata = {
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.permission_type = IPT_TYPE_MM_CARVEOUT,
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.align = PAGE_SIZE,
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};
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static struct ion_cp_heap_pdata cp_mfc_ion_pdata = {
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.permission_type = IPT_TYPE_MFC_SHAREDMEM,
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.align = PAGE_SIZE,
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};
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static struct ion_co_heap_pdata co_ion_pdata = {
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.adjacent_mem_id = INVALID_HEAP_ID,
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.align = PAGE_SIZE,
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};
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static struct ion_co_heap_pdata fw_co_ion_pdata = {
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.adjacent_mem_id = ION_CP_MM_HEAP_ID,
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.align = SZ_128K,
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};
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#endif
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static struct ion_platform_data ion_pdata = {
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.nr = MSM_ION_HEAP_NUM,
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.heaps = {
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{
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.id = ION_SYSTEM_HEAP_ID,
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.type = ION_HEAP_TYPE_SYSTEM,
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.name = ION_VMALLOC_HEAP_NAME,
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},
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#ifdef CONFIG_MSM_MULTIMEDIA_USE_ION
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{
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.id = ION_SF_HEAP_ID,
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.type = ION_HEAP_TYPE_CARVEOUT,
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.name = ION_SF_HEAP_NAME,
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.size = MSM_ION_SF_SIZE,
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.memory_type = ION_EBI_TYPE,
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.extra_data = (void *) &co_ion_pdata,
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},
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{
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.id = ION_CP_MM_HEAP_ID,
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.type = ION_HEAP_TYPE_CP,
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.name = ION_MM_HEAP_NAME,
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.size = MSM_ION_MM_SIZE,
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.memory_type = ION_EBI_TYPE,
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.extra_data = (void *) &cp_mm_ion_pdata,
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},
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{
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.id = ION_MM_FIRMWARE_HEAP_ID,
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.type = ION_HEAP_TYPE_CARVEOUT,
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.name = ION_MM_FIRMWARE_HEAP_NAME,
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.size = MSM_ION_MM_FW_SIZE,
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.memory_type = ION_EBI_TYPE,
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.extra_data = (void *) &fw_co_ion_pdata,
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},
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{
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.id = ION_CP_MFC_HEAP_ID,
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.type = ION_HEAP_TYPE_CP,
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.name = ION_MFC_HEAP_NAME,
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.size = MSM_ION_MFC_SIZE,
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.memory_type = ION_EBI_TYPE,
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.extra_data = (void *) &cp_mfc_ion_pdata,
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},
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{
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.id = ION_IOMMU_HEAP_ID,
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.type = ION_HEAP_TYPE_IOMMU,
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.name = ION_IOMMU_HEAP_NAME,
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},
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{
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.id = ION_QSECOM_HEAP_ID,
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.type = ION_HEAP_TYPE_CARVEOUT,
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.name = ION_QSECOM_HEAP_NAME,
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.size = MSM_ION_QSECOM_SIZE,
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.memory_type = ION_EBI_TYPE,
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.extra_data = (void *) &co_ion_pdata,
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},
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{
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.id = ION_AUDIO_HEAP_ID,
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.type = ION_HEAP_TYPE_CARVEOUT,
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.name = ION_AUDIO_HEAP_NAME,
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.size = MSM_ION_AUDIO_SIZE,
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.memory_type = ION_EBI_TYPE,
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.extra_data = (void *) &co_ion_pdata,
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},
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#endif
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}
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};
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static struct platform_device ion_dev = {
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.name = "ion-msm",
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.id = 1,
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.dev = { .platform_data = &ion_pdata },
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};
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#endif
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static void reserve_ion_memory(void)
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{
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#if defined(CONFIG_ION_MSM) && defined(CONFIG_MSM_MULTIMEDIA_USE_ION)
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apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MM_SIZE;
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apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MM_FW_SIZE;
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apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_SF_SIZE;
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apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_MFC_SIZE;
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apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_QSECOM_SIZE;
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apq8064_reserve_table[MEMTYPE_EBI1].size += MSM_ION_AUDIO_SIZE;
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#endif
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}
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static void __init reserve_mdp_memory(void)
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{
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apq8064_mdp_writeback(apq8064_reserve_table);
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}
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static void __init apq8064_calculate_reserve_sizes(void)
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{
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size_pmem_devices();
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reserve_pmem_memory();
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reserve_ion_memory();
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reserve_mdp_memory();
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}
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static struct reserve_info apq8064_reserve_info __initdata = {
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.memtype_reserve_table = apq8064_reserve_table,
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.calculate_reserve_sizes = apq8064_calculate_reserve_sizes,
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.paddr_to_memtype = apq8064_paddr_to_memtype,
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};
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static int apq8064_memory_bank_size(void)
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{
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return 1<<29;
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}
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static void __init locate_unstable_memory(void)
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{
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struct membank *mb = &meminfo.bank[meminfo.nr_banks - 1];
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unsigned long bank_size;
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unsigned long low, high;
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bank_size = apq8064_memory_bank_size();
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low = meminfo.bank[0].start;
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high = mb->start + mb->size;
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/* Check if 32 bit overflow occured */
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if (high < mb->start)
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high = ~0UL;
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low &= ~(bank_size - 1);
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if (high - low <= bank_size)
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return;
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apq8064_reserve_info.low_unstable_address = mb->start -
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MIN_MEMORY_BLOCK_SIZE + mb->size;
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apq8064_reserve_info.max_unstable_size = MIN_MEMORY_BLOCK_SIZE;
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apq8064_reserve_info.bank_size = bank_size;
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pr_info("low unstable address %lx max size %lx bank size %lx\n",
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apq8064_reserve_info.low_unstable_address,
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apq8064_reserve_info.max_unstable_size,
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apq8064_reserve_info.bank_size);
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}
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static void __init apq8064_reserve(void)
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{
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reserve_info = &apq8064_reserve_info;
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locate_unstable_memory();
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msm_reserve();
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}
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static struct platform_device android_usb_device = {
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.name = "android_usb",
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.id = -1,
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};
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static struct msm_otg_platform_data msm_otg_pdata = {
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.mode = USB_PERIPHERAL,
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.otg_control = OTG_PHY_CONTROL,
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.phy_type = SNPS_28NM_INTEGRATED_PHY,
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};
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#define TABLA_INTERRUPT_BASE (NR_MSM_IRQS + NR_GPIO_IRQS + NR_PM8921_IRQS)
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/* Micbias setting is based on 8660 CDP/MTP/FLUID requirement
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* 4 micbiases are used to power various analog and digital
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* microphones operating at 1800 mV. Technically, all micbiases
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* can source from single cfilter since all microphones operate
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* at the same voltage level. The arrangement below is to make
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* sure all cfilters are exercised. LDO_H regulator ouput level
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* does not need to be as high as 2.85V. It is choosen for
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* microphone sensitivity purpose.
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*/
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static struct tabla_pdata apq8064_tabla_platform_data = {
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.slimbus_slave_device = {
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.name = "tabla-slave",
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.e_addr = {0, 0, 0x10, 0, 0x17, 2},
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},
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.irq = MSM_GPIO_TO_INT(42),
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.irq_base = TABLA_INTERRUPT_BASE,
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.num_irqs = NR_TABLA_IRQS,
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.reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
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.micbias = {
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.ldoh_v = TABLA_LDOH_2P85_V,
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.cfilt1_mv = 1800,
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.cfilt2_mv = 1800,
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.cfilt3_mv = 1800,
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.bias1_cfilt_sel = TABLA_CFILT1_SEL,
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.bias2_cfilt_sel = TABLA_CFILT2_SEL,
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.bias3_cfilt_sel = TABLA_CFILT3_SEL,
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.bias4_cfilt_sel = TABLA_CFILT3_SEL,
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}
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};
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static struct slim_device apq8064_slim_tabla = {
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.name = "tabla-slim",
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.e_addr = {0, 1, 0x10, 0, 0x17, 2},
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.dev = {
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.platform_data = &apq8064_tabla_platform_data,
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},
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};
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static struct tabla_pdata apq8064_tabla20_platform_data = {
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.slimbus_slave_device = {
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.name = "tabla-slave",
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.e_addr = {0, 0, 0x60, 0, 0x17, 2},
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},
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.irq = MSM_GPIO_TO_INT(42),
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.irq_base = TABLA_INTERRUPT_BASE,
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.num_irqs = NR_TABLA_IRQS,
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.reset_gpio = PM8921_GPIO_PM_TO_SYS(34),
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.micbias = {
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.ldoh_v = TABLA_LDOH_2P85_V,
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.cfilt1_mv = 1800,
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.cfilt2_mv = 1800,
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.cfilt3_mv = 1800,
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.bias1_cfilt_sel = TABLA_CFILT1_SEL,
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.bias2_cfilt_sel = TABLA_CFILT2_SEL,
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.bias3_cfilt_sel = TABLA_CFILT3_SEL,
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.bias4_cfilt_sel = TABLA_CFILT3_SEL,
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}
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};
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static struct slim_device apq8064_slim_tabla20 = {
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.name = "tabla2x-slim",
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.e_addr = {0, 1, 0x60, 0, 0x17, 2},
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.dev = {
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.platform_data = &apq8064_tabla20_platform_data,
|
|
},
|
|
};
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
|
|
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE) || \
|
|
defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
|
|
defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
|
|
|
|
#define QCE_SIZE 0x10000
|
|
#define QCE_0_BASE 0x11000000
|
|
|
|
#define QCE_HW_KEY_SUPPORT 0
|
|
#define QCE_SHA_HMAC_SUPPORT 1
|
|
#define QCE_SHARE_CE_RESOURCE 3
|
|
#define QCE_CE_SHARED 0
|
|
|
|
static struct resource qcrypto_resources[] = {
|
|
[0] = {
|
|
.start = QCE_0_BASE,
|
|
.end = QCE_0_BASE + QCE_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.name = "crypto_channels",
|
|
.start = DMOV8064_CE_IN_CHAN,
|
|
.end = DMOV8064_CE_OUT_CHAN,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
[2] = {
|
|
.name = "crypto_crci_in",
|
|
.start = DMOV8064_CE_IN_CRCI,
|
|
.end = DMOV8064_CE_IN_CRCI,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
[3] = {
|
|
.name = "crypto_crci_out",
|
|
.start = DMOV8064_CE_OUT_CRCI,
|
|
.end = DMOV8064_CE_OUT_CRCI,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
};
|
|
|
|
static struct resource qcedev_resources[] = {
|
|
[0] = {
|
|
.start = QCE_0_BASE,
|
|
.end = QCE_0_BASE + QCE_SIZE - 1,
|
|
.flags = IORESOURCE_MEM,
|
|
},
|
|
[1] = {
|
|
.name = "crypto_channels",
|
|
.start = DMOV8064_CE_IN_CHAN,
|
|
.end = DMOV8064_CE_OUT_CHAN,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
[2] = {
|
|
.name = "crypto_crci_in",
|
|
.start = DMOV8064_CE_IN_CRCI,
|
|
.end = DMOV8064_CE_IN_CRCI,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
[3] = {
|
|
.name = "crypto_crci_out",
|
|
.start = DMOV8064_CE_OUT_CRCI,
|
|
.end = DMOV8064_CE_OUT_CRCI,
|
|
.flags = IORESOURCE_DMA,
|
|
},
|
|
};
|
|
|
|
#endif
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
|
|
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
|
|
|
|
static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
|
|
.ce_shared = QCE_CE_SHARED,
|
|
.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
|
|
.hw_key_support = QCE_HW_KEY_SUPPORT,
|
|
.sha_hmac = QCE_SHA_HMAC_SUPPORT,
|
|
.bus_scale_table = NULL,
|
|
};
|
|
|
|
static struct platform_device qcrypto_device = {
|
|
.name = "qcrypto",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(qcrypto_resources),
|
|
.resource = qcrypto_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &qcrypto_ce_hw_suppport,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
|
|
defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
|
|
|
|
static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
|
|
.ce_shared = QCE_CE_SHARED,
|
|
.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
|
|
.hw_key_support = QCE_HW_KEY_SUPPORT,
|
|
.sha_hmac = QCE_SHA_HMAC_SUPPORT,
|
|
.bus_scale_table = NULL,
|
|
};
|
|
|
|
static struct platform_device qcedev_device = {
|
|
.name = "qce",
|
|
.id = 0,
|
|
.num_resources = ARRAY_SIZE(qcedev_resources),
|
|
.resource = qcedev_resources,
|
|
.dev = {
|
|
.coherent_dma_mask = DMA_BIT_MASK(32),
|
|
.platform_data = &qcedev_ce_hw_suppport,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
|
|
#define MSM_SHARED_RAM_PHYS 0x80000000
|
|
static void __init apq8064_map_io(void)
|
|
{
|
|
msm_shared_ram_phys = MSM_SHARED_RAM_PHYS;
|
|
msm_map_apq8064_io();
|
|
if (socinfo_init() < 0)
|
|
pr_err("socinfo_init() failed!\n");
|
|
}
|
|
|
|
static void __init apq8064_init_irq(void)
|
|
{
|
|
struct msm_mpm_device_data *data = NULL;
|
|
|
|
#ifdef CONFIG_MSM_MPM
|
|
data = &apq8064_mpm_dev_data;
|
|
#endif
|
|
|
|
msm_mpm_irq_extn_init(data);
|
|
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
|
|
(void *)MSM_QGIC_CPU_BASE);
|
|
|
|
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
|
|
writel_relaxed(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
|
|
|
|
writel_relaxed(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
|
|
mb();
|
|
}
|
|
|
|
static struct platform_device msm8064_device_saw_regulator_core0 = {
|
|
.name = "saw-regulator",
|
|
.id = 0,
|
|
.dev = {
|
|
.platform_data = &msm8064_saw_regulator_pdata_8921_s5,
|
|
},
|
|
};
|
|
|
|
static struct platform_device msm8064_device_saw_regulator_core1 = {
|
|
.name = "saw-regulator",
|
|
.id = 1,
|
|
.dev = {
|
|
.platform_data = &msm8064_saw_regulator_pdata_8921_s6,
|
|
},
|
|
};
|
|
|
|
static struct platform_device msm8064_device_saw_regulator_core2 = {
|
|
.name = "saw-regulator",
|
|
.id = 2,
|
|
.dev = {
|
|
.platform_data = &msm8064_saw_regulator_pdata_8821_s0,
|
|
},
|
|
};
|
|
|
|
static struct platform_device msm8064_device_saw_regulator_core3 = {
|
|
.name = "saw-regulator",
|
|
.id = 3,
|
|
.dev = {
|
|
.platform_data = &msm8064_saw_regulator_pdata_8821_s1,
|
|
|
|
},
|
|
};
|
|
|
|
static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
|
|
{
|
|
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
|
|
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
|
|
true,
|
|
100, 8000, 100000, 1,
|
|
},
|
|
|
|
{
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
|
|
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
|
|
true,
|
|
2000, 6000, 60100000, 3000,
|
|
},
|
|
|
|
{
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
|
|
MSM_RPMRS_LIMITS(ON, GDHS, MAX, ACTIVE),
|
|
false,
|
|
4200, 5000, 60350000, 3500,
|
|
},
|
|
|
|
{
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
|
|
MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
|
|
false,
|
|
6300, 4500, 65350000, 4800,
|
|
},
|
|
|
|
{
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
|
|
MSM_RPMRS_LIMITS(OFF, GDHS, MAX, ACTIVE),
|
|
false,
|
|
11700, 2500, 67850000, 5500,
|
|
},
|
|
|
|
{
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
|
|
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
|
|
false,
|
|
13800, 2000, 71850000, 6800,
|
|
},
|
|
|
|
{
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
|
|
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
|
|
false,
|
|
29700, 500, 75850000, 8800,
|
|
},
|
|
|
|
{
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
|
|
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
|
|
false,
|
|
29700, 0, 76350000, 9800,
|
|
},
|
|
};
|
|
|
|
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
|
|
.mode = MSM_PM_BOOT_CONFIG_TZ,
|
|
};
|
|
|
|
static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
|
|
.levels = &msm_rpmrs_levels[0],
|
|
.num_levels = ARRAY_SIZE(msm_rpmrs_levels),
|
|
.vdd_mem_levels = {
|
|
[MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
|
|
[MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
|
|
[MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
|
|
[MSM_RPMRS_VDD_MEM_MAX] = 1150000,
|
|
},
|
|
.vdd_dig_levels = {
|
|
[MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
|
|
[MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
|
|
[MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
|
|
[MSM_RPMRS_VDD_DIG_MAX] = 1150000,
|
|
},
|
|
.vdd_mask = 0x7FFFFF,
|
|
.rpmrs_target_id = {
|
|
[MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
|
|
[MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
|
|
[MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8921_S3_0,
|
|
[MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8921_S3_1,
|
|
[MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8921_L24_0,
|
|
[MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8921_L24_1,
|
|
[MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
|
|
},
|
|
};
|
|
|
|
static struct msm_cpuidle_state msm_cstates[] __initdata = {
|
|
{0, 0, "C0", "WFI",
|
|
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
|
|
|
|
{0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
|
|
|
|
{0, 2, "C2", "POWER_COLLAPSE",
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
|
|
|
|
{1, 0, "C0", "WFI",
|
|
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
|
|
|
|
{1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
|
|
|
|
{2, 0, "C0", "WFI",
|
|
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
|
|
|
|
{2, 1, "C1", "STANDALONE_POWER_COLLAPSE",
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
|
|
|
|
{3, 0, "C0", "WFI",
|
|
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
|
|
|
|
{3, 1, "C1", "STANDALONE_POWER_COLLAPSE",
|
|
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
|
|
};
|
|
|
|
static struct msm_pm_platform_data msm_pm_data[] = {
|
|
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 0,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 0,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 1,
|
|
.suspend_enabled = 1,
|
|
},
|
|
|
|
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
|
|
.idle_supported = 0,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 0,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 0,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 0,
|
|
.idle_enabled = 1,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
|
|
.idle_supported = 0,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 0,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 0,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 0,
|
|
.idle_enabled = 1,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
|
|
.idle_supported = 0,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 0,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 1,
|
|
.idle_enabled = 0,
|
|
.suspend_enabled = 0,
|
|
},
|
|
|
|
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
|
|
.idle_supported = 1,
|
|
.suspend_supported = 0,
|
|
.idle_enabled = 1,
|
|
.suspend_enabled = 0,
|
|
},
|
|
};
|
|
|
|
static uint8_t spm_wfi_cmd_sequence[] __initdata = {
|
|
0x03, 0x0f,
|
|
};
|
|
|
|
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
|
|
0x00, 0x24, 0x54, 0x10,
|
|
0x09, 0x03, 0x01,
|
|
0x10, 0x54, 0x30, 0x0C,
|
|
0x24, 0x30, 0x0f,
|
|
};
|
|
|
|
static uint8_t spm_power_collapse_with_rpm[] __initdata = {
|
|
0x00, 0x24, 0x54, 0x10,
|
|
0x09, 0x07, 0x01, 0x0B,
|
|
0x10, 0x54, 0x30, 0x0C,
|
|
0x24, 0x30, 0x0f,
|
|
};
|
|
|
|
static struct msm_spm_seq_entry msm_spm_seq_list[] __initdata = {
|
|
[0] = {
|
|
.mode = MSM_SPM_MODE_CLOCK_GATING,
|
|
.notify_rpm = false,
|
|
.cmd = spm_wfi_cmd_sequence,
|
|
},
|
|
[1] = {
|
|
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
|
|
.notify_rpm = false,
|
|
.cmd = spm_power_collapse_without_rpm,
|
|
},
|
|
[2] = {
|
|
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
|
|
.notify_rpm = true,
|
|
.cmd = spm_power_collapse_with_rpm,
|
|
},
|
|
};
|
|
|
|
static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = {
|
|
0x00, 0x20, 0x03, 0x20,
|
|
0x00, 0x0f,
|
|
};
|
|
|
|
static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = {
|
|
0x00, 0x20, 0x34, 0x64,
|
|
0x48, 0x07, 0x48, 0x20,
|
|
0x50, 0x64, 0x04, 0x34,
|
|
0x50, 0x0f,
|
|
};
|
|
static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = {
|
|
0x00, 0x10, 0x34, 0x64,
|
|
0x48, 0x07, 0x48, 0x10,
|
|
0x50, 0x64, 0x04, 0x34,
|
|
0x50, 0x0F,
|
|
};
|
|
|
|
static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = {
|
|
[0] = {
|
|
.mode = MSM_SPM_L2_MODE_RETENTION,
|
|
.notify_rpm = false,
|
|
.cmd = l2_spm_wfi_cmd_sequence,
|
|
},
|
|
[1] = {
|
|
.mode = MSM_SPM_L2_MODE_GDHS,
|
|
.notify_rpm = true,
|
|
.cmd = l2_spm_gdhs_cmd_sequence,
|
|
},
|
|
[2] = {
|
|
.mode = MSM_SPM_L2_MODE_POWER_COLLAPSE,
|
|
.notify_rpm = true,
|
|
.cmd = l2_spm_power_off_cmd_sequence,
|
|
},
|
|
};
|
|
|
|
|
|
static struct msm_spm_platform_data msm_spm_l2_data[] __initdata = {
|
|
[0] = {
|
|
.reg_base_addr = MSM_SAW_L2_BASE,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x00A000AE,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A00020,
|
|
.modes = msm_spm_l2_seq_list,
|
|
.num_modes = ARRAY_SIZE(msm_spm_l2_seq_list),
|
|
},
|
|
};
|
|
|
|
static struct msm_spm_platform_data msm_spm_data[] __initdata = {
|
|
[0] = {
|
|
.reg_base_addr = MSM_SAW0_BASE,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
|
|
#if defined(CONFIG_MSM_AVS_HW)
|
|
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
|
|
#endif
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
|
|
.vctl_timeout_us = 50,
|
|
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
|
|
.modes = msm_spm_seq_list,
|
|
},
|
|
[1] = {
|
|
.reg_base_addr = MSM_SAW1_BASE,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
|
|
#if defined(CONFIG_MSM_AVS_HW)
|
|
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
|
|
#endif
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
|
|
.vctl_timeout_us = 50,
|
|
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
|
|
.modes = msm_spm_seq_list,
|
|
},
|
|
[2] = {
|
|
.reg_base_addr = MSM_SAW2_BASE,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
|
|
#if defined(CONFIG_MSM_AVS_HW)
|
|
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
|
|
#endif
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
|
|
.vctl_timeout_us = 50,
|
|
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
|
|
.modes = msm_spm_seq_list,
|
|
},
|
|
[3] = {
|
|
.reg_base_addr = MSM_SAW3_BASE,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
|
|
#if defined(CONFIG_MSM_AVS_HW)
|
|
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
|
|
#endif
|
|
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
|
|
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
|
|
.vctl_timeout_us = 50,
|
|
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
|
|
.modes = msm_spm_seq_list,
|
|
},
|
|
};
|
|
|
|
static void __init apq8064_init_buses(void)
|
|
{
|
|
msm_bus_rpm_set_mt_mask();
|
|
msm_bus_8064_apps_fabric_pdata.rpm_enabled = 1;
|
|
msm_bus_8064_sys_fabric_pdata.rpm_enabled = 1;
|
|
msm_bus_8064_mm_fabric_pdata.rpm_enabled = 1;
|
|
msm_bus_8064_apps_fabric.dev.platform_data =
|
|
&msm_bus_8064_apps_fabric_pdata;
|
|
msm_bus_8064_sys_fabric.dev.platform_data =
|
|
&msm_bus_8064_sys_fabric_pdata;
|
|
msm_bus_8064_mm_fabric.dev.platform_data =
|
|
&msm_bus_8064_mm_fabric_pdata;
|
|
msm_bus_8064_sys_fpb.dev.platform_data = &msm_bus_8064_sys_fpb_pdata;
|
|
msm_bus_8064_cpss_fpb.dev.platform_data = &msm_bus_8064_cpss_fpb_pdata;
|
|
}
|
|
|
|
static struct platform_device *common_devices[] __initdata = {
|
|
&apq8064_device_dmov,
|
|
&apq8064_device_qup_i2c_gsbi4,
|
|
&apq8064_device_qup_spi_gsbi5,
|
|
&apq8064_slim_ctrl,
|
|
&apq8064_device_ssbi_pmic1,
|
|
&apq8064_device_ssbi_pmic2,
|
|
&msm_device_smd_apq8064,
|
|
&apq8064_device_otg,
|
|
&apq8064_device_gadget_peripheral,
|
|
&android_usb_device,
|
|
#ifdef CONFIG_ANDROID_PMEM
|
|
#ifndef CONFIG_MSM_MULTIMEDIA_USE_ION
|
|
&android_pmem_device,
|
|
&android_pmem_adsp_device,
|
|
#endif
|
|
&android_pmem_audio_device,
|
|
#endif
|
|
#ifdef CONFIG_ION_MSM
|
|
&ion_dev,
|
|
#endif
|
|
&msm8064_device_watchdog,
|
|
&msm8064_device_saw_regulator_core0,
|
|
&msm8064_device_saw_regulator_core1,
|
|
&msm8064_device_saw_regulator_core2,
|
|
&msm8064_device_saw_regulator_core3,
|
|
#if defined(CONFIG_CRYPTO_DEV_QCRYPTO) || \
|
|
defined(CONFIG_CRYPTO_DEV_QCRYPTO_MODULE)
|
|
&qcrypto_device,
|
|
#endif
|
|
|
|
#if defined(CONFIG_CRYPTO_DEV_QCEDEV) || \
|
|
defined(CONFIG_CRYPTO_DEV_QCEDEV_MODULE)
|
|
&qcedev_device,
|
|
#endif
|
|
|
|
#ifdef CONFIG_HW_RANDOM_MSM
|
|
&apq8064_device_rng,
|
|
#endif
|
|
&apq_pcm,
|
|
&apq_pcm_routing,
|
|
&apq_cpudai0,
|
|
&apq_cpudai1,
|
|
&apq_cpudai_hdmi_rx,
|
|
&apq_cpudai_bt_rx,
|
|
&apq_cpudai_bt_tx,
|
|
&apq_cpudai_fm_rx,
|
|
&apq_cpudai_fm_tx,
|
|
&apq_cpu_fe,
|
|
&apq_stub_codec,
|
|
&apq_voice,
|
|
&apq_voip,
|
|
&apq_lpa_pcm,
|
|
&apq_pcm_hostless,
|
|
&apq_cpudai_afe_01_rx,
|
|
&apq_cpudai_afe_01_tx,
|
|
&apq_cpudai_afe_02_rx,
|
|
&apq_cpudai_afe_02_tx,
|
|
&apq_pcm_afe,
|
|
&apq_cpudai_auxpcm_rx,
|
|
&apq_cpudai_auxpcm_tx,
|
|
&apq8064_rpm_device,
|
|
&apq8064_rpm_log_device,
|
|
&apq8064_rpm_stat_device,
|
|
&msm_bus_8064_apps_fabric,
|
|
&msm_bus_8064_sys_fabric,
|
|
&msm_bus_8064_mm_fabric,
|
|
&msm_bus_8064_sys_fpb,
|
|
&msm_bus_8064_cpss_fpb,
|
|
&msm_device_vidc,
|
|
};
|
|
|
|
static struct platform_device *sim_devices[] __initdata = {
|
|
&apq8064_device_uart_gsbi3,
|
|
&msm_device_sps_apq8064,
|
|
};
|
|
|
|
static struct platform_device *rumi3_devices[] __initdata = {
|
|
&apq8064_device_uart_gsbi1,
|
|
&msm_device_sps_apq8064,
|
|
#ifdef CONFIG_MSM_ROTATOR
|
|
&msm_rotator_device,
|
|
#endif
|
|
};
|
|
|
|
static struct platform_device *cdp_devices[] __initdata = {
|
|
&apq8064_device_uart_gsbi1,
|
|
&msm_device_sps_apq8064,
|
|
};
|
|
|
|
static struct msm_spi_platform_data apq8064_qup_spi_gsbi5_pdata = {
|
|
.max_clock_speed = 24000000,
|
|
};
|
|
|
|
#define KS8851_IRQ_GPIO 43
|
|
|
|
static struct spi_board_info spi_board_info[] __initdata = {
|
|
{
|
|
.modalias = "ks8851",
|
|
.irq = MSM_GPIO_TO_INT(KS8851_IRQ_GPIO),
|
|
.max_speed_hz = 19200000,
|
|
.bus_num = 0,
|
|
.chip_select = 2,
|
|
.mode = SPI_MODE_0,
|
|
},
|
|
};
|
|
|
|
static struct slim_boardinfo apq8064_slim_devices[] = {
|
|
{
|
|
.bus_num = 1,
|
|
.slim_slave = &apq8064_slim_tabla,
|
|
},
|
|
{
|
|
.bus_num = 1,
|
|
.slim_slave = &apq8064_slim_tabla20,
|
|
},
|
|
/* add more slimbus slaves as needed */
|
|
};
|
|
|
|
static struct msm_i2c_platform_data apq8064_i2c_qup_gsbi4_pdata = {
|
|
.clk_freq = 100000,
|
|
.src_clk_rate = 24000000,
|
|
};
|
|
|
|
static void __init apq8064_i2c_init(void)
|
|
{
|
|
apq8064_device_qup_i2c_gsbi4.dev.platform_data =
|
|
&apq8064_i2c_qup_gsbi4_pdata;
|
|
}
|
|
|
|
#ifdef CONFIG_KS8851
|
|
static int ethernet_init(void)
|
|
{
|
|
int ret;
|
|
ret = gpio_request(KS8851_IRQ_GPIO, "ks8851_irq");
|
|
if (ret) {
|
|
pr_err("ks8851 gpio_request failed: %d\n", ret);
|
|
goto fail;
|
|
}
|
|
|
|
return 0;
|
|
fail:
|
|
return ret;
|
|
}
|
|
#else
|
|
static int ethernet_init(void)
|
|
{
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static void __init apq8064_clock_init(void)
|
|
{
|
|
if (machine_is_apq8064_sim())
|
|
msm_clock_init(&apq8064_clock_init_data);
|
|
else
|
|
msm_clock_init(&apq8064_dummy_clock_init_data);
|
|
}
|
|
|
|
static void __init apq8064_common_init(void)
|
|
{
|
|
if (socinfo_init() < 0)
|
|
pr_err("socinfo_init() failed!\n");
|
|
BUG_ON(msm_rpm_init(&apq8064_rpm_data));
|
|
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
|
|
apq8064_clock_init();
|
|
apq8064_init_gpiomux();
|
|
apq8064_i2c_init();
|
|
|
|
apq8064_device_qup_spi_gsbi5.dev.platform_data =
|
|
&apq8064_qup_spi_gsbi5_pdata;
|
|
apq8064_init_pmic();
|
|
apq8064_device_otg.dev.platform_data = &msm_otg_pdata;
|
|
apq8064_init_buses();
|
|
platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
|
|
apq8064_init_mmc();
|
|
slim_register_board_info(apq8064_slim_devices,
|
|
ARRAY_SIZE(apq8064_slim_devices));
|
|
acpuclk_init(&acpuclk_8064_soc_data);
|
|
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
|
|
msm_spm_l2_init(msm_spm_l2_data);
|
|
msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
|
|
msm_pm_set_rpm_wakeup_irq(RPM_APCC_CPU0_WAKE_UP_IRQ);
|
|
msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
|
|
msm_pm_data);
|
|
BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata));
|
|
}
|
|
|
|
static void __init apq8064_allocate_memory_regions(void)
|
|
{
|
|
apq8064_allocate_fb_region();
|
|
}
|
|
|
|
static void __init apq8064_sim_init(void)
|
|
{
|
|
struct msm_watchdog_pdata *wdog_pdata = (struct msm_watchdog_pdata *)
|
|
&msm8064_device_watchdog.dev.platform_data;
|
|
|
|
wdog_pdata->bark_time = 15000;
|
|
apq8064_common_init();
|
|
platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
|
|
}
|
|
|
|
static void __init apq8064_rumi3_init(void)
|
|
{
|
|
apq8064_common_init();
|
|
ethernet_init();
|
|
platform_add_devices(rumi3_devices, ARRAY_SIZE(rumi3_devices));
|
|
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
|
|
apq8064_init_fb();
|
|
}
|
|
|
|
static void __init apq8064_cdp_init(void)
|
|
{
|
|
apq8064_common_init();
|
|
ethernet_init();
|
|
platform_add_devices(cdp_devices, ARRAY_SIZE(cdp_devices));
|
|
spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
|
|
}
|
|
|
|
MACHINE_START(APQ8064_SIM, "QCT APQ8064 SIMULATOR")
|
|
.map_io = apq8064_map_io,
|
|
.reserve = apq8064_reserve,
|
|
.init_irq = apq8064_init_irq,
|
|
.handle_irq = gic_handle_irq,
|
|
.timer = &msm_timer,
|
|
.init_machine = apq8064_sim_init,
|
|
MACHINE_END
|
|
|
|
MACHINE_START(APQ8064_RUMI3, "QCT APQ8064 RUMI3")
|
|
.map_io = apq8064_map_io,
|
|
.reserve = apq8064_reserve,
|
|
.init_irq = apq8064_init_irq,
|
|
.handle_irq = gic_handle_irq,
|
|
.timer = &msm_timer,
|
|
.init_machine = apq8064_rumi3_init,
|
|
.init_early = apq8064_allocate_memory_regions,
|
|
MACHINE_END
|
|
|
|
MACHINE_START(APQ8064_CDP, "QCT APQ8064 CDP")
|
|
.map_io = apq8064_map_io,
|
|
.reserve = apq8064_reserve,
|
|
.init_irq = apq8064_init_irq,
|
|
.handle_irq = gic_handle_irq,
|
|
.timer = &msm_timer,
|
|
.init_machine = apq8064_cdp_init,
|
|
MACHINE_END
|
|
|
|
MACHINE_START(APQ8064_MTP, "QCT APQ8064 MTP")
|
|
.map_io = apq8064_map_io,
|
|
.reserve = apq8064_reserve,
|
|
.init_irq = apq8064_init_irq,
|
|
.handle_irq = gic_handle_irq,
|
|
.timer = &msm_timer,
|
|
.init_machine = apq8064_cdp_init,
|
|
MACHINE_END
|
|
|
|
MACHINE_START(APQ8064_LIQUID, "QCT APQ8064 LIQUID")
|
|
.map_io = apq8064_map_io,
|
|
.reserve = apq8064_reserve,
|
|
.init_irq = apq8064_init_irq,
|
|
.handle_irq = gic_handle_irq,
|
|
.timer = &msm_timer,
|
|
.init_machine = apq8064_cdp_init,
|
|
MACHINE_END
|
|
|