0ff37e7a2f
The change supports save/restore of processor state during warmboot when the number of cores is greater than 2. The current version supports two cores only. Change-Id: Icd23f10cde00a5dbe0abc1a76f1555f8834053a3 Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>
289 lines
7.6 KiB
ArmAsm
289 lines
7.6 KiB
ArmAsm
/*
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* Idle processing for ARMv7-based Qualcomm SoCs.
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2007-2009, 2011-2012 Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/threads.h>
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#include <asm/assembler.h>
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#ifdef CONFIG_MSM_CPU_AVS
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/* 11 general purpose registers (r4-r14), 10 cp15 registers, 3 AVS registers */
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#define CPU_SAVED_STATE_SIZE (4 * 11 + 4 * 10 + 4 * 3)
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#else
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/* 11 general purpose registers (r4-r14), 10 cp15 registers */
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#define CPU_SAVED_STATE_SIZE (4 * 11 + 4 * 10)
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#endif
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#ifdef CONFIG_ARCH_MSM_KRAIT
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#define SCM_SVC_BOOT 0x1
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#define SCM_CMD_TERMINATE_PC 0x2
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#endif
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ENTRY(msm_arch_idle)
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wfi
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#ifdef CONFIG_ARCH_MSM8X60
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mrc p14, 1, r1, c1, c5, 4 /* read ETM PDSR to clear sticky bit */
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mrc p14, 0, r1, c1, c5, 4 /* read DBG PRSR to clear sticky bit */
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isb
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#endif
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bx lr
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ENTRY(msm_pm_collapse)
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#if defined(CONFIG_MSM_FIQ_SUPPORT)
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cpsid f
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#endif
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ldr r0, =saved_state
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#if (NR_CPUS >= 2)
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mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
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ands r1, r1, #15 /* What CPU am I */
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mov r2, #CPU_SAVED_STATE_SIZE
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mul r1, r1, r2
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add r0, r0, r1
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#endif
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stmia r0!, {r4-r14}
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mrc p15, 0, r1, c1, c0, 0 /* MMU control */
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mrc p15, 0, r2, c2, c0, 0 /* TTBR0 */
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mrc p15, 0, r3, c3, c0, 0 /* dacr */
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#ifdef CONFIG_ARCH_MSM_SCORPION
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/* This instruction is not valid for non scorpion processors */
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mrc p15, 3, r4, c15, c0, 3 /* L2CR1 is the L2 cache control reg 1 */
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#endif
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mrc p15, 0, r5, c10, c2, 0 /* PRRR */
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mrc p15, 0, r6, c10, c2, 1 /* NMRR */
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mrc p15, 0, r7, c1, c0, 1 /* ACTLR */
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mrc p15, 0, r8, c2, c0, 1 /* TTBR1 */
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mrc p15, 0, r9, c13, c0, 3 /* TPIDRURO */
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mrc p15, 0, ip, c13, c0, 1 /* context ID */
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stmia r0!, {r1-r9, ip}
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#ifdef CONFIG_MSM_CPU_AVS
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mrc p15, 7, r1, c15, c1, 7 /* AVSCSR is the Adaptive Voltage Scaling
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* Control and Status Register */
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mrc p15, 7, r2, c15, c0, 6 /* AVSDSCR is the Adaptive Voltage
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* Scaling Delay Synthesizer Control
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* Register */
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#ifndef CONFIG_ARCH_MSM_KRAIT
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mrc p15, 7, r3, c15, c1, 0 /* TSCSR is the Temperature Status and
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* Control Register
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*/
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#endif
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stmia r0!, {r1-r3}
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#endif
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#ifdef CONFIG_MSM_JTAG
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bl msm_jtag_save_state
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#endif
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ldr r0, =msm_pm_flush_l2_flag
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ldr r0, [r0]
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mov r1, #0
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mcr p15, 2, r1, c0, c0, 0 /*CCSELR*/
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isb
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mrc p15, 1, r1, c0, c0, 0 /*CCSIDR*/
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mov r2, #1
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and r1, r2, r1, ASR #30 /* Check if the cache is write back */
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orr r1, r0, r1
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cmp r1, #1
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bne skip
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bl v7_flush_dcache_all
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skip: ldr r0, =saved_state
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ldr r1, =saved_state_end
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sub r1, r1, r0
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bl v7_flush_kern_dcache_area
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mrc p15, 0, r4, c1, c0, 0 /* read current CR */
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bic r0, r4, #(1 << 2) /* clear dcache bit */
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bic r0, r0, #(1 << 12) /* clear icache bit */
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mcr p15, 0, r0, c1, c0, 0 /* disable d/i cache */
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dsb
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#ifdef CONFIG_ARCH_MSM_KRAIT
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ldr r0, =SCM_SVC_BOOT
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ldr r1, =SCM_CMD_TERMINATE_PC
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ldr r2, =msm_pm_flush_l2_flag
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ldr r2, [r2]
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bl scm_call_atomic1
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#else
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wfi
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#endif
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mcr p15, 0, r4, c1, c0, 0 /* restore d/i cache */
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isb
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#if defined(CONFIG_MSM_FIQ_SUPPORT)
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cpsie f
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#endif
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#ifdef CONFIG_MSM_JTAG
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bl msm_jtag_restore_state
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#endif
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ldr r0, =saved_state /* restore registers */
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#if (NR_CPUS >= 2)
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mrc p15, 0, r1, c0, c0, 5 /* MPIDR */
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ands r1, r1, #15 /* What CPU am I */
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addne r0, r0, #CPU_SAVED_STATE_SIZE
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#endif
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ldmfd r0, {r4-r14}
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mov r0, #0 /* return power collapse failed */
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bx lr
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ENTRY(msm_pm_collapse_exit)
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#if 0 /* serial debug */
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mov r0, #0x80000016
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mcr p15, 0, r0, c15, c2, 4
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mov r0, #0xA9000000
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add r0, r0, #0x00A00000 /* UART1 */
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/*add r0, r0, #0x00C00000*/ /* UART3 */
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mov r1, #'A'
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str r1, [r0, #0x00C]
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#endif
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ldr r1, =saved_state
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ldr r2, =msm_pm_collapse_exit
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adr r3, msm_pm_collapse_exit
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add r1, r1, r3
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sub r1, r1, r2
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add r1, r1, #CPU_SAVED_STATE_SIZE
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#if (NR_CPUS >= 2)
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mrc p15, 0, r2, c0, c0, 5 /* MPIDR */
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ands r2, r2, #15 /* What CPU am I */
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mov r3, #CPU_SAVED_STATE_SIZE
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mul r2, r2, r3
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add r1, r1, r2
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#endif
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#ifdef CONFIG_MSM_CPU_AVS
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ldmdb r1!, {r2-r4}
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#ifndef CONFIG_ARCH_MSM_KRAIT
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mcr p15, 7, r4, c15, c1, 0 /* TSCSR */
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#endif
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mcr p15, 7, r3, c15, c0, 6 /* AVSDSCR */
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mcr p15, 7, r2, c15, c1, 7 /* AVSCSR */
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#endif
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ldmdb r1!, {r2-r11}
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mcr p15, 0, r4, c3, c0, 0 /* dacr */
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mcr p15, 0, r3, c2, c0, 0 /* TTBR0 */
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#ifdef CONFIG_ARCH_MSM_SCORPION
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/* This instruction is not valid for non scorpion processors */
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mcr p15, 3, r5, c15, c0, 3 /* L2CR1 */
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#endif
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mcr p15, 0, r6, c10, c2, 0 /* PRRR */
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mcr p15, 0, r7, c10, c2, 1 /* NMRR */
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mcr p15, 0, r8, c1, c0, 1 /* ACTLR */
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mcr p15, 0, r9, c2, c0, 1 /* TTBR1 */
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mcr p15, 0, r10, c13, c0, 3 /* TPIDRURO */
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mcr p15, 0, r11, c13, c0, 1 /* context ID */
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isb
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ldmdb r1!, {r4-r14}
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ldr r0, =msm_pm_pc_pgd
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ldr r1, =msm_pm_collapse_exit
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adr r3, msm_pm_collapse_exit
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add r0, r0, r3
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sub r0, r0, r1
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ldr r0, [r0]
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mrc p15, 0, r1, c2, c0, 0 /* save current TTBR0 */
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and r3, r1, #0x7f /* mask to get TTB flags */
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orr r0, r0, r3 /* add TTB flags to switch TTBR value */
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mcr p15, 0, r0, c2, c0, 0 /* temporary switch TTBR0 */
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isb
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mcr p15, 0, r2, c1, c0, 0 /* MMU control */
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isb
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msm_pm_mapped_pa:
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/* Switch to virtual */
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ldr r0, =msm_pm_pa_to_va
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mov pc, r0
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msm_pm_pa_to_va:
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mcr p15, 0, r1, c2, c0, 0 /* restore TTBR0 */
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isb
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mcr p15, 0, r3, c8, c7, 0 /* UTLBIALL */
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mcr p15, 0, r3, c7, c5, 6 /* BPIALL */
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dsb
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isb
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#ifdef CONFIG_ARCH_MSM_KRAIT
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mrc p15, 0, r1, c0, c0, 0
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ldr r3, =0xff00fc00
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and r3, r1, r3
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ldr r1, =0x51000400
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cmp r3, r1
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mrceq p15, 7, r3, c15, c0, 2
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biceq r3, r3, #0x400
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mcreq p15, 7, r3, c15, c0, 2
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#endif
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stmfd sp!, {lr}
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bl v7_flush_kern_cache_all
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#ifdef CONFIG_MSM_JTAG
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bl msm_jtag_restore_state
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#endif
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ldmfd sp!, {lr}
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mov r0, #1
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bx lr
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nop
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nop
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nop
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nop
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nop
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1: b 1b
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ENTRY(msm_pm_boot_entry)
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mrc p15, 0, r0, c0, c0, 5 /* MPIDR */
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and r0, r0, #15 /* what CPU am I */
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ldr r1, =msm_pm_boot_vector
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ldr r2, =msm_pm_boot_entry
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adr r3, msm_pm_boot_entry
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add r1, r1, r3 /* translate virt to phys addr */
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sub r1, r1, r2
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add r1, r1, r0, LSL #2 /* locate boot vector for our cpu */
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ldr pc, [r1] /* jump */
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ENTRY(msm_pm_write_boot_vector)
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ldr r2, =msm_pm_boot_vector
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add r2, r2, r0, LSL #2 /* locate boot vector for our cpu */
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str r1, [r2]
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mov r0, r2
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ldr r1, =4
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stmfd sp!, {lr}
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bl v7_flush_kern_dcache_area
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ldmfd sp!, {lr}
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bx lr
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ENTRY(msm_pm_set_l2_flush_flag)
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ldr r1, =msm_pm_flush_l2_flag
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str r0, [r1]
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bx lr
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.data
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.globl msm_pm_pc_pgd
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msm_pm_pc_pgd:
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.long 0x0
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saved_state:
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.space CPU_SAVED_STATE_SIZE * NR_CPUS
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saved_state_end:
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msm_pm_boot_vector:
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.space 4 * NR_CPUS
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/*
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* Default the l2 flush flag to 1 so that caches are flushed during power
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* collapse unless the L2 driver decides to flush them only during L2
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* Power collapse.
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*/
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msm_pm_flush_l2_flag:
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.long 0x1
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