3f2bc4d6eb
msm-2.6.38: tag AU_LINUX_ANDROID_GINGERBREAD.02.03.04.00.142 Signed-off-by: Bryan Huntsman <bryanh@codeaurora.org>
400 lines
10 KiB
C
400 lines
10 KiB
C
/*
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* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/system.h>
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#ifdef CONFIG_CPU_V7
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#define KRAIT_EVT_PREFIX 1
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#define KRAIT_MAX_L1_REG 2
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/*
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event encoding: prccg
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p = prefix (1 for Krait L1)
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r = register
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cc = code
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g = group
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*/
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#define KRAIT_L1_ICACHE_MISS 0x10010
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#define KRAIT_L1_ICACHE_ACCESS 0x10011
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#define KRAIT_DTLB_ACCESS 0x121B2
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#define KRAIT_ITLB_ACCESS 0x121C0
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u32 evt_type_base[] = {0x4c, 0x50, 0x54};
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static const unsigned armv7_krait_perf_map[PERF_COUNT_HW_MAX] = {
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[PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
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[PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
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[PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
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[PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
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[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
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[PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
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[PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
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};
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static const unsigned armv7_krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
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[PERF_COUNT_HW_CACHE_OP_MAX]
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[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
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[C(L1D)] = {
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/*
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* The performance counters don't differentiate between read
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* and write accesses/misses so this isn't strictly correct,
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* but it's the best we can do. Writes and reads get
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* combined.
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*/
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
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[C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(L1I)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = KRAIT_L1_ICACHE_ACCESS,
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[C(RESULT_MISS)] = KRAIT_L1_ICACHE_MISS,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = KRAIT_L1_ICACHE_ACCESS,
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[C(RESULT_MISS)] = KRAIT_L1_ICACHE_MISS,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(LL)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(DTLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = KRAIT_DTLB_ACCESS,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = KRAIT_DTLB_ACCESS,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(ITLB)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)] = KRAIT_ITLB_ACCESS,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)] = KRAIT_ITLB_ACCESS,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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[C(BPU)] = {
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[C(OP_READ)] = {
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[C(RESULT_ACCESS)]
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= ARMV7_PERFCTR_PC_BRANCH_MIS_USED,
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[C(RESULT_MISS)]
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= ARMV7_PERFCTR_PC_BRANCH_MIS_USED,
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},
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[C(OP_WRITE)] = {
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[C(RESULT_ACCESS)]
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= ARMV7_PERFCTR_PC_BRANCH_MIS_USED,
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[C(RESULT_MISS)]
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= ARMV7_PERFCTR_PC_BRANCH_MIS_USED,
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},
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[C(OP_PREFETCH)] = {
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[C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
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[C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
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},
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},
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};
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struct krait_evt {
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/*
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* The group_setval field corresponds to the value that the group
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* register needs to be set to. This value is calculated from the row
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* and column that the event belongs to in the event table
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*/
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u32 group_setval;
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/*
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* The groupcode corresponds to the group that the event belongs to.
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* Krait has 3 groups of events PMRESR0, 1, 2
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* going from 0 to 2 in terms of the codes used
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*/
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u8 groupcode;
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/*
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* The armv7_evt_type field corresponds to the armv7 defined event
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* code that the Krait events map to
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*/
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u32 armv7_evt_type;
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};
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static unsigned int get_krait_evtinfo(unsigned int krait_evt_type,
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struct krait_evt *evtinfo)
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{
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u8 prefix;
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u8 reg;
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u8 code;
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u8 group;
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prefix = (krait_evt_type & 0xF0000) >> 16;
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reg = (krait_evt_type & 0x0F000) >> 12;
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code = (krait_evt_type & 0x00FF0) >> 4;
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group = krait_evt_type & 0x0000F;
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if ((prefix != KRAIT_EVT_PREFIX) || (group > 3) ||
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(reg > KRAIT_MAX_L1_REG))
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return -EINVAL;
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evtinfo->group_setval = 0x80000000 | (code << (group * 8));
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evtinfo->groupcode = reg;
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evtinfo->armv7_evt_type = evt_type_base[reg] | group;
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return evtinfo->armv7_evt_type;
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}
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static u32 krait_read_pmresr0(void)
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{
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u32 val;
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asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val));
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return val;
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}
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static void krait_write_pmresr0(u32 val)
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{
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asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val));
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}
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static u32 krait_read_pmresr1(void)
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{
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u32 val;
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asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val));
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return val;
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}
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static void krait_write_pmresr1(u32 val)
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{
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asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val));
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}
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static u32 krait_read_pmresr2(void)
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{
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u32 val;
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asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val));
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return val;
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}
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static void krait_write_pmresr2(u32 val)
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{
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asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val));
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}
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struct krait_access_funcs {
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u32 (*read) (void);
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void (*write) (u32);
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};
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/*
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* The krait_functions array is used to set up the event register codes
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* based on the group to which an event belongs.
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* Having the following array modularizes the code for doing that.
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*/
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struct krait_access_funcs krait_functions[] = {
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{krait_read_pmresr0, krait_write_pmresr0},
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{krait_read_pmresr1, krait_write_pmresr1},
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{krait_read_pmresr2, krait_write_pmresr2},
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};
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static inline u32 krait_get_columnmask(u32 evt_code)
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{
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const u32 columnmasks[] = {0xffffff00, 0xffff00ff, 0xff00ffff,
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0x80ffffff};
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return columnmasks[evt_code & 0x3];
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}
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static void krait_evt_setup(u32 gr, u32 setval, u32 evt_code)
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{
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u32 val;
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val = krait_get_columnmask(evt_code) & krait_functions[gr].read();
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val = val | setval;
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krait_functions[gr].write(val);
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}
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static void krait_clear_pmuregs(void)
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{
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krait_write_pmresr0(0);
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krait_write_pmresr1(0);
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krait_write_pmresr2(0);
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}
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static void krait_clearpmu(u32 grp, u32 val, u32 evt_code)
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{
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u32 new_pmuval;
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new_pmuval = krait_functions[grp].read() &
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krait_get_columnmask(evt_code);
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krait_functions[grp].write(new_pmuval);
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}
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static void krait_pmu_disable_event(struct hw_perf_event *hwc, int idx)
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{
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unsigned long flags;
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u32 val = 0;
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u32 gr;
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unsigned long event;
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struct krait_evt evtinfo;
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/* Disable counter and interrupt */
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raw_spin_lock_irqsave(&pmu_lock, flags);
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/* Disable counter */
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armv7_pmnc_disable_counter(idx);
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/*
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* Clear pmresr code (if destined for PMNx counters)
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* We don't need to set the event if it's a cycle count
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*/
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if (idx != ARMV7_CYCLE_COUNTER) {
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val = hwc->config_base;
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if (val > 0x40) {
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event = get_krait_evtinfo(val, &evtinfo);
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if (event == -EINVAL)
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goto krait_dis_out;
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val = evtinfo.group_setval;
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gr = evtinfo.groupcode;
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krait_clearpmu(gr, val, evtinfo.armv7_evt_type);
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}
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}
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/* Disable interrupt for this counter */
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armv7_pmnc_disable_intens(idx);
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krait_dis_out:
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raw_spin_unlock_irqrestore(&pmu_lock, flags);
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}
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static void krait_pmu_enable_event(struct hw_perf_event *hwc, int idx)
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{
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unsigned long flags;
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u32 val = 0;
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u32 gr;
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unsigned long event;
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struct krait_evt evtinfo;
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/*
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* Enable counter and interrupt, and set the counter to count
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* the event that we're interested in.
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*/
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raw_spin_lock_irqsave(&pmu_lock, flags);
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/* Disable counter */
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armv7_pmnc_disable_counter(idx);
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/*
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* Set event (if destined for PMNx counters)
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* We don't need to set the event if it's a cycle count
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*/
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if (idx != ARMV7_CYCLE_COUNTER) {
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val = hwc->config_base;
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if (val < 0x40) {
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armv7_pmnc_write_evtsel(idx, hwc->config_base);
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} else {
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event = get_krait_evtinfo(val, &evtinfo);
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if (event == -EINVAL)
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goto krait_out;
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/*
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* Set event (if destined for PMNx counters)
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* We don't need to set the event if it's a cycle count
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*/
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armv7_pmnc_write_evtsel(idx, event);
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val = 0x0;
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asm volatile("mcr p15, 0, %0, c9, c15, 0" : :
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"r" (val));
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val = evtinfo.group_setval;
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gr = evtinfo.groupcode;
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krait_evt_setup(gr, val, evtinfo.armv7_evt_type);
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}
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}
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/* Enable interrupt for this counter */
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armv7_pmnc_enable_intens(idx);
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/* Enable counter */
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armv7_pmnc_enable_counter(idx);
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krait_out:
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raw_spin_unlock_irqrestore(&pmu_lock, flags);
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}
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static struct arm_pmu krait_pmu = {
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.handle_irq = armv7pmu_handle_irq,
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#ifdef CONFIG_ARCH_MSM_SMP
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.secondary_enable = scorpion_secondary_enable,
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.secondary_disable = scorpion_secondary_disable,
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#endif
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.enable = krait_pmu_enable_event,
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.disable = krait_pmu_disable_event,
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.read_counter = armv7pmu_read_counter,
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.write_counter = armv7pmu_write_counter,
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.raw_event_mask = 0xFFFFF,
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.get_event_idx = armv7pmu_get_event_idx,
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.start = armv7pmu_start,
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.stop = armv7pmu_stop,
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.max_period = (1LLU << 32) - 1,
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};
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static const struct arm_pmu *__init armv7_krait_pmu_init(void)
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{
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krait_pmu.id = ARM_PERF_PMU_ID_KRAIT;
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krait_pmu.name = "ARMv7 Krait";
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krait_pmu.cache_map = &armv7_krait_perf_cache_map;
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krait_pmu.event_map = &armv7_krait_perf_map;
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krait_pmu.num_events = armv7_read_num_pmnc_events();
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krait_clear_pmuregs();
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return &krait_pmu;
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}
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#else
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static const struct arm_pmu *__init armv7_krait_pmu_init(void)
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{
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return NULL;
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}
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#endif /* CONFIG_CPU_V7 */
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