Files
kernel-tenderloin-3.0/drivers/tty
Mayank Rana 70a8e7d29d msm_serial_hs_lite: Set UART Clock rate to zero, only when it is disable
UART Core clock set rate is getting called before actually disabling uart
core clock. This problem has been seen with console suspend due to setting
clock rate to zero from msm_hsl_power api. This change makes sure that uart
core clock is actually disabled before it is set to zero.

Signed-off-by: Mayank Rana <mrana@codeaurora.org>
2011-10-03 16:17:14 -07:00
..
2011-10-03 09:57:10 -07:00
2011-03-31 11:26:23 -03:00
2011-08-04 21:58:40 -07:00
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2011-03-31 11:26:23 -03:00
2011-03-31 11:26:23 -03:00