055cb8ecdd
New targets are following V4L2 architecture for camera. Update 7x27a camera drivers to support new V4L2 architecture to unify all camera drivers in the same architecture. Signed-off-by: Suresh Vankadara <svankada@codeaurora.org> Change-Id: Ie23ac982375041c06b68537d5784d8cdbbc9bf04
292 lines
13 KiB
C
292 lines
13 KiB
C
#ifndef __MSM_ISP_H__
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#define __MSM_ISP_H__
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/* ISP message IDs */
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#define MSG_ID_RESET_ACK 0
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#define MSG_ID_START_ACK 1
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#define MSG_ID_STOP_ACK 2
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#define MSG_ID_UPDATE_ACK 3
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#define MSG_ID_OUTPUT_P 4
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#define MSG_ID_OUTPUT_T 5
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#define MSG_ID_OUTPUT_S 6
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#define MSG_ID_OUTPUT_V 7
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#define MSG_ID_SNAPSHOT_DONE 8
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#define MSG_ID_STATS_AEC 9
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#define MSG_ID_STATS_AF 10
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#define MSG_ID_STATS_AWB 11
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#define MSG_ID_STATS_RS 12
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#define MSG_ID_STATS_CS 13
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#define MSG_ID_STATS_IHIST 14
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#define MSG_ID_STATS_SKIN 15
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#define MSG_ID_EPOCH1 16
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#define MSG_ID_EPOCH2 17
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#define MSG_ID_SYNC_TIMER0_DONE 18
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#define MSG_ID_SYNC_TIMER1_DONE 19
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#define MSG_ID_SYNC_TIMER2_DONE 20
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#define MSG_ID_ASYNC_TIMER0_DONE 21
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#define MSG_ID_ASYNC_TIMER1_DONE 22
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#define MSG_ID_ASYNC_TIMER2_DONE 23
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#define MSG_ID_ASYNC_TIMER3_DONE 24
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#define MSG_ID_AE_OVERFLOW 25
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#define MSG_ID_AF_OVERFLOW 26
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#define MSG_ID_AWB_OVERFLOW 27
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#define MSG_ID_RS_OVERFLOW 28
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#define MSG_ID_CS_OVERFLOW 29
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#define MSG_ID_IHIST_OVERFLOW 30
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#define MSG_ID_SKIN_OVERFLOW 31
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#define MSG_ID_AXI_ERROR 32
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#define MSG_ID_CAMIF_OVERFLOW 33
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#define MSG_ID_VIOLATION 34
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#define MSG_ID_CAMIF_ERROR 35
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#define MSG_ID_BUS_OVERFLOW 36
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#define MSG_ID_SOF_ACK 37
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#define MSG_ID_STOP_REC_ACK 38
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#define MSG_ID_STATS_AWB_AEC 39
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/* ISP command IDs */
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#define VFE_CMD_DUMMY_0 0
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#define VFE_CMD_SET_CLK 1
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#define VFE_CMD_RESET 2
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#define VFE_CMD_START 3
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#define VFE_CMD_TEST_GEN_START 4
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#define VFE_CMD_OPERATION_CFG 5
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#define VFE_CMD_AXI_OUT_CFG 6
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#define VFE_CMD_CAMIF_CFG 7
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#define VFE_CMD_AXI_INPUT_CFG 8
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#define VFE_CMD_BLACK_LEVEL_CFG 9
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#define VFE_CMD_MESH_ROLL_OFF_CFG 10
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#define VFE_CMD_DEMUX_CFG 11
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#define VFE_CMD_FOV_CFG 12
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#define VFE_CMD_MAIN_SCALER_CFG 13
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#define VFE_CMD_WB_CFG 14
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#define VFE_CMD_COLOR_COR_CFG 15
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#define VFE_CMD_RGB_G_CFG 16
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#define VFE_CMD_LA_CFG 17
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#define VFE_CMD_CHROMA_EN_CFG 18
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#define VFE_CMD_CHROMA_SUP_CFG 19
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#define VFE_CMD_MCE_CFG 20
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#define VFE_CMD_SK_ENHAN_CFG 21
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#define VFE_CMD_ASF_CFG 22
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#define VFE_CMD_S2Y_CFG 23
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#define VFE_CMD_S2CbCr_CFG 24
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#define VFE_CMD_CHROMA_SUBS_CFG 25
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#define VFE_CMD_OUT_CLAMP_CFG 26
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#define VFE_CMD_FRAME_SKIP_CFG 27
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#define VFE_CMD_DUMMY_1 28
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#define VFE_CMD_DUMMY_2 29
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#define VFE_CMD_DUMMY_3 30
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#define VFE_CMD_UPDATE 31
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#define VFE_CMD_BL_LVL_UPDATE 32
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#define VFE_CMD_DEMUX_UPDATE 33
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#define VFE_CMD_FOV_UPDATE 34
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#define VFE_CMD_MAIN_SCALER_UPDATE 35
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#define VFE_CMD_WB_UPDATE 36
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#define VFE_CMD_COLOR_COR_UPDATE 37
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#define VFE_CMD_RGB_G_UPDATE 38
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#define VFE_CMD_LA_UPDATE 39
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#define VFE_CMD_CHROMA_EN_UPDATE 40
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#define VFE_CMD_CHROMA_SUP_UPDATE 41
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#define VFE_CMD_MCE_UPDATE 42
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#define VFE_CMD_SK_ENHAN_UPDATE 43
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#define VFE_CMD_S2CbCr_UPDATE 44
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#define VFE_CMD_S2Y_UPDATE 45
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#define VFE_CMD_ASF_UPDATE 46
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#define VFE_CMD_FRAME_SKIP_UPDATE 47
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#define VFE_CMD_CAMIF_FRAME_UPDATE 48
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#define VFE_CMD_STATS_AF_UPDATE 49
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#define VFE_CMD_STATS_AE_UPDATE 50
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#define VFE_CMD_STATS_AWB_UPDATE 51
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#define VFE_CMD_STATS_RS_UPDATE 52
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#define VFE_CMD_STATS_CS_UPDATE 53
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#define VFE_CMD_STATS_SKIN_UPDATE 54
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#define VFE_CMD_STATS_IHIST_UPDATE 55
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#define VFE_CMD_DUMMY_4 56
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#define VFE_CMD_EPOCH1_ACK 57
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#define VFE_CMD_EPOCH2_ACK 58
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#define VFE_CMD_START_RECORDING 59
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#define VFE_CMD_STOP_RECORDING 60
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#define VFE_CMD_DUMMY_5 61
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#define VFE_CMD_DUMMY_6 62
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#define VFE_CMD_CAPTURE 63
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#define VFE_CMD_DUMMY_7 64
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#define VFE_CMD_STOP 65
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#define VFE_CMD_GET_HW_VERSION 66
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#define VFE_CMD_GET_FRAME_SKIP_COUNTS 67
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#define VFE_CMD_OUTPUT1_BUFFER_ENQ 68
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#define VFE_CMD_OUTPUT2_BUFFER_ENQ 69
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#define VFE_CMD_OUTPUT3_BUFFER_ENQ 70
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#define VFE_CMD_JPEG_OUT_BUF_ENQ 71
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#define VFE_CMD_RAW_OUT_BUF_ENQ 72
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#define VFE_CMD_RAW_IN_BUF_ENQ 73
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#define VFE_CMD_STATS_AF_ENQ 74
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#define VFE_CMD_STATS_AE_ENQ 75
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#define VFE_CMD_STATS_AWB_ENQ 76
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#define VFE_CMD_STATS_RS_ENQ 77
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#define VFE_CMD_STATS_CS_ENQ 78
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#define VFE_CMD_STATS_SKIN_ENQ 79
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#define VFE_CMD_STATS_IHIST_ENQ 80
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#define VFE_CMD_DUMMY_8 81
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#define VFE_CMD_JPEG_ENC_CFG 82
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#define VFE_CMD_DUMMY_9 83
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#define VFE_CMD_STATS_AF_START 84
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#define VFE_CMD_STATS_AF_STOP 85
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#define VFE_CMD_STATS_AE_START 86
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#define VFE_CMD_STATS_AE_STOP 87
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#define VFE_CMD_STATS_AWB_START 88
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#define VFE_CMD_STATS_AWB_STOP 89
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#define VFE_CMD_STATS_RS_START 90
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#define VFE_CMD_STATS_RS_STOP 91
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#define VFE_CMD_STATS_CS_START 92
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#define VFE_CMD_STATS_CS_STOP 93
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#define VFE_CMD_STATS_SKIN_START 94
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#define VFE_CMD_STATS_SKIN_STOP 95
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#define VFE_CMD_STATS_IHIST_START 96
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#define VFE_CMD_STATS_IHIST_STOP 97
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#define VFE_CMD_DUMMY_10 98
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#define VFE_CMD_SYNC_TIMER_SETTING 99
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#define VFE_CMD_ASYNC_TIMER_SETTING 100
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#define VFE_CMD_LIVESHOT 101
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#define VFE_CMD_LA_SETUP 102
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#define VFE_CMD_LINEARIZATION_CFG 103
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#define VFE_CMD_DEMOSAICV3 104
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#define VFE_CMD_DEMOSAICV3_ABCC_CFG 105
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#define VFE_CMD_DEMOSAICV3_DBCC_CFG 106
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#define VFE_CMD_DEMOSAICV3_DBPC_CFG 107
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#define VFE_CMD_DEMOSAICV3_ABF_CFG 108
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#define VFE_CMD_DEMOSAICV3_ABCC_UPDATE 109
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#define VFE_CMD_DEMOSAICV3_DBCC_UPDATE 110
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#define VFE_CMD_DEMOSAICV3_DBPC_UPDATE 111
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#define VFE_CMD_XBAR_CFG 112
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#define VFE_CMD_MODULE_CFG 113
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#define VFE_CMD_ZSL 114
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#define VFE_CMD_LINEARIZATION_UPDATE 115
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#define VFE_CMD_DEMOSAICV3_ABF_UPDATE 116
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#define VFE_CMD_CLF_CFG 117
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#define VFE_CMD_CLF_LUMA_UPDATE 118
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#define VFE_CMD_CLF_CHROMA_UPDATE 119
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#define VFE_CMD_PCA_ROLL_OFF_CFG 120
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#define VFE_CMD_PCA_ROLL_OFF_UPDATE 121
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#define VFE_CMD_GET_REG_DUMP 122
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#define VFE_CMD_GET_LINEARIZATON_TABLE 123
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#define VFE_CMD_GET_MESH_ROLLOFF_TABLE 124
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#define VFE_CMD_GET_PCA_ROLLOFF_TABLE 125
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#define VFE_CMD_GET_RGB_G_TABLE 126
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#define VFE_CMD_GET_LA_TABLE 127
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#define VFE_CMD_DEMOSAICV3_UPDATE 128
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#define VFE_CMD_ACTIVE_REGION_CFG 129
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#define VFE_CMD_COLOR_PROCESSING_CONFIG 130
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#define VFE_CMD_STATS_WB_AEC_CONFIG 131
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#define VFE_CMD_STATS_WB_AEC_UPDATE 132
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#define VFE_CMD_Y_GAMMA_CONFIG 133
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#define VFE_CMD_SCALE_OUTPUT1_CONFIG 134
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#define VFE_CMD_SCALE_OUTPUT2_CONFIG 135
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struct msm_isp_cmd {
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int32_t id;
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uint16_t length;
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void *value;
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};
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#define VPE_CMD_DUMMY_0 0
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#define VPE_CMD_INIT 1
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#define VPE_CMD_DEINIT 2
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#define VPE_CMD_ENABLE 3
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#define VPE_CMD_DISABLE 4
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#define VPE_CMD_RESET 5
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#define VPE_CMD_FLUSH 6
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#define VPE_CMD_OPERATION_MODE_CFG 7
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#define VPE_CMD_INPUT_PLANE_CFG 8
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#define VPE_CMD_OUTPUT_PLANE_CFG 9
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#define VPE_CMD_INPUT_PLANE_UPDATE 10
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#define VPE_CMD_SCALE_CFG_TYPE 11
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#define VPE_CMD_DIS_OFFSET_CFG 12
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#define VPE_CMD_ZOOM 13
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#define MSM_PP_CMD_TYPE_NOT_USED 0 /* not used */
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#define MSM_PP_CMD_TYPE_VPE 1 /* VPE cmd */
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#define MSM_PP_CMD_TYPE_MCTL 2 /* MCTL cmd */
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#define MCTL_CMD_DUMMY_0 0 /* not used */
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#define MCTL_CMD_GET_FRAME_BUFFER 1 /* reserve a free frame buffer */
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#define MCTL_CMD_PUT_FRAME_BUFFER 2 /* return the free frame buffer */
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#define MCTL_CMD_DIVERT_FRAME_PP_PATH 3 /* divert frame for pp */
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/* event typese sending to MCTL PP module */
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#define MCTL_PP_EVENT_NOTUSED 0
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#define MCTL_PP_EVENT_CMD_ACK 1
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#define VPE_OPERATION_MODE_CFG_LEN 8
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#define VPE_INPUT_PLANE_CFG_LEN 24
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#define VPE_OUTPUT_PLANE_CFG_LEN 24
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#define VPE_INPUT_PLANE_UPDATE_LEN 12
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#define VPE_SCALER_CONFIG_LEN 260
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#define VPE_DIS_OFFSET_CFG_LEN 12
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struct msm_vpe_op_mode_cfg {
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uint8_t op_mode_cfg[VPE_OPERATION_MODE_CFG_LEN];
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};
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struct msm_vpe_input_plane_cfg {
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uint8_t input_plane_cfg[VPE_INPUT_PLANE_CFG_LEN];
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};
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struct msm_vpe_output_plane_cfg {
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uint8_t output_plane_cfg[VPE_OUTPUT_PLANE_CFG_LEN];
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};
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struct msm_vpe_input_plane_update_cfg {
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uint8_t input_plane_update_cfg[VPE_INPUT_PLANE_UPDATE_LEN];
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};
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struct msm_vpe_scaler_cfg {
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uint8_t scaler_cfg[VPE_SCALER_CONFIG_LEN];
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};
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struct msm_vpe_dis_offset_cfg {
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uint8_t dis_offset_cfg[VPE_DIS_OFFSET_CFG_LEN];
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};
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struct msm_vpe_flush_frame_buffer {
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uint32_t src_buf_handle;
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uint32_t dest_buf_handle;
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int path;
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};
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struct msm_mctl_pp_frame_buffer {
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uint32_t buf_handle;
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int path;
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};
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struct msm_mctl_pp_divert_pp {
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int path;
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int enable;
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};
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struct msm_vpe_clock_rate {
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uint32_t rate;
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};
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struct msm_pp_crop {
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uint32_t src_x;
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uint32_t src_y;
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uint32_t src_w;
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uint32_t src_h;
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uint32_t dst_x;
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uint32_t dst_y;
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uint32_t dst_w;
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uint32_t dst_h;
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uint8_t update_flag;
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};
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#define MSM_MCTL_PP_VPE_FRAME_ACK (1<<0)
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#define MSM_MCTL_PP_VPE_FRAME_TO_APP (1<<1)
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struct msm_mctl_pp_frame_cmd {
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uint32_t cookie;
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uint8_t vpe_output_action;
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uint32_t src_buf_handle;
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uint32_t dest_buf_handle;
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struct msm_pp_crop crop;
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int path;
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/* TBD: 3D related */
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};
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#endif /*__MSM_ISP_H__*/
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