8e7b85734e
Introduce optional ticket locks to help ensure fairness in contended locks, as well as preventing livelock. CRs-fixed: 302764 Signed-off-by: Brent DeGraaf <bdegraaf@codeaurora.org> Conflicts: arch/arm/include/asm/spinlock.h
395 lines
8.7 KiB
C
395 lines
8.7 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#if __LINUX_ARM_ARCH__ < 6
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#error SMP not supported on pre-ARMv6 CPUs
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#endif
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#include <asm/processor.h>
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/*
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* sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K
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* extensions, so when running on UP, we have to patch these instructions away.
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*/
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#define ALT_SMP(smp, up) \
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"9998: " smp "\n" \
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" .pushsection \".alt.smp.init\", \"a\"\n" \
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" .long 9998b\n" \
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" " up "\n" \
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" .popsection\n"
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#ifdef CONFIG_THUMB2_KERNEL
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#define SEV ALT_SMP("sev.w", "nop.w")
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/*
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* For Thumb-2, special care is needed to ensure that the conditional WFE
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* instruction really does assemble to exactly 4 bytes (as required by
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* the SMP_ON_UP fixup code). By itself "wfene" might cause the
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* assembler to insert a extra (16-bit) IT instruction, depending on the
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* presence or absence of neighbouring conditional instructions.
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*
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* To avoid this unpredictableness, an approprite IT is inserted explicitly:
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* the assembler won't change IT instructions which are explicitly present
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* in the input.
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*/
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#define WFE(cond) ALT_SMP( \
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"it " cond "\n\t" \
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"wfe" cond ".n", \
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\
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"nop.w" \
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)
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#else
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#define SEV ALT_SMP("sev", "nop")
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#define WFE(cond) ALT_SMP("wfe" cond, "nop")
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#endif
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static inline void dsb_sev(void)
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{
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#if __LINUX_ARM_ARCH__ >= 7
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__asm__ __volatile__ (
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"dsb\n"
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SEV
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);
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#else
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__asm__ __volatile__ (
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"mcr p15, 0, %0, c7, c10, 4\n"
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SEV
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: : "r" (0)
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);
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#endif
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}
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#ifndef CONFIG_ARM_TICKET_LOCKS
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/*
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* ARMv6 Spin-locking.
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*
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* We exclusively read the old value. If it is zero, we may have
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* won the lock, so we try exclusively storing it. A memory barrier
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* is required after we get a lock, and before we release it, because
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* V6 CPUs are assumed to have weakly ordered memory.
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*
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* Unlocked value: 0
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* Locked value: 1
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*/
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#define arch_spin_is_locked(x) ((x)->lock != 0)
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#define arch_spin_unlock_wait(lock) \
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do { while (arch_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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WFE("ne")
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" strexeq %0, %2, [%1]\n"
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" teqeq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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smp_mb();
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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" ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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if (tmp == 0) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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smp_mb();
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__asm__ __volatile__(
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" str %1, [%0]\n"
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:
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: "r" (&lock->lock), "r" (0)
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: "cc");
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dsb_sev();
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}
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#else
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/*
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* ARM Ticket spin-locking
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*
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* Ticket locks are conceptually two parts, one indicating the current head of
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* the queue, and the other indicating the current tail. The lock is acquired
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* by atomically noting the tail and incrementing it by one (thus adding
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* ourself to the queue and noting our position), then waiting until the head
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* becomes equal to the the initial value of the tail.
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*
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* Unlocked value: 0
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* Locked value: now_serving != next_ticket
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*
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* 31 17 16 15 14 0
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* +----------------------------------------------------+
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* | now_serving | next_ticket |
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* +----------------------------------------------------+
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*/
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#define TICKET_SHIFT 16
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#define TICKET_BITS 16
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#define TICKET_MASK 0xFFFF
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#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
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static inline void arch_spin_lock(arch_spinlock_t *lock)
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{
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unsigned long tmp, ticket, next_ticket;
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/* Grab the next ticket and wait for it to be "served" */
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__asm__ __volatile__(
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"1: ldrex %[ticket], [%[lockaddr]]\n"
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" uadd16 %[next_ticket], %[ticket], %[val1]\n"
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" strex %[tmp], %[next_ticket], [%[lockaddr]]\n"
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" teq %[tmp], #0\n"
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" bne 1b\n"
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" uxth %[ticket], %[ticket]\n"
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"2:\n"
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#ifdef CONFIG_CPU_32v6K
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" wfene\n"
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#endif
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" ldr %[tmp], [%[lockaddr]]\n"
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" cmp %[ticket], %[tmp], lsr #16\n"
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" bne 2b"
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: [ticket]"=&r" (ticket), [tmp]"=&r" (tmp), [next_ticket]"=&r" (next_ticket)
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: [lockaddr]"r" (&lock->lock), [val1]"r" (1)
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: "cc");
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smp_mb();
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}
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static inline int arch_spin_trylock(arch_spinlock_t *lock)
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{
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unsigned long tmp, ticket, next_ticket;
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/* Grab lock if now_serving == next_ticket and access is exclusive */
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__asm__ __volatile__(
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" ldrex %[ticket], [%[lockaddr]]\n"
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" ror %[tmp], %[ticket], #16\n"
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" eors %[tmp], %[tmp], %[ticket]\n"
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" bne 1f\n"
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" uadd16 %[next_ticket], %[ticket], %[val1]\n"
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" strex %[tmp], %[next_ticket], [%[lockaddr]]\n"
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"1:"
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: [ticket]"=&r" (ticket), [tmp]"=&r" (tmp),
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[next_ticket]"=&r" (next_ticket)
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: [lockaddr]"r" (&lock->lock), [val1]"r" (1)
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: "cc");
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if (!tmp)
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smp_mb();
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return !tmp;
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}
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static inline void arch_spin_unlock(arch_spinlock_t *lock)
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{
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unsigned long ticket, tmp;
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smp_mb();
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/* Bump now_serving by 1 */
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__asm__ __volatile__(
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"1: ldrex %[ticket], [%[lockaddr]]\n"
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" uadd16 %[ticket], %[ticket], %[serving1]\n"
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" strex %[tmp], %[ticket], [%[lockaddr]]\n"
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" teq %[tmp], #0\n"
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" bne 1b"
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: [ticket]"=&r" (ticket), [tmp]"=&r" (tmp)
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: [lockaddr]"r" (&lock->lock), [serving1]"r" (0x00010000)
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: "cc");
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dsb_sev();
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}
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static inline void arch_spin_unlock_wait(arch_spinlock_t *lock)
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{
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unsigned long ticket;
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/* Wait for now_serving == next_ticket */
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__asm__ __volatile__(
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#ifdef CONFIG_CPU_32v6K
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" cmpne %[lockaddr], %[lockaddr]\n"
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"1: wfene\n"
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#else
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"1:\n"
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#endif
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" ldr %[ticket], [%[lockaddr]]\n"
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" eor %[ticket], %[ticket], %[ticket], lsr #16\n"
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" uxth %[ticket], %[ticket]\n"
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" cmp %[ticket], #0\n"
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" bne 1b"
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: [ticket]"=&r" (ticket)
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: [lockaddr]"r" (&lock->lock)
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: "cc");
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}
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static inline int arch_spin_is_locked(arch_spinlock_t *lock)
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{
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unsigned long tmp = ACCESS_ONCE(lock->lock);
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return (((tmp >> TICKET_SHIFT) ^ tmp) & TICKET_MASK) != 0;
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}
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static inline int arch_spin_is_contended(arch_spinlock_t *lock)
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{
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unsigned long tmp = ACCESS_ONCE(lock->lock);
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return ((tmp - (tmp >> TICKET_SHIFT)) & TICKET_MASK) > 1;
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}
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#endif
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/*
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* RWLOCKS
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*
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*
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* Write locks are easy - we just set bit 31. When unlocking, we can
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* just write zero since the lock is exclusively held.
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*/
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static inline void arch_write_lock(arch_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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WFE("ne")
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" strexeq %0, %2, [%1]\n"
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" teq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc");
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smp_mb();
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}
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static inline int arch_write_trylock(arch_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc");
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if (tmp == 0) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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static inline void arch_write_unlock(arch_rwlock_t *rw)
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{
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smp_mb();
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__asm__ __volatile__(
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"str %1, [%0]\n"
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:
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: "r" (&rw->lock), "r" (0)
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: "cc");
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dsb_sev();
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}
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/* write_can_lock - would write_trylock() succeed? */
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#define arch_write_can_lock(x) ((x)->lock == 0)
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/*
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* Read locks are a bit more hairy:
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* - Exclusively load the lock value.
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* - Increment it.
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* - Store new lock value if positive, and we still own this location.
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* If the value is negative, we've already failed.
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* - If we failed to store the value, we want a negative result.
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* - If we failed, try again.
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* Unlocking is similarly hairy. We may have multiple read locks
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* currently active. However, we know we won't have any write
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* locks.
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*/
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static inline void arch_read_lock(arch_rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" adds %0, %0, #1\n"
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" strexpl %1, %0, [%2]\n"
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WFE("mi")
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" rsbpls %0, %1, #0\n"
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" bmi 1b"
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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smp_mb();
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}
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static inline void arch_read_unlock(arch_rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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smp_mb();
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" sub %0, %0, #1\n"
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" strex %1, %0, [%2]\n"
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" teq %1, #0\n"
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" bne 1b"
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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if (tmp == 0)
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dsb_sev();
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}
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static inline int arch_read_trylock(arch_rwlock_t *rw)
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{
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unsigned long tmp, tmp2 = 1;
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" adds %0, %0, #1\n"
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" strexpl %1, %0, [%2]\n"
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: "=&r" (tmp), "+r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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smp_mb();
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return tmp2 == 0;
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}
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/* read_can_lock - would read_trylock() succeed? */
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#define arch_read_can_lock(x) ((x)->lock < 0x80000000)
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#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
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#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
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#define arch_spin_relax(lock) cpu_relax()
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#define arch_read_relax(lock) cpu_relax()
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#define arch_write_relax(lock) cpu_relax()
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#endif /* __ASM_SPINLOCK_H */
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