When emulating a SWP/SWPB instruction, check the condition code of the instruction and compare it against CPSR status bits rather than relying on the architecture to only raise an undefined instruction exception if the condition checks are passing. Change-Id: I9707960b091c3a5af20e396e0b6d5ed2aaf935ff Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
325 lines
7.9 KiB
C
325 lines
7.9 KiB
C
/*
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* linux/arch/arm/kernel/swp_emulate.c
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*
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* Copyright (C) 2009 ARM Limited
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* __user_* functions adapted from include/asm/uaccess.h
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Implements emulation of the SWP/SWPB instructions using load-exclusive and
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* store-exclusive for processors that have them disabled (or future ones that
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* might not implement them).
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*
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* Syntax of SWP{B} instruction: SWP{B}<c> <Rt>, <Rt2>, [<Rn>]
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* Where: Rt = destination
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* Rt2 = source
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* Rn = address
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/proc_fs.h>
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#include <linux/sched.h>
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#include <linux/syscalls.h>
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#include <linux/perf_event.h>
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#include <asm/traps.h>
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#include <asm/uaccess.h>
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/*
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* Error-checking SWP macros implemented using ldrex{b}/strex{b}
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*/
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#define __user_swpX_asm(data, addr, res, temp, B) \
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__asm__ __volatile__( \
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" mov %2, %1\n" \
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"0: ldrex"B" %1, [%3]\n" \
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"1: strex"B" %0, %2, [%3]\n" \
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" cmp %0, #0\n" \
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" movne %0, %4\n" \
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"2:\n" \
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" .section .fixup,\"ax\"\n" \
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" .align 2\n" \
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"3: mov %0, %5\n" \
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" b 2b\n" \
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" .previous\n" \
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" .section __ex_table,\"a\"\n" \
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" .align 3\n" \
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" .long 0b, 3b\n" \
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" .long 1b, 3b\n" \
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" .previous" \
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: "=&r" (res), "+r" (data), "=&r" (temp) \
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: "r" (addr), "i" (-EAGAIN), "i" (-EFAULT) \
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: "cc", "memory")
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#define __user_swp_asm(data, addr, res, temp) \
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__user_swpX_asm(data, addr, res, temp, "")
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#define __user_swpb_asm(data, addr, res, temp) \
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__user_swpX_asm(data, addr, res, temp, "b")
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/*
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* Macros/defines for extracting register numbers from instruction.
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*/
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#define EXTRACT_REG_NUM(instruction, offset) \
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(((instruction) & (0xf << (offset))) >> (offset))
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#define RN_OFFSET 16
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#define RT_OFFSET 12
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#define RT2_OFFSET 0
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/*
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* Bit 22 of the instruction encoding distinguishes between
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* the SWP and SWPB variants (bit set means SWPB).
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*/
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#define TYPE_SWPB (1 << 22)
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static unsigned long swpcounter;
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static unsigned long swpbcounter;
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static unsigned long abtcounter;
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static pid_t previous_pid;
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#ifdef CONFIG_PROC_FS
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static int proc_read_status(char *page, char **start, off_t off, int count,
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int *eof, void *data)
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{
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char *p = page;
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int len;
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p += sprintf(p, "Emulated SWP:\t\t%lu\n", swpcounter);
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p += sprintf(p, "Emulated SWPB:\t\t%lu\n", swpbcounter);
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p += sprintf(p, "Aborted SWP{B}:\t\t%lu\n", abtcounter);
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if (previous_pid != 0)
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p += sprintf(p, "Last process:\t\t%d\n", previous_pid);
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len = (p - page) - off;
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if (len < 0)
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len = 0;
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*eof = (len <= count) ? 1 : 0;
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*start = page + off;
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return len;
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}
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#endif
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/*
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* Set up process info to signal segmentation fault - called on access error.
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*/
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static void set_segfault(struct pt_regs *regs, unsigned long addr)
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{
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siginfo_t info;
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if (find_vma(current->mm, addr) == NULL)
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info.si_code = SEGV_MAPERR;
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else
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info.si_code = SEGV_ACCERR;
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info.si_signo = SIGSEGV;
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info.si_errno = 0;
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info.si_addr = (void *) instruction_pointer(regs);
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pr_debug("SWP{B} emulation: access caused memory abort!\n");
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arm_notify_die("Illegal memory access", regs, &info, 0, 0);
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abtcounter++;
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}
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static int emulate_swpX(unsigned int address, unsigned int *data,
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unsigned int type)
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{
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unsigned int res = 0;
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if ((type != TYPE_SWPB) && (address & 0x3)) {
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/* SWP to unaligned address not permitted */
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pr_debug("SWP instruction on unaligned pointer!\n");
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return -EFAULT;
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}
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while (1) {
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unsigned long temp;
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/*
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* Barrier required between accessing protected resource and
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* releasing a lock for it. Legacy code might not have done
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* this, and we cannot determine that this is not the case
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* being emulated, so insert always.
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*/
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smp_mb();
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if (type == TYPE_SWPB)
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__user_swpb_asm(*data, address, res, temp);
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else
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__user_swp_asm(*data, address, res, temp);
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if (likely(res != -EAGAIN) || signal_pending(current))
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break;
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cond_resched();
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}
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if (res == 0) {
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/*
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* Barrier also required between acquiring a lock for a
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* protected resource and accessing the resource. Inserted for
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* same reason as above.
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*/
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smp_mb();
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if (type == TYPE_SWPB)
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swpbcounter++;
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else
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swpcounter++;
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}
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return res;
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}
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static int check_condition(struct pt_regs *regs, unsigned int insn)
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{
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unsigned int base_cond, neg, cond = 0;
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unsigned int cpsr_z, cpsr_c, cpsr_n, cpsr_v;
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cpsr_n = (regs->ARM_cpsr & PSR_N_BIT) ? 1 : 0;
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cpsr_z = (regs->ARM_cpsr & PSR_Z_BIT) ? 1 : 0;
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cpsr_c = (regs->ARM_cpsr & PSR_C_BIT) ? 1 : 0;
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cpsr_v = (regs->ARM_cpsr & PSR_V_BIT) ? 1 : 0;
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/* Upper 3 bits indicate condition, lower bit incicates negation */
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base_cond = insn >> 29;
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neg = insn & BIT(28) ? 1 : 0;
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switch (base_cond) {
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case 0x0: /* equal */
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cond = cpsr_z;
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break;
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case 0x1: /* carry set */
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cond = cpsr_c;
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break;
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case 0x2: /* minus / negative */
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cond = cpsr_n;
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break;
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case 0x3: /* overflow */
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cond = cpsr_v;
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break;
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case 0x4: /* unsigned higher */
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cond = (cpsr_c == 1) && (cpsr_z == 0);
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break;
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case 0x5: /* signed greater / equal */
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cond = (cpsr_n == cpsr_v);
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break;
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case 0x6: /* signed greater */
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cond = (cpsr_z == 0) && (cpsr_n == cpsr_v);
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break;
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case 0x7: /* always */
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cond = 1;
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break;
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};
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return cond && !neg;
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}
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/*
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* swp_handler logs the id of calling process, dissects the instruction, sanity
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* checks the memory location, calls emulate_swpX for the actual operation and
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* deals with fixup/error handling before returning
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*/
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static int swp_handler(struct pt_regs *regs, unsigned int instr)
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{
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unsigned int address, destreg, data, type;
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unsigned int res = 0;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, 0, regs, regs->ARM_pc);
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if (current->pid != previous_pid) {
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pr_debug("\"%s\" (%ld) uses deprecated SWP{B} instruction\n",
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current->comm, (unsigned long)current->pid);
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previous_pid = current->pid;
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}
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/* Ignore the instruction if it fails its condition code check */
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if (!check_condition(regs, instr)) {
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regs->ARM_pc += 4;
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return 0;
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}
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address = regs->uregs[EXTRACT_REG_NUM(instr, RN_OFFSET)];
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data = regs->uregs[EXTRACT_REG_NUM(instr, RT2_OFFSET)];
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destreg = EXTRACT_REG_NUM(instr, RT_OFFSET);
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type = instr & TYPE_SWPB;
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pr_debug("addr in r%d->0x%08x, dest is r%d, source in r%d->0x%08x)\n",
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EXTRACT_REG_NUM(instr, RN_OFFSET), address,
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destreg, EXTRACT_REG_NUM(instr, RT2_OFFSET), data);
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/* Check access in reasonable access range for both SWP and SWPB */
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if (!access_ok(VERIFY_WRITE, (address & ~3), 4)) {
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pr_debug("SWP{B} emulation: access to %p not allowed!\n",
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(void *)address);
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res = -EFAULT;
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} else {
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res = emulate_swpX(address, &data, type);
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}
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if (res == 0) {
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/*
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* On successful emulation, revert the adjustment to the PC
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* made in kernel/traps.c in order to resume execution at the
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* instruction following the SWP{B}.
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*/
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regs->ARM_pc += 4;
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regs->uregs[destreg] = data;
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} else if (res == -EFAULT) {
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/*
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* Memory errors do not mean emulation failed.
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* Set up signal info to return SEGV, then return OK
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*/
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set_segfault(regs, address);
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}
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return 0;
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}
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/*
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* Only emulate SWP/SWPB executed in ARM state/User mode.
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* The kernel must be SWP free and SWP{B} does not exist in Thumb/ThumbEE.
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*/
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static struct undef_hook swp_hook = {
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.instr_mask = 0x0fb00ff0,
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.instr_val = 0x01000090,
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.cpsr_mask = MODE_MASK | PSR_T_BIT | PSR_J_BIT,
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.cpsr_val = USR_MODE,
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.fn = swp_handler
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};
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/*
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* Register handler and create status file in /proc/cpu
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* Invoked as late_initcall, since not needed before init spawned.
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*/
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static int __init swp_emulation_init(void)
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{
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#ifdef CONFIG_PROC_FS
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struct proc_dir_entry *res;
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res = create_proc_entry("cpu/swp_emulation", S_IRUGO, NULL);
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if (!res)
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return -ENOMEM;
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res->read_proc = proc_read_status;
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#endif /* CONFIG_PROC_FS */
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printk(KERN_NOTICE "Registering SWP/SWPB emulation handler\n");
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register_undef_hook(&swp_hook);
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return 0;
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}
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late_initcall(swp_emulation_init);
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