ac69ee635c
In 7x30 device DDR1 Ram's 2nd bank starts from address 0x20000000 while in DDR2 Ram, start address is 0x40000000. Hence physical offset for 2nd bank needs to be configured depending on the address of 2nd bank. This offset is used in virtual to physical address calculation and vice versa. Hence add a machine fixup fuction, which at runtime will find the address of 2nd bank and accordingly configure the physical offset. So device with any memory configuration will be able to boot. CRs-Fixed: 326370 Change-Id: I094ca0fc17c50a85009c81169a57194b06f86456 Signed-off-by: Pankaj Kumar <pakuma@codeaurora.org>
138 lines
4.3 KiB
C
138 lines
4.3 KiB
C
/* arch/arm/mach-msm/include/mach/memory.h
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*
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* Copyright (C) 2007 Google, Inc.
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* Copyright (c) 2009-2012, Code Aurora Forum. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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#include <linux/types.h>
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/* physical offset of RAM */
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#define PLAT_PHYS_OFFSET UL(CONFIG_PHYS_OFFSET)
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#define MAX_PHYSMEM_BITS 32
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#define SECTION_SIZE_BITS 28
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/* Maximum number of Memory Regions
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* The largest system can have 4 memory banks, each divided into 8 regions
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*/
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#define MAX_NR_REGIONS 32
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/* The number of regions each memory bank is divided into */
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#define NR_REGIONS_PER_BANK 8
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/* Certain configurations of MSM7x30 have multiple memory banks.
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* One or more of these banks can contain holes in the memory map as well.
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* These macros define appropriate conversion routines between the physical
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* and virtual address domains for supporting these configurations using
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* SPARSEMEM and a 3G/1G VM split.
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*/
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#if defined(CONFIG_ARCH_MSM7X30)
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#define EBI0_PHYS_OFFSET PHYS_OFFSET
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#define EBI0_PAGE_OFFSET PAGE_OFFSET
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#define EBI0_SIZE 0x10000000
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#ifndef __ASSEMBLY__
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extern unsigned long ebi1_phys_offset;
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#define EBI1_PHYS_OFFSET (ebi1_phys_offset)
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#define EBI1_PAGE_OFFSET (EBI0_PAGE_OFFSET + EBI0_SIZE)
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#if (defined(CONFIG_SPARSEMEM) && defined(CONFIG_VMSPLIT_3G))
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#define __phys_to_virt(phys) \
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((phys) >= EBI1_PHYS_OFFSET ? \
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(phys) - EBI1_PHYS_OFFSET + EBI1_PAGE_OFFSET : \
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(phys) - EBI0_PHYS_OFFSET + EBI0_PAGE_OFFSET)
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#define __virt_to_phys(virt) \
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((virt) >= EBI1_PAGE_OFFSET ? \
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(virt) - EBI1_PAGE_OFFSET + EBI1_PHYS_OFFSET : \
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(virt) - EBI0_PAGE_OFFSET + EBI0_PHYS_OFFSET)
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#endif
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#endif
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#endif
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#ifndef __ASSEMBLY__
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void *alloc_bootmem_aligned(unsigned long size, unsigned long alignment);
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void *allocate_contiguous_ebi(unsigned long, unsigned long, int);
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unsigned long allocate_contiguous_ebi_nomap(unsigned long, unsigned long);
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void clean_and_invalidate_caches(unsigned long, unsigned long, unsigned long);
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void clean_caches(unsigned long, unsigned long, unsigned long);
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void invalidate_caches(unsigned long, unsigned long, unsigned long);
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int platform_physical_remove_pages(u64, u64);
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int platform_physical_active_pages(u64, u64);
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int platform_physical_low_power_pages(u64, u64);
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extern int (*change_memory_power)(u64, u64, int);
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#if defined(CONFIG_ARCH_MSM_ARM11) || defined(CONFIG_ARCH_MSM_CORTEX_A5)
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void write_to_strongly_ordered_memory(void);
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void map_page_strongly_ordered(void);
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#endif
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#ifdef CONFIG_CACHE_L2X0
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extern void l2x0_cache_sync(void);
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#define finish_arch_switch(prev) do { l2x0_cache_sync(); } while (0)
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#endif
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#if defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960)
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extern void store_ttbr0(void);
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#define finish_arch_switch(prev) do { store_ttbr0(); } while (0)
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#endif
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#ifdef CONFIG_DONT_MAP_HOLE_AFTER_MEMBANK0
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extern unsigned long membank0_size;
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extern unsigned long membank1_start;
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#define MEMBANK0_PHYS_OFFSET PHYS_OFFSET
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#define MEMBANK0_PAGE_OFFSET PAGE_OFFSET
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#define MEMBANK1_PHYS_OFFSET (membank1_start)
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#define MEMBANK1_PAGE_OFFSET (MEMBANK0_PAGE_OFFSET + (membank0_size))
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#define __phys_to_virt(phys) \
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((MEMBANK1_PHYS_OFFSET && ((phys) >= MEMBANK1_PHYS_OFFSET)) ? \
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(phys) - MEMBANK1_PHYS_OFFSET + MEMBANK1_PAGE_OFFSET : \
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(phys) - MEMBANK0_PHYS_OFFSET + MEMBANK0_PAGE_OFFSET)
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#define __virt_to_phys(virt) \
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((MEMBANK1_PHYS_OFFSET && ((virt) >= MEMBANK1_PAGE_OFFSET)) ? \
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(virt) - MEMBANK1_PAGE_OFFSET + MEMBANK1_PHYS_OFFSET : \
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(virt) - MEMBANK0_PAGE_OFFSET + MEMBANK0_PHYS_OFFSET)
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#endif
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#endif
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#if defined CONFIG_ARCH_MSM_SCORPION || defined CONFIG_ARCH_MSM_KRAIT
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#define arch_has_speculative_dfetch() 1
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#endif
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#endif
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/* these correspond to values known by the modem */
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#define MEMORY_DEEP_POWERDOWN 0
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#define MEMORY_SELF_REFRESH 1
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#define MEMORY_ACTIVE 2
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#define NPA_MEMORY_NODE_NAME "/mem/apps/ddr_dpd"
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#ifndef CONFIG_ARCH_MSM7X27
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#define CONSISTENT_DMA_SIZE (SZ_1M * 14)
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#endif
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