aa449e1efb
Synopsis 28nm PHY has two different circuits for detecting changes on ID line. ID_DIG is designed for detecting ID_float vs ID_gnd. ID_ACA is designed for detecting RID_A, RID_B, RID_C states. These are mutually exclusive and enabling both circuits has undefined behavior. Enable ID_ACA upon VBUS high or ID_gnd events to detect further ACA states. ACA ID_GND threshold range is overlapped with OTG ID_FLOAT threshold range. Hence PHY ID_DIG circuit can not be used for detecting ACA ID_GND. Use PMIC ID circuit for detecting both OTG and ACA ID_GND. Link controller can not generate PHY_ALT interrupt in host mode. But the corresponding PHY register reflects the actual ID state. Hence implement polling to read PHY register to detect ID_GND --> ID_A, ID_A --> ID_B transitions. That means low power mode can not be allowed in host mode. Also disallow suspending the device attached on the root hub. Otherwise PHY is put into suspend state automatically upon setting SUSP bit in PORTSC register. Link controller can not generate asynchronous interrupt for ID_ACA changes in low power mode. Hence disallow low power mode in ID_B and ID_C states. USB_MSM_ACA is not selected by default. If it selected, ACA states can be detected and low power mode is not allowed in host mode. Writing "enable" to <debugfs>/msm_otg/aca enables ACA irrespective of USB_MSM_ACA selection. This is meant for debugging only. Change-Id: I51e80d803a583c5bdffc8111696943c04958f604 Signed-off-by: Pavankumar Kondeti <pkondeti@codeaurora.org>
66 lines
2.4 KiB
C
66 lines
2.4 KiB
C
/*
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* Copyright (C) 2007 Google, Inc.
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* Author: Brian Swetland <swetland@google.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#ifndef __LINUX_USB_GADGET_MSM72K_UDC_H__
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#define __LINUX_USB_GADGET_MSM72K_UDC_H__
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#define USB_AHBBURST (MSM_USB_BASE + 0x0090)
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#define USB_AHBMODE (MSM_USB_BASE + 0x0098)
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#define USB_CAPLENGTH (MSM_USB_BASE + 0x0100) /* 8 bit */
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#define USB_USBCMD (MSM_USB_BASE + 0x0140)
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#define USB_USBSTS (MSM_USB_BASE + 0x0144)
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#define USB_PORTSC (MSM_USB_BASE + 0x0184)
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#define USB_OTGSC (MSM_USB_BASE + 0x01A4)
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#define USB_USBMODE (MSM_USB_BASE + 0x01A8)
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#define USB_PHY_CTRL (MSM_USB_BASE + 0x0240)
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#define USBCMD_RESET 2
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#define USB_USBINTR (MSM_USB_BASE + 0x0148)
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#define PORTSC_PHCD (1 << 23) /* phy suspend mode */
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#define PORTSC_PTS_MASK (3 << 30)
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#define PORTSC_PTS_ULPI (3 << 30)
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#define USB_ULPI_VIEWPORT (MSM_USB_BASE + 0x0170)
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#define ULPI_RUN (1 << 30)
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#define ULPI_WRITE (1 << 29)
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#define ULPI_READ (0 << 29)
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#define ULPI_SYNC_STATE (1 << 27)
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#define ULPI_ADDR(n) (((n) & 255) << 16)
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#define ULPI_DATA(n) ((n) & 255)
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#define ULPI_DATA_READ(n) (((n) >> 8) & 255)
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/* synopsys 28nm phy registers */
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#define ULPI_PWR_CLK_MNG_REG 0x88
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#define OTG_COMP_DISABLE BIT(0)
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#define PHY_ALT_INT (1 << 28) /* PHY alternate interrupt */
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#define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */
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#define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */
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#define PHY_RETEN (1 << 1) /* PHY retention enable/disable */
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/* OTG definitions */
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#define OTGSC_INTSTS_MASK (0x7f << 16)
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#define OTGSC_IDPU (1 << 5)
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#define OTGSC_ID (1 << 8)
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#define OTGSC_BSV (1 << 11)
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#define OTGSC_IDIS (1 << 16)
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#define OTGSC_BSVIS (1 << 19)
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#define OTGSC_IDIE (1 << 24)
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#define OTGSC_BSVIE (1 << 27)
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#endif /* __LINUX_USB_GADGET_MSM72K_UDC_H__ */
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