c29e3c60e7
Due to the full duplex nature of the SPI bus, the SPI master on DaVinci needs transmit to be active even if the tranfer is only meant to collect receive data. The current code achieves this by using a temporary zeroed buffer to provide DMA data in case the transfer does not have a transmit buffer provided. However, the transmit DMA is started only if transmit buffer is provided rendering the temporary buffer unused. Instead the code relies on a write to SPIDAT1 register to trigger transmit operation. This however only sends two bytes of data. Fix this by starting transmit DMA always. This changes exposes a bug on DM355 where the CSHOLD bit in SPIDAT1 needs to be written to in between transfers. Handle that by introducing a "cshold_bug" platform data which is set to true for DM355. Signed-off-by: Brian Niebuhr <bniebuhr@efjohnson.com> Tested-By: Michael Williamson <michael.williamson@criticallink.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
54 lines
1.3 KiB
C
54 lines
1.3 KiB
C
/*
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* Copyright 2009 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ARCH_ARM_DAVINCI_SPI_H
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#define __ARCH_ARM_DAVINCI_SPI_H
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#define SPI_INTERN_CS 0xFF
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enum {
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SPI_VERSION_1, /* For DM355/DM365/DM6467 */
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SPI_VERSION_2, /* For DA8xx */
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};
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struct davinci_spi_platform_data {
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u8 version;
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u8 num_chipselect;
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u8 clk_internal;
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u8 intr_line;
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u8 use_dma;
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u8 *chip_sel;
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bool cshold_bug;
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};
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struct davinci_spi_config {
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u8 wdelay;
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u8 odd_parity;
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u8 parity_enable;
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#define SPI_IO_TYPE_INTR 0
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#define SPI_IO_TYPE_POLL 1
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u8 io_type;
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u8 timer_disable;
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u8 c2tdelay;
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u8 t2cdelay;
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u8 t2edelay;
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u8 c2edelay;
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};
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#endif /* __ARCH_ARM_DAVINCI_SPI_H */
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