Upper layers are not acquiring the locks properly, hence wakelock release
timeout is increased to 500 ms. This logic and value is derived from
the implementation for UART transport.
CRs-fixed: 325550
Change-Id: I15c39705e63ebb1fb4ccac3c42d72f0cc1e32929
Signed-off-by: Mallikarjuna GB <gbmalli@codeaurora.org>