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d2b854419501d2e069c176eff058d41530f27a52
android-g900/Start_WM/test6/inc/GFRm.h
Angell Fear d2b8544195 fb fix, ts fix, flash ttfs experemental
2010-10-16 00:02:07 +06:00

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/* Copyright (c) 2006 NVIDIA Corporation. All rights reserved.
*
* NVIDIA Corporation and its licensors retain all intellectual property
* and proprietary rights in and to this software, related documentation
* and any modifications thereto. Any use, reproduction, disclosure or
* distribution of this software and related documentation without an
* express license agreement from NVIDIA Corporation is strictly prohibited.
*/
/** @file GFRm.h
GFSDK Resource Manager API header file.
*/
#ifndef __GFRM_H__
#define __GFRM_H__
#include "GF.h"
#include "GFRmError.h"
/** @addtogroup groupRm RmAPI Resource Manager API
<ul>
<li> @ref pageRmAppNotes
<ul>
<li> @ref pageRmAppNotes1
</ul>
</ul>
*/
/*@{*/
#ifdef __cplusplus
extern "C"
{
#endif /* __cplusplus */
#include "GFRmScr.h"
/** Hardware Module IDs.
List of all the modules in the SCXX chips.
*/
typedef enum
{
#define GFRM_MODULE(x,y) MODID_##x,
#include "gfrm_module_ids.h"
#undef GFRM_MODULE
GFNUMOFMODULEIDS
} eGFModuleIDs;
/** @name Power Planes/Islands
List of all the power planes in the SCXX chips.
@{*/
/** Power Plane ID: Core Power Plane. */
#define GFPPID_AOCVDD 0x00000001
/** Power Plane ID: Video Codec Power Plane. */
#define GFPPID_VECVDD 0x00000002
/** Power Plane ID: SRAM Power Plane. */
#define GFPPID_MMCVDD 0x00000004
/** Power Plane ID: 3D Power Plane. */
#define GFPPID_TDCVDD 0x00000008
/** Power Plane ID: SRAM I/O Power Plane. */
#define GFPPID_EMVDD 0x00000010
/** Power Plane ID: Mostly Bus Interface Power Plane. */
#define GFPPID_HVDD 0x00000020
/** Power Plane ID: Video I/O Power Plane. */
#define GFPPID_VVDD 0x00000040
/** Power Plane ID: LCD I/O Power Plane. */
#define GFPPID_LVDD 0x00000080
/** Power Plane ID: Audio I/O Power Plane. */
#define GFPPID_ACVDD 0x00000100
/** Power Plane ID: SD I/O Power Plane. */
#define GFPPID_SDVDD 0x00000200
/** Power Plane ID: Oscillator Power Plane. */
#define GFPPID_AVDDOSC 0x00000400
/** Power Plane ID: PLL1 Power Plane. */
#define GFPPID_AVDDP1 0x00000800
/** Power Plane ID: PLL2 Power Plane. */
#define GFPPID_AVDDP2 0x00001000
/** Power Plane ID: DRAM Power Plane. */
#define GFPPID_DRAM 0x00002000
/** Number of power plane IDs. */
#define GFNUMOFPPIDS 14
/*@}*/
/** @name States for Component Manager and general services
@{*/
/** State for registering Component.
@see GF_STATE_TYPE, GFRmComponentGet().
*/
#define GF_STATE_REGISTER 0x00000001
/** State for unregistering Component.
@see GF_STATE_TYPE, GFRmComponentRelease().
*/
#define GF_STATE_UNREGISTER 0x00000002
/** State for unregistering all Components (internal used only).
@see GF_STATE_TYPE, GFRmComponentRelease().
*/
#define GF_STATE_UNREGISTER_ALL 0x00000004
/** General Enable State.
@see GF_STATE_TYPE.
*/
#define GF_STATE_ENABLE 0x00000008
/** General Disable State.
@see GF_STATE_TYPE.
*/
#define GF_STATE_DISABLE 0x00000010
/** General Done State.
@see GF_STATE_TYPE.
*/
#define GF_STATE_DONE 0x00000020
/** State for instantiating a new or share Component.
@see GF_STATE_TYPE, GFRmComponentGet().
*/
#define GF_STATE_NEW_OR_SHARE 0x00000100
/** State for instantiating a new Component only.
@see GF_STATE_TYPE, GFRmComponentGet().
*/
#define GF_STATE_NEW_ONLY 0x00000200
/** State for instantiating a share Component only.
@see GF_STATE_TYPE, GFRmComponentGet().
*/
#define GF_STATE_SHARE_ONLY 0x00000400
/** State indicating special Block Device Component (internal use).
@see GF_STATE_TYPE, GFRmComponentGet().
*/
#define GF_STATE_BLOCK_DEVICE 0x80000000
/** Default Component instantiation State.
@see GF_STATE_TYPE, GFRmComponentGet().
*/
#define GF_STATE_DEFAULT GF_STATE_NEW_OR_SHARE
/** Mask for the regular States.
@see GF_STATE_TYPE.
*/
#define GF_STATE_MASK 0x000000FF
/*@}*/
/** Attributes ID/Values.
@see GFRmGetAttribute(), GFRmSetAttribute().
*/
typedef enum
{
/** Attribute for changing device bus addressing (direct/indirect) mode. */
GF_ATTRIB_DEVICE_ADDRESS,
/** Attribute for mapped/virtual/usable I/O base address. */
GF_ATTRIB_IO_MAP_BASE,
/** Attribute for mapped/virtual/usable embedded memory base. */
GF_ATTRIB_EMBEDDED_MEM_MAP_BASE,
/** Attribute for initial embedded internal memory size. */
GF_ATTRIB_INIT_EMBEDDED_MEM_TOTAL,
/** Attribute for initial available embedded internal memory size. */
GF_ATTRIB_INIT_EMBEDDED_MEM_AVAIL,
/** Attribute for initial embedded extended memory size. */
GF_ATTRIB_INIT_EXT_EMBEDDED_MEM_TOTAL,
/** Attribute for user specific object 0. */
GF_ATTRIB_USER_OBJECT_0,
/** Attribute for user specific object 1. */
GF_ATTRIB_USER_OBJECT_1,
/** Attribute for user specific object 2. */
GF_ATTRIB_USER_OBJECT_2,
/** Attribute for user specific object 3. */
GF_ATTRIB_USER_OBJECT_3,
/** Attribute for swapping memory allocation with shared embedded memory
MAX CHUNK scheme. For advanced user only. */
GF_ATTRIB_SWAP_SHARE_MEMORY_ALLOC_ON_MAX_CHUNK,
/** Get device information structure.
GFRmGetAttribute() parameter \a AttribData is of type PGFRMDEVICEINFO.
*/
GF_ATTRIB_DEVICE_INFO_STRUCT,
/** For internal use only. */
GF_ATTRIB_RMC_FLAG,
/** Enable/Disable Hardware Resource Constraint. */
GF_ATTRIB_HW_RESOURCE_CONSTRAINT,
/** Enable embedded extended memory. */
GF_ATTRIB_ENABLE_EXTENDED_MEMORY,
/** Disable RMC trace, closing any log files that might be opened */
GF_ATTRIB_DISABLE_RMC_TRACE,
/** Set/Clr surface with absolute rotation option. */
GF_ATTRIB_SURFACE_ABSOLUTE_ROTATE,
/** Primary surface freeing policy. */
GF_ATTRIB_PRIMSURF_FREEING_POLICY,
/** Primary surface allocation policy. */
GF_ATTRIB_PRIMSURF_ALLOCATION_POLICY,
/** Internal use. */
GF_ATTRIB_EFUSE_PRODUCT_SKU_ID,
/** Internal use. */
GF_ATTRIB_MAIN_PANEL_INDEX,
/** GFRm attribute: Set DSP2Host communication mode.
This attribute can be used to control how components wait
for messages from the DSP. The following options for \a AttribData are available:
- #GF_ATTRIB_DSPCOMMODE_POLLING -- Register polling.
This mode is intended for debuging only, since it allows only one client
to use DSP2Host interrupts.
- #GF_ATTRIB_DSPCOMMODE_EVENT -- Receive DSP2Host messages via an interrupt framework.
This mode requires an ISR/IST to be setup, that handles DSP interrupts and calls
GFRmDispatchMessage().
The default setting is register polling.
Attribute can be get and set.
@see GFRmSetAttribute(), GFRmGetAttribute(), GFRmQueueSetHandler(), GFRmDispatchMessage()
*/
GF_ATTRIB_DSPCOMMODE,
/** Set surface for DSP debug console output.
This sets a surface which will be used to output text from the DSP debug console.
The DSP XRM must be initialized before this function can be called.
GFRmSetAttribute() parameter \a AttribData is of type #PGFRMSURFACE and defines a pointer to a
surface descriptor.
@retval GF_SUCCESS Successfully send message
@retval GF_WAIT_TIME_OUT Timeout sending message
@retval GFRM_ERROR_BAD_PARAMETER Bad parameters, e.g. surface color format is not supported
@see GFRmSetAttribute()
Attribute can be set only.
*/
GF_ATTRIB_DSPCONSOLE_SURFACE,
/** Internal use. */
GF_ATTRIB_USE_CAMERA_SCRIPT,
/** Internal use. */
GF_ATTRIB_DEVICE_TYPE,
/** Timeout in ms for RM IST to wait for interrupts.
Set to 0 to disable timeout, default setting is 1000 ms.
GFRmSetAttribute() parameter \a AttribData is of type NvU32 and defines timout in ms.
*/
GF_ATTRIB_INTX_TIMEOUT,
/** Enable debug printout for GPU memory allocations.
GFRmSetAttribute() parameter \a AttribData is of type NvU32,
- 0 means disable log (default)
- !=0 means enable log
This GFRmSetAttribute() call always succeeds.
@see GFRmSetAttribute()
Attribute can be set only.
*/
GF_ATTRIB_GPUMEM_ENABLELOG
} GF_ATTRIBUTE_TYPE;
/** DSP2Host communication modes, polling.
@see GF_ATTRIB_DSPCOMMODE
*/
#define GF_ATTRIB_DSPCOMMODE_POLLING 0
/** DSP2Host communication modes, OS event synchronization.
@see GF_ATTRIB_DSPCOMMODE
*/
#define GF_ATTRIB_DSPCOMMODE_EVENT 1
/** GFSDK (low-level) device interface type. (Read Only)
* @see GF_ATTRIB_DEVICE_TYPE.
**/
#define GF_ATTRIB_DEVICE_TYPE_HARDWARE 0x00000000
#define GF_ATTRIB_DEVICE_TYPE_SIMULATOR 0x00001000
/** @name Component Types
@{*/
/** Component Type: EPP Component.
@anchor ComponentTypes
*/
#define GF_EPPAPI 0x00000001L
/** Component Type: Gx (2D) API Component. */
#define GF_GXAPI 0x00000002L
/** Component Type: Vx (general Video and Video Input Port) API Component. */
#define GF_VXAPI 0x00000003L
/** Component Type: JxE (JPEG Encode) API Component. */
#define GF_JXEAPI 0x00000004L
/** Component Type: JxE (JPEG Decode) API Component. */
#define GF_JXDAPI 0x00000005L
/** Component Type: MxE (MPEG Encode) API Component. */
#define GF_MXEAPI 0x00000006L
/** Component Type: MxD (MPEG Decode) API Component. */
#define GF_MXDAPI 0x00000007L
// 0x8 is unused
/** Component Type: Dx (Display and Flat Panel) API Component. */
#define GF_DXAPI 0x00000009L
// 0xA is unused
/** Component Type: ISP (Image Signal Processing) API Component. */
#define GF_ISPAPI 0x0000000BL
/** Component Type: FDev (Pseudo File System/Device) API Component. */
#define GF_FDEVAPI 0x0000000CL
/** Component Type: BDevSD (SD Block Device) Component. */
#define GF_BDEVSDAPI 0x0000000DL
// 0xE is unused
// 0xF is unused
/** Component Type: OSx (Operating System) API COmponent */
#define GF_OSXAPI 0x00000010L
/** Component Type: I2C API Component */
#define GF_I2CAPI 0x00000011L
/** Component Type: I2S API COmponent */
#define GF_I2SAPI 0x00000012L
/** Component Type: MMProc (Audio) API COmponent */
#define GF_MMPROCAPI 0x00000013L
/** Component Type: CAM (Camera) API Component */
#define GF_CAMAPI 0x00000014L
/** Component Type: 3D API Component */
#define GF_3DAPI 0x00000015L
/** Component Type: INTx (Interrupt) API COmponent */
#define GF_INTXAPI 0x00000016L
/** Component Type: MXDH264 (H264 Decoder) API COmponent */
#define GF_MXDH264API 0x00000017L
/** Component Type: MXEH264 (H264 Encoder) API Component */
#define GF_MXEH264API 0x00000018L
/** Component Type: RM (Resource Manager) Services (listed only for return status). */
#define GF_RMAPI 0x00000019L
/** Component Type: GxFB (Gx/2D API with Frame Buffer rendering) API. Internal Use. */
#define GF_GXFBAPI 0x0000001AL
/** MXDRV9 (RV9 Decoder) API COmponent */
#define GF_MXDRV9API 0x0000001BL
/** Component Type: MXDVC1 (VC1 Decoder) API Component */
#define GF_MXDVC1API 0x0000001CL
/** Component Type: MXDEMTS (MPEG TS Demux) API Component */
#define GF_MXDEMTSAPI 0x0000001DL
/** Component Type: Minimal ISP API Component (NvIsp) */
#define GF_MINIMALISPAPI 0x0000001EL
/** Component Type: NvISP API Component ID -- only used for GF_TRACE */
#define NV_ISPAPI 0x0000001FL
/*@}*/
/** NULL driver related. Internal use. */
#define GF_USE_NULL_DRIVER 0x1
/** NULL driver related. Internal use. */
#define GF_USE_HW_DRIVER 0x2
/** @name Hardware Resources
@anchor HardwareResources
Flags 'hwEngineReq' in GFRmHwResourceConstraint(). (not working yet).
@see GFRmHwResourceConstraint().
@{*/
/** Hardware resource flag: MPEG Decoder Engine. */
#define GF_HWR_MPEGD 0x00000001
/** Hardware resource flag: JPEG Decoder is same as MPEG Decoder Engine. */
#define GF_HWR_JPEGD 0x00000001
/** Hardware resource flag: MPEG Encoder Engine. */
#define GF_HWR_MPEGE 0x00000002
/** Hardware resource flag: JPEG Encoder shares FrontEnd and BackEnd with JPEG Enc Engine. */
#define GF_HWR_JPEGE 0x00000002
/** Hardware resource flag: Video Input Port. */
#define GF_HWR_VIP 0x00000004
/** Hardware resource flag: EPP */
#define GF_HWR_EPP 0x00000008
/** Options for GFRmHwResourceConstraint().
(not working yet!)
@see GFRmHwResourceConstraint().
*/
typedef enum
{
/** check availability and allocate hardware resource. */
GF_HRC_ALLOCATE,
/** free hardware resource. */
GF_HRC_FREE,
/** check availability of hardware resource. */
GF_HRC_CHECK
} GF_HRC_OPTIONS;
/*@}*/
/** Component ID structure. */
typedef struct _GFRMCOMPONENTID
{
NvU32 ComponentType; /**< Component Type, see @ref ComponentTypes. */
GFRmChHandle CxtHandle;
} GFRMCOMPONENTID, *PGFRMCOMPONENTID;
/* Component */
/* forward declaration */
typedef struct _GFRMCOMPONENT GFRMCOMPONENT, *PGFRMCOMPONENT;
typedef GF_HANDLE (* GFOPENFUNCTIONTYPE)(GFRmHandle pRm, GFRmChHandle);
typedef GF_RETTYPE (* GFCLOSEFUNCTIONTYPE)(GF_HANDLE *);
/** Component Registration structure.
Internal use.
@internal
*/
struct _GFRMCOMPONENT
{
GFRMCOMPONENTID id; /**< Structure defining component. */
GFOPENFUNCTIONTYPE Open; /**< Component Open callback. Called from GFRmComponentGet(). */
GFCLOSEFUNCTIONTYPE Close; /**< Component Close callback. Called from GFRmComponentRelease(). */
};
/** @name Surface Types
@anchor SurfaceTypes
@see GFRmSurfaceAlloc().
@{*/
/** Surface Type: Surface rotation orientation at 0 degree. */
#define GF_SURFACE_ROTATE_0 0x00000000
/** Surface Type: Surface rotation orientation at 90 degree (relative to _ROTATE_0). */
#define GF_SURFACE_ROTATE_90 0x10000000
/** Surface Type: Surface rotation orientation at 180 degree (relative to _ROTATE_0). */
#define GF_SURFACE_ROTATE_180 0x20000000
/** Surface Type: Surface rotation orientation at 270 degree (relative to _ROTATE_0). */
#define GF_SURFACE_ROTATE_270 0x30000000
/*
* GF_SURFACE_H_FLIP and GF_SURFACE_V_FLIP can be ORed with above 4 rotation
* options to create 16 combinations but in reality there are only 8 unique
* combinations.
*/
/** Surface Type: Horizontal Flip. You can or'ed this flag with _ROTATE_ flag above too. */
#define GF_SURFACE_H_FLIP 0x40000000
/** Surface Type: Vertical Flip. You can or'ed this flag with _ROTATE_ flag above too. */
#define GF_SURFACE_V_FLIP 0x80000000
/** Surface Type: internal use. */
#define GF_SURFACE_ROTATE_MASK 0xF0000000
/** Surface Type: internal use. */
#define GF_SURFACE_PLANAR_ROTATE_MASK 0x30000000
/** Surface Type: internal use. */
#define GF_SURFACE_ROTATE_SHIFT 28 // bits[31:28]
/** Surface Type: internal use. */
#define GF_SURFACE_ROTATE_WRAP 8
/** Surface Type: Primary Surface (default rotate orientation). */
#define GF_SURFACE_PRIMARY 0x00000001 //primary surface
/** Surface Type: Primary Surface with 0 degree rotation. */
#define GF_SURFACE_PRIMARY_0 (GF_SURFACE_PRIMARY| GF_SURFACE_ROTATE_0)
/** Surface Type: Primary Surface with 90 degree rotation. */
#define GF_SURFACE_PRIMARY_90 (GF_SURFACE_PRIMARY| GF_SURFACE_ROTATE_90)
/** Surface Type: Primary Surface with 180 degree rotation. */
#define GF_SURFACE_PRIMARY_180 (GF_SURFACE_PRIMARY| GF_SURFACE_ROTATE_180)
/** Surface Type: Primary Surface with 180 degree rotation. */
#define GF_SURFACE_PRIMARY_270 (GF_SURFACE_PRIMARY| GF_SURFACE_ROTATE_270)
/** Surface Type: Overlay Surface. */
#define GF_SURFACE_OVERLAY 0x00000002
/** Surface Type: Surface to reside in embedded (video) memory. */
#define GF_SURFACE_VIDEO_MEMORY 0x00000004
/** Surface Type: Surface to reside in system memory. */
#define GF_SURFACE_SYSTEM_MEMORY 0x00000008
/** Surface Type: Sub primary surface (for Sub LCD). */
#define GF_SURFACE_PRIMARY_SUB 0x00000100 //Sub primary surface
/** Surface Type: Surface to be allocated from "share" embedded memory for
advanced use only.
Cannot be used with #GF_SURFACE_PRIMARY.
No effect with #GF_SURFACE_SYSTEM_MEMORY.
*/
#define GF_SURFACE_SHARE 0x00001000
/** Surface Type: Allocate surface with pre-allocated memory handle. */
#define GF_SURFACE_PREALLOCATED_MEM 0x00002000
/** Request to use new API */
#define GF_SURFACE_NEW_API 0x01000000
/*
* Note: GF_SURFACE_ROTATE_ refers to caller's view of current logical
* orientation relative to Primary Surface. And Primary surface is
* always set to GF_SURFACE_ROTATE_0 even though physical LCD Display
* panel may require different physical orientation.
*/
/*@}*/
/** @name Surface Hints
@anchor SurfaceHints
@see GFRmSurfaceAlloc().
@{*/
/** Surface Hint: Alloc from highest possible position. */
#define GF_SURFACE_HINT_TOP_DOWN 0x1
/** Surface Hint: Alloc from lowest possible position. */
#define GF_SURFACE_HINT_BOTTOM_UP 0x2
/** Surface Hint: Alloc max chunck of memory. */
#define GF_SURFACE_HINT_MAX_CHUNK 0x4
/** Surface Hint: Try allocations from external memory first before internal memory */
#define GF_SURFACE_HINT_EXT_MEMORY_PREFERRED 0x8
/** Surface Hint: Try allocations only from external memory. */
#define GF_SURFACE_HINT_EXT_MEMORY_ONLY 0x10
/** Surface Hint: Try allocations only from internal memory. */
#define GF_SURFACE_HINT_INT_MEMORY_ONLY 0x20
/** Surface Hint: Alloc from embedded memory, YUV in the same contiguous memory.
Valid only for GF_SURFACE_YUV420.
*/
#define GF_SURFACE_HINT_CONTIGUOUS_MEMORY 0x40
/** Surface Hint: Try allocations from internal memory first before external memory */
#define GF_SURFACE_HINT_INT_MEMORY_PREFERRED 0x80
/** Surface Hint: Hints to align stride to 4 bytes - default for YUV422 */
#define GF_SURFACE_HINT_STRIDE_ALIGN4 0x100
/** Surface Hint: Hints to align stride to 8 bytes */
#define GF_SURFACE_HINT_STRIDE_ALIGN8 0x200
/** Surface Hint: Hints to align stride to 16 bytes */
#define GF_SURFACE_HINT_STRIDE_ALIGN16 0x400
/** Surface Hint: Hints to align stride to 32 bytes */
#define GF_SURFACE_HINT_STRIDE_ALIGN32 0x800
/** Surface Hint: Surface will be used for direct read by the applications */
#define GF_SURFACE_NEED_DIRECT_CPU_READ 0x1000
/** Surface Hint: Surface will be used for direct write by the applications */
#define GF_SURFACE_NEED_DIRECT_CPU_WRITE 0x2000
/** Surface Hint: Surface will be used for direct access by the applications
both read and write actions are allowed
*/
#define GF_SURFACE_NEED_DIRECT_CPU_ACCESS \
(GF_SURFACE_NEED_DIRECT_CPU_READ | GF_SURFACE_NEED_DIRECT_CPU_WRITE)
/*@}*/
/** @name Primary surface allocation and freeing policies
@see GFRmSetAttribute().
@{*/
/** Any avaliable memory. Use with GF_ATTRIB_PRIMSURF_ALLOCATION_POLICY. */
#define GF_ATTRIB_PRIMSURF_ALLOCP_NONE 0x0
/** Allocate Primary surface from embedded extended memory.
Use with GF_ATTRIB_PRIMSURF_ALLOCATION_POLICY.
*/
#define GF_ATTRIB_PRIMSURF_ALLOCP_USE_EXT_MEM 0x1
/** Allocate Primary surface from internal memory (SRAM).
Use with GF_ATTRIB_PRIMSURF_ALLOCATION_POLICY.
*/
#define GF_ATTRIB_PRIMSURF_ALLOCP_USE_INT_MEM 0x2
/** Use with GF_ATTRIB_PRIMSURF_FREEING_POLICY. */
#define GF_ATTRIB_PRIMSURF_FREEP_NONE 0x0
/** Never free, Default policy. Use with GF_ATTRIB_PRIMSURF_FREEING_POLICY. */
#define GF_ATTRIB_PRIMSURF_FREEP_NEVER_FREE 0x0
/** Free when the ref count is zero. Use with GF_ATTRIB_PRIMSURF_FREEING_POLICY. */
#define GF_ATTRIB_PRIMSURF_FREEP_FREE_ON_EMPTY 0x1
/** Force free. Use with GF_ATTRIB_PRIMSURF_FREEING_POLICY. */
#define GF_ATTRIB_PRIMSURF_FREEP_FORCE_FREE 0x2
/*@}*/
/** Surface structure.
@see GFRmSurfaceAlloc(), GFRmSurfaceFree().
*/
typedef struct _GFRMSURFACE
{
NvU32 width; /**< Width in pixels. */
NvU32 height; /**< Height in lines. */
NvU32 SurfaceType; /**< Surface type, see @ref SurfaceTypes. */
NvU32 ColorFormat; /**< Surface color format, see @ref SurfaceTypes. */
NvU32 YStride; /**< Stride for RGB, YUV422 surfaces, or Y plane. */
NvU32 UStride; /**< U plane stride */
NvU32 VStride; /**< V plane stride */
GFRmMemHandle YMemHandle; /**< Opaque handle for RGB, YUV422 surface, or Y plane memory. */
GFRmMemHandle VMemHandle; /**< Opaque handle for V plane memory. */
GFRmMemHandle UMemHandle; /**< Opaque handle for U plane memory. */
NvU32 YOffset; /**< Physical address of RGB, YUV422 surfae, or Y plane. */
NvU32 UOffset; /**< Physical address of U plane. */
NvU32 VOffset; /**< Physical address of U plane. */
/* Direct addressable pointer to the memory region. Don't
use these pointers, unless you want to run only in
"direct addressing mode". Instead, use handles for reading
or writing to the memory from the host, and offsets for
programming the hardware registers. */
NvU8 *pY; /**< Pointer to non-planar surface or Y plane of YUV420, valid only for direct addressing. */
NvU8 *pU; /**< for YUV420 surface, valid only for direct addressing. */
NvU8 *pV; /**< for YUV420 surface, valid only for direct addressing. */
NvU32 memUsed; /**< Total number of bytes used by surfaces. */
//void *reserved; // Reserved. Do not modify
} GFRMSURFACE, *PGFRMSURFACE;
/** Surface Request
@see GFRmSurfaceAlloc(), GFRmSurfaceFree().
*/
typedef struct _GFRMSURFACEREQUEST
{
NvU32 width; /**< Width in pixels. */
NvU32 height; /**< Height in lines. */
NvU32 SurfaceType;/**< Surface type, see @ref SurfaceTypes. */
NvU32 ColorFormat;/**< Surface color format, see @ref SurfaceTypes. */
NvU32 hint; /**< Allocation hint or 0, see @ref SurfaceHints. */
NvU8 *pMem; /**< Pointer to pre-allocated memory from which
to allocate the surface planes. */
NvU32 memSize; /**< Size of pre-allocated Y plane memory. */
NvU32 id; /**< User defined ID to track allocated block, debugging use */
/* Reserved for future */
/* GF_RETTYPE (* pSurfaceCallBack)
( GFRmHandle RmHandle, PGFRMSURFACE pSurface); */
/* Reserved for future */
/* PGFRMSURFACE pSurfaceShare; */
} GFRMSURFACEREQUEST, *PGFRMSURFACEREQUEST;
/** Device Info */
typedef struct _GFRMDEVICEINFO
{
NvU32 MinorRev;
NvU32 MajorRev;
NvU32 ChipID;
NvU32 Family;
} GFRMDEVICEINFO, *PGFRMDEVICEINFO;
/** @name Surface Update Flags
@anchor SurfaceUpdateFlags
@see GFRmSurfaceUpdate()
@{*/
/** GFRmSurfaceUpdate() attribute type: Update surface rotation.
The following values are valid for parameter \a data of GFRmSurfaceUpdate():
<pre>
#GF_SURFACE_ROTATE_0
#GF_SURFACE_ROTATE_90
#GF_SURFACE_ROTATE_180
#GF_SURFACE_ROTATE_270
</pre>
@see GFRmSurfaceUpdate()
*/
#define GF_SURFACE_UPDATE_ROTATE 0x00000001
/** GFRmSurfaceUpdate() attribute type: Update surface width.
Meaning of parameter \a data of GFRmSurfaceUpdate():
New surface width in pixels.
The number of bytes required for the new width must not exceed the
surface stride. It is the responsibility of the caller to ensure this.
@see GFRmSurfaceUpdate()
*/
#define GF_SURFACE_UPDATE_WIDTH 0x00000002
/** GFRmSurfaceUpdate() attribute type: Update surface height.
Meaning of parameter \a data of GFRmSurfaceUpdate():
New surface height in line.
The set height * surface stride must not exceed the memory allocated
for the surface. It is the responsibility of the caller to ensure this.
@see GFRmSurfaceUpdate()
*/
#define GF_SURFACE_UPDATE_HEIGHT 0x00000003
/** GFRmSurfaceUpdate() attribute type: Update surface width and stride.
Meaning of parameter \a data of GFRmSurfaceUpdate():
New surface width in pixels.
YStride, UStride, and VStride will be updated automatically according
to alignment requirements. Supported colour formats:
- GF_SURFACE_YUV420
@see GFRmSurfaceUpdate()
*/
#define GF_SURFACE_UPDATE_WIDTH_STRIDE 0x00000004
/*@}*/
/** @name Memory types
@anchor MemoryTypes
@see GFRMMEMORYREQUEST, GFRmMemHandleAlloc()
@{*/
/** Memory Type: Host system memory. */
#define GF_MEMORY_SYSTEM 0x01
/** Memory Type: Any GPU memory */
#define GF_MEMORY_EMBEDDED 0x02
/** Memory Type: Memory mapped memory. */
#define GF_MEMORY_MEMMAPPED 0x04
/** Memory Type: External GPU memory only. */
#define GF_MEMORY_EMBEDDED_EXT_ONLY GF_MEMORY_EMBEDDED_EXT
#define GF_MEMORY_EMBEDDED_EXT 0x08
/** Memory Type: Internal GPU memory only. */
#define GF_MEMORY_EMBEDDED_INT_ONLY GF_MEMORY_EMBEDDED_INT
#define GF_MEMORY_EMBEDDED_INT 0x10
/** Memory type: Internal or external memory with preference to internal memory. */
#define GF_MEMORY_EMBEDDED_INT_PREFERRED 0x20
/** Memory type: External or internal memory with preference to external memory. */
#define GF_MEMORY_EMBEDDED_EXT_PREFERRED 0x40
/** Memory type: Direct Read access */
#define GF_MEMORY_DIRECT_CPU_READ_ACCESS 0x80
/** Memory type: Direct Write access */
#define GF_MEMORY_DIRECT_CPU_WRITE_ACCESS 0x100
/** Memory type: Direct Read/Write access */
#define GF_MEMORY_DIRECT_CPU_ACCESS (GF_MEMORY_DIRECT_CPU_WRITE_ACCESS | GF_MEMORY_DIRECT_CPU_READ_ACCESS)
/*@}*/
/** @name Memory Share Types
@anchor MemoryShare
@see GFRMMEMORYREQUEST, GFRmMemHandleAlloc()
@{*/
/** Memory Share Flag: Internal use, used in GFRmMemInfo only. */
#define GF_MEMORY_SHARE 0x80
/*@}*/
/** @name Memory Alignment
@anchor MemoryAlignment
@see GFRMMEMORYREQUEST, GFRmMemHandleAlloc()
@{*/
/** Memory alignment types, must match log2 of alignment size. */
enum
{
GF_MEMORY_ALIGN_NONE = 0, /**< Memory Alignment: Don't care. */
GF_MEMORY_ALIGN2, /**< Memory Alignment: Aligned to 2 byte boundary. */
GF_MEMORY_ALIGN4, /**< Memory Alignment: Aligned to 4 byte boundary. */
GF_MEMORY_ALIGN8, /**< Memory Alignment: Aligned to 8 byte boundary. */
GF_MEMORY_ALIGN16, /**< Memory Alignment: Aligned to 16 byte boundary. */
GF_MEMORY_ALIGN32, /**< Memory Alignment: Aligned to 32 byte boundary. */
GF_MEMORY_ALIGN64, /**< Memory Alignment: Aligned to 64 byte boundary. */
GF_MEMORY_ALIGN128, /**< Memory Alignment: Aligned to 128 byte boundary. */
GF_MEMORY_ALIGN256, /**< Memory Alignment: Aligned to 256 byte boundary. */
GF_MEMORY_ALIGN512, /**< Memory Alignment: Aligned to 512 byte boundary. */
GF_MEMORY_ALIGN1024, /**< Memory Alignment: Aligned to 1024 byte boundary. */
GF_MEMORY_ALIGN2048, /**< Memory Alignment: Aligned to 2048 byte boundary. */
GF_MEMORY_ALIGN4096, /**< Memory Alignment: Aligned to 4096 byte boundary. */
GF_MEMORY_ALIGN_DSP = 0xFF /**< Memory Alignment: Aligned properly for DSP cacheline size. */
};
/*@}*/
/** @name Memory Allocation Hints
@anchor MemoryHints
@see GFRMMEMORYREQUEST, GFRmMemHandleAlloc()
@{*/
/* Memory Hint - Follow Surface Hint */
/** Memory Allocation Hint: Allocate from high to low addresses. */
#define GF_MEMORY_HINT_TOP_DOWN GF_SURFACE_HINT_TOP_DOWN
/** Memory Allocation Hint: Allocate from low to high addresses. */
#define GF_MEMORY_HINT_BOTTOM_UP GF_SURFACE_HINT_BOTTOM_UP
/** Memory Allocation Hint: Allocate from maximum available chunk. */
#define GF_MEMORY_HINT_MAX_CHUNK GF_SURFACE_HINT_MAX_CHUNK
/** Memory Allocation Hint: Allocate at fixed address. */
#define GF_MEMORY_HINT_FIXED (GF_MEMORY_HINT_MAX_CHUNK << 1)
/** Memory Allocation Hint: Allocate for 3D. */
#define GF_MEMORY_HINT_3D (GF_MEMORY_HINT_MAX_CHUNK << 2)
/* These options are for DRAM as extended memory. This option specifies
* bank the buffer should come from. This will avoid
* bank clobbering between two buffers that are accessed in lock
* step.
*/
/** Memory Allocation Hint: Allocate from even banks in external memory. */
#define GF_MEMORY_HINT_EVEN_BANK (GF_MEMORY_HINT_MAX_CHUNK << 3)
/** Memory Allocation Hint: Allocate from odd banks in external memory. */
#define GF_MEMORY_HINT_ODD_BANK (GF_MEMORY_HINT_MAX_CHUNK << 4)
/*@}*/
/** Memory allocation request.
@see GFRmMemHandleAlloc()
*/
typedef struct _GFRMMEMORYREQUEST
{
NvU32 length; /**< Size in bytes. */
NvU32 hint; /**< Allocation hint or 0, see @ref MemoryHints. */
struct
{
NvU16 type; /**< Memory type, see @ref MemoryTypes. */
NvU8 share; /**< Share flags or 0, see @ref MemoryShare. */
NvU8 align; /**< Alignment flags, see @ref MemoryAlignment. */
}
flag;
NvU32 id; /**< User defined ID to track allocated block, debugging use */
} GFRMMEMORYREQUEST, *PGFRMMEMORYREQUEST;
/** OS Critical Section bits 0-15 are general purpose use
bit 16-31 are for internal use */
#define GF_CRITICAL_SECTION_HW 0x00000001
/** RM internal use */
#define GF_CRITICAL_SECTION_SW2 0x00000004
/** RM internal use */
#define GF_CRITICAL_SECTION_SW4 0x00000010
/** I2C critical section */
#define GF_CRITICAL_SECTION_I2C 0x00000020
/** RM All channel lock, internal use */
#define GF_CRITICAL_SECTION_ALL_CHANNELS 0x00000040
/** Ix internal use */
#define GF_CRITICAL_SECTION_SW8 0x00000100
/** RM DSP to Host communication, internal use */
#define GF_CRITICAL_SECTION_D2H 0x00000200
/** The SHUTDOWN_DSP lock protects the race between
* UpdateDSPFreq/DSPDisable and HandleInterrupt (IST).
* (Update and DSPDisable turn off the DSP, HandleInt reads
* DSP regs)
*/
#define GF_CRITICAL_SECTION_SHUTDOWN_DSP 0x00000400
/** The DSP lock protects the race between
* AddTask and RemoveTask.
*/
#define GF_CRITICAL_SECTION_DSP 0x00000401
/** Define the ID for the kernel semaphore */
#define GF_DSP_KERNEL_SEM_ID 0x0CAFEFAD
/** Shared memory lock - used for internal purposes */
#define GF_CRITICAL_SECTION_SHM 0x00000800
/** RM Host to DSP communication, internal use */
#define GF_CRITICAL_SECTION_H2D 0x00001000
/** Rm internal use: lock for channel structures */
#define GF_CRITICAL_SECTION_CHSTRUCT 0x00004000
/** Dx internal use */
#define GF_CRITICAL_SECTION_DX 0x00008000
/** Vx internal use */
#define GF_CRITICAL_SECTION_VX 0x00000080
#ifdef PROJECT_SEC_G1
/** JxDec internal use */
#define GF_CRITICAL_SECTION_JXDEC 0x00002000
#endif
/** Rm internal use: lock for DSP messages */
#define GF_CRITICAL_SECTION_DSPMSG_MIN 0x00010000
#define GF_CRITICAL_SECTION_DSPMSG_MAX 0x20000000
/** Audio Shared Memory lock - used for multiprocess OS */
#define GF_CRITICAL_SECTION_SWAUDIO 0x10002000
/** Maximiun id */
#define GF_CRITICAL_SECTION_SWMAX 0x00010000
/** OS IRQ Callback */
typedef void (* GFRMOSIRQCALLBACK)( void *pData );
struct _GFRMCOMMONSTRUCT;
struct _GFRMENVIRONMENTVARIABLES;
struct _GFRMEXTDATASTRUCT;
/** Definition of Ix powerplane operations
*/
typedef enum _GFIX_POWERPLANE_OP_TYPE
{
GFIX_POWERPLANE_OP_ENABLE = 0,
GFIX_POWERPLANE_OP_DISABLE,
GFIX_POWERPLANE_OP_QUERY
} GFIX_POWERPLANE_OP_TYPE;
/** Configuration structure that may be passed to GFRmOpen().
See GFRmOpen() for details.
*/
typedef struct _GFRMOPENSTRUCT
{
NvU32 isFirstProcess;
NvU32 isDeviceMapped;
GF_RETTYPE retStatus; //!< Return error reason code, in case GFRmOpen() fails
/** Declare which driver HW or NULL driver to use.
This is for GFSDK compiled for NULL driver case.
*/
NvU32 useDriver;
} GFRMOPENSTRUCT;
/** @name Interface Manager Returned Functions
@{*/
/** Write a 32-bit register in the device.
@param base I/O base address
@param offset Offset of register
@param data Data to write
*/
typedef void (*GF_FUNC_WRITE_32BIT)(void * base, NvU32 offset, NvU32 data);
/** Read a 32-bit register in the device.
@param base I/O base address
@param offset Offset of register
@retval #NvU32 register value
*/
typedef NvU32 (*GF_FUNC_READ_32BIT)(void * base, NvU32 offset);
/*@}*/
/** Interface Options for Read/Write Embedded FIFO (for Jx/Mx APIs) */
#define GF_EMBFIFO_SWAP_BYTE 0x00000001
#define GF_EMBFIFO_SWAP_WORD 0x00000002
/** Interface FIFO flags */
/** Front-End FIFO */
#define GF_FIFO_FEND 0x00000001
/** GE (2D/Primary) FIFO */
#define GF_FIFO_SRC 0x00000002
/** Interface Helper macro to generate Address Pointer */
#define GFMAKEADDR(base, offset) (void *)base, offset
/** Utility Debug Flag */
#define GF_DEBUG_DEFAULT 0
/** 4th argument for GFRmOSGetTickCount */
#define GF_USEC_TICKS 0
#define GF_MSEC_TICKS 1
#define GF_SEC_TICKS 2
/** Flags for the Context manager GF_CTX_DEFAULT, GF_CTX_NEW */
#define GF_CTX_DEFAULT 1
#define GF_CTX_NEW 2
#define GF_CTX_SHARED 3
/*
########################################################################
* Function Prototypes for GFSDK Resource Manager (RM) Services
########################################################################
*/
/* Object Manager */
/** GFRmOpen - Starts Resource Manager and GFSDK.
@param RmOpenHandle Must be NULL.
@return Resource manager handle, or NULL on failure.
This must be called prior using any GFSDK component APIs and RM services.
This function can be called multiple times, for each successfull call
the application must also call GFRmClose().
If this function fails, and a pointer to an open structure is passed in
\a RmOpenHandle, the a failure reasoncode will be returned in GF_OPEN_RETTYPE::retStatus.
*/
GFRmHandle GFRmOpen(GFRMOPENSTRUCT *RmOpenHandle);
/** GFRmClose - Ends Resource Manager and GFSDK.
@param pRmHandle Ptr to RmHandle to be closed.
@retval GF_RETTYPE #GF_SUCCESS if successful.<br>
#GF_ERROR on error.<br>
All GFSDK resources will be freed related to this process.
Calls to GFRmOpen are reference counted, GFDSK will be closed only for
the last call to this function.
*/
void GFRmClose(GFRmHandle *pRmHandle);
/** GFRmCleanUp - Frees resources allocated to a terminated Resource Manager session.
@param RmProcessID RM Process ID to clean up after.
@retval GF_RETTYPE #GF_SUCCESS if successful.<br>
#GF_ERROR on error.<br>
All GFSDK resources will be freed related to this
process.
*/
GF_RETTYPE
GFRmCleanUp( GFRmHandle RmHandle, NvU32 RmProcessID );
// FIXME: ripped off from the API doc. GFRmRecover is not implemented as of
// yet - there's null implementation in GFRmObj.c.
/** GFRmRecover - Handles ESD failures.
@param RmHandle The handle to the Resource Manager.
@param option
@retval GF_RETTYPE #GF_SUCCESS if successful.<br>
#GF_ERROR on error.<br>
This function is used to recover from an ESD (electrostatic discharge)
failure. If the system software finds that the GoForce processor is not
responding, the software uses the CPU GPIO to reset the GoForce processor
and then calls this function. GFRmRecover() only calls Recover()
functions of registered components. For example, the GFDxAPI and GFGxAPI
have registered Recover() functions that can bring the GoForce processor
back from the reset to normal working mode.
*/
GF_RETTYPE
GFRmRecover( GFRmHandle RmHandle, NvU32 option );
/** GFRmGetProperty - Returns properties of RM.
@param pRmProp Caller passes ptr to GFPROPERTY that will be filled
upon return.
@retval #GF_SUCCESS if successful.
*/
GF_RETTYPE
GFRmGetProperty( GFRmHandle RmHandle,
GFPROPERTY *pRmProp );
/** GFRmSetAttribute - Sets RM attribute.
@param AttribType Attribute to get of type #GF_ATTRIBUTE_TYPE.
@param AttribData Data specific to AttribType.
@retval #GF_SUCCESS if successful.
*/
GF_RETTYPE
GFRmSetAttribute(GFRmHandle RmHandle,
GF_ATTRIBUTE_TYPE AttribType,
NvU32 AttribData);
/** GFRmGetAttribute - Gets RM attribute.
@param AttribType Attribute to get of type #GF_ATTRIBUTE_TYPE.
@param AttribData Data specific to AttribType.
See GF_ATTRIBUTE_TYPE for interpretation.
May pass input and/or output parameters.
@retval #GF_SUCCESS if successful.
*/
GF_RETTYPE
GFRmGetAttribute(GFRmHandle RmHandle,
GF_ATTRIBUTE_TYPE AttribType,
NvU32 *pAttribData);
/** Claim or release a hardware resource.
The GoForce GPU has a few hardware engines which are used by
different component API. If a component API is using that hardware
engine, then other API component should not be allowed to use that
engine. For example we have MPEG Decoder engine in the hardware which
is used by GFMxDecAPI and GFJxDecAPI components. If one of the API is
using MPEGD Engine and app/system software tries to use other engines,
it should not be allowed.
For SC4/SC5/SC10/SC12 GPU, we have following constraints:
GFMxDecAPI MPEGD, optional Auto Trigger SB
GFJxDecAPI MPEGD, optional Auto Trigger SB
Both of these component API share same engine so we should only allow
one component to be opened at a time.
GFMxEncAPI MPEGE, EPP (planar converter)
GFJxEncAPI JPEGE, EPP (planar converter)
Both of these component API share same fron-end planar converter so we
should only allow one component to be opened.
StetchBlt is represented by VxBlt(). SB has one context where auto
trigger SB can be set. Manual SB command uses same context for manual
command and then restores the auto context.
There is no need to check for manual VxBlt().
Autotrigger need checking but it is difficult to check in the VxBlt()
function.
This function only deals with Component level constraints.
Constraint checking can be enabled if GF_ATTRIB_HW_RESOURCE_CONSTRAINT.
@param RmHandle Handle to the resource manager.
@param options Action code
@param hwEngineReq Flag bitmask specifying 0 or more HW engines, see @ref HardwareResources
@retval GF_SUCCESS Hardware resource is available.
@retval GFRM_ERROR_HWRESOURCE_NOT_AVAILABLE Hardware resource is not available.
@retval GFRM_ERROR_BAD_PARAMETER Bad parameters passed
*/
GF_RETTYPE
GFRmHwResourceConstraint( GFRmHandle RmHandle,
GF_HRC_OPTIONS options,
NvU32 hwEngineReq );
/* Context Manager */
/** GFRmContextGet - Retrieves either a default or new context.
@param RmHandle Handle to the resource manager.
@param flags #GF_CTX_DEFAULT or #GF_CTX_NEW
@param pContext Pointer to the retreived context.
@retval #GF_SUCCESS on success.
@retval #GF_ERROR on error.
*/
GF_RETTYPE
GFRmContextGet( GFRmHandle RmHandle,
NvU32 flags,
GFRmChHandle *pContext);
/** GFRmChFree - Free a channel (same thing as a context).
@param hRm Resource manager handle.
@param phCh Pointer to the channel handle.
@see GFRmContextGet
*/
void GFRmChFree(GFRmHandle hRm, GFRmChHandle *phCh);
/* Component Manager */
/** GFRmComponentRegister - Register Component with Resource Manager
@param pComponent Ptr to component to be registerd.
@param RegisterState Parameter of type GF_STATE_TYPE.
Usually, GF_STATE_REGISTER is passed.
@retval #GF_SUCCESS on success.
@retval #GF_ERROR on error.
*/
GF_RETTYPE
GFRmComponentRegister( GFRmHandle RmHandle,
GFRMCOMPONENT *pComponent,
GF_STATE_TYPE RegisterState );
/** GFRmComponentGet - Gets a registered component, associated with the passed
context.
@param ComponentType Desired component type.
@param state Parameter of type #GF_STATE_TYPE.
@param pComponent Ptr to Handle to component available.
NULL if not available.
@param hCh Context Handle. Can be allocated by a call to
#GFRmContextGet function.
@retval #GF_SUCCESS on success.
@retval #GF_ERROR on error.
Depending on the requested state, a newly instantiated component or
a shared component is returned. GF_STATE_DEFAULT is the default option
for the state parameter. If the hCh passed is NULL, then a default
context is associalted with the component.
*/
GF_RETTYPE
GFRmComponentGet(GFRmHandle hRm,
NvU32 ComponentType,
GF_HANDLE *pComponent,
GF_STATE_TYPE state,
GFRmChHandle hCh);
/** GFRmComponentRelease - Releases the specified component handle.
@param hRm Handle to the resource manager.
@param phComponent Pointer to component handle to be released.
The handle pointed to by phComponent will be cleared to NULL as a side
effect of calling this function. Also, this function has no effect if
the handle pointed to by phComponent is already NULL, so it is not
necessary to check whether a component handle is NULL before releasing it.
*/
void GFRmComponentRelease(GFRmHandle hRm, GF_HANDLE *phComponent);
/* Surface Manager */
/** GFRmSurfaceAlloc - Allocate a Surface without synchronization.
@param pSurfaceReq Pointer to surface request structure #GFRMSURFACEREQUEST.
@param ppSurface Pointer to surface pointer.
@retval #GF_SUCCESS on success.
@retval #GF_ERROR on error.
@retval #GF_OUT_OF_MEMORY when low on memory.
*/
GF_RETTYPE
GFRmSurfaceAlloc( GFRmHandle RmHandle,
GFRMSURFACEREQUEST *pSurfaceReq,
PGFRMSURFACE *ppSurface );
/** GFRmSurfaceFree - Frees an allocated surface.
@param ppSurface Pointer to surface pointer.
*ppSurface is cleared to NULL.
*/
void
GFRmSurfaceFree(GFRmHandle hRm,
PGFRMSURFACE *ppSurface);
/** GFRmSurfaceQueryPrimaryInfo - Make a query on Primary Surface.
@param ppSurface Pointer to Primary surface pointer.
@param pRotate Ptr to current Rotation orientation.
@retval GF_RETTYPE #GF_SUCCESS on success.
#GF_ERROR on error.
Returned surface pointer is for quick reference only and is a
pointer to transient structure. In other words, this will not
increment the reference count as GFRmSurfaceAlloc does.
*/
GF_RETTYPE
GFRmSurfaceQueryPrimaryInfo( GFRmHandle RmHandle,
PGFRMSURFACE *ppSurface,
NvU32 *pRotate,
NvU32 subSurfaceType );
/** Update surface attributes.
@param ppSurface Pointer to Primary surface pointer.
@param type Type of attribute to update:
<table>
<tr><td>#GF_SURFACE_UPDATE_ROTATE</td><td>Set surface rotation</td></tr>
<tr><td>#GF_SURFACE_UPDATE_WIDTH </td><td>Set surface width</td></tr>
<tr><td>#GF_SURFACE_UPDATE_HEIGHT</td><td>Set surface height</td></tr>
</table>
@param data Data specific to the type.
@retval #GF_SUCCESS on success.
@retval #GF_ERROR on error.
Currently only one update flag is defined #GF_SURFACE_UPDATE_ROTATE
*/
GF_RETTYPE
GFRmSurfaceUpdate( GFRmHandle RmHandle,
PGFRMSURFACE pSurface,
NvU32 type,
NvU32 data );
/* Memory Manager */
/** Allocate a linear piece of internal memory block.
@param pMemoryReq Pointer to Memory Request struct #GFRMMEMORYREQUEST.
@param pMemHandle A Pointer to the memory handle.
@retval #GF_SUCCESS on success.
@retval #GF_ERROR on error.
*/
GF_RETTYPE
GFRmMemHandleAlloc(GFRmHandle RmHandle,
GFRMMEMORYREQUEST *pMemoryReq,
GFRmMemHandle *pMemHandle );
/** Frees an allocated internal memory block.
@param phMem A Pointer to the memory handle.
*/
void
GFRmMemHandleFree(GFRmHandle hRm,
GFRmMemHandle *phMem);
/** Current memory info. Only supports embedded memory.
@param pTotalFree Pointer to NvU32 holding total free memoory available.
@param flag Type of memory. Can be one the
#GF_MEMORY_EMBEDDED
#GF_MEMORY_EMBEDDED_EXT
#GF_MEMORY_EMBEDDED_INT
@param pMaxChunk Size of the max chunk.
@retval #GF_SUCCESS on success.
@retval #GF_ERROR on error.
GF_MEMORY_EMBEDDED returns the free memory available in both internal
and external memory.
*/
GF_RETTYPE
GFRmMemInfo (GFRmHandle RmHandle,
NvU32 *pTotalFree,
NvU32 *pMaxChunk,
NvU32 flag );
/** Get an handle for the entire internal memory. Used for debugging purposes
only.
*/
GFRmMemHandle GFRmMemGetIntMemHandle(GFRmHandle RmHandle);
/** Get an handle for the entire external memory. Used for debugging purposes
only.
*/
GFRmMemHandle GFRmMemGetExtMemHandle(GFRmHandle RmHandle);
/** Handle to offset(sc15 view of hw address) conversion.
*/
NvU32 GFRmMemGetOffset(GFRmMemHandle hMem);
/** Handle to DSP offset(DSP address address map) conversion.
*/
NvU32 GFRmMemGetDSPOffset(GFRmMemHandle hMem);
/** Handle to virtual address conversion.
Returned pointer cannot be dereferenced excpet in direct
addressing mode.
*/
void *GFRmMemGetPointer(GFRmMemHandle hMem);
/** Get the DSP address with a particular caching attribute for a given memory
handle.
*/
NvU32 GFRmMemGetUncachedDSPAddr(GFRmMemHandle hMem);
NvU32 GFRmMemGetWriteBackDSPAddr(GFRmMemHandle hMem);
NvU32 GFRmMemGetWriteThroughDSPAddr(GFRmMemHandle hMem);
/** Memory Handle reverse lookup from offset.
This can be used only for the embedded memory.
*/
GF_RETTYPE
GFRmMemOffsetToHandle(GFRmHandle RmHandle, NvU32 offset, GFRmMemHandle *MemHandle);
/** Converts offset to virtual address.
@param offset Hardware offset as seen by the SCxx chip.
@param ppMemory Pointer to Virtual address.
*/
GF_RETTYPE
GFRmMemOffsetToVirt(GFRmHandle RmHandle, NvU32 offset, void **ppMemory);
/** Converts virtual to offset (SCxx hw view)
@param offset Hardware offset SCxx view.
@param ppMemory Virtual address.
*/
GF_RETTYPE
GFRmMemVirtToOffset(GFRmHandle RmHandle, void *ppMemory, NvU32 *offset);
/** Test if the memory offset is from external memory.
Returns NV_TRUE if the offset is comming from
external memory, otherwise NV_FALSE.
*/
NvBool
GFRmIsExternalMemoryOffset(GFRmHandle RmHandle,
NvU32 offset);
/** Test if the memory handle is from external memory.
Returns NV_TRUE if the handle is comming from
external memory, otherwise NV_FALSE.
*/
NvBool
GFRmIsExternalMemoryHandle(GFRmHandle RmHandle,
GFRmMemHandle memhandle);
/** Test if the memory offset is valid.
@return NV_TRUE if valid, or NV_FALSE otherwise.
*/
NvBool GFRmIsMemoryOffsetValid(GFRmHandle hRm, NvU32 Offset);
/** Test for bufferoverflows in allocated GPU memory.
This does nothing for release builds. In GFSDK debug build
each GPU memory block will be guarded by leading and trailing
8 byte marker sequences:
<pre>
Start of block: 0x0D,0xF0,0xAD,0xDE,0x0D,0xF0,0xAD,0xDE
End of block: 0xDE,0xAD,0xFO,0xOD,0xDE,0xAD,0xFO,0xOD
</pre>
This call checks if these guard markers have been overwritten
@return Index of corrupted memory block, or -1 if all are ok.
*/
int GFRmMemEmbVerify(GFRmHandle RmHandle);
/* CPU bound memory fill functions:
These functions will use CPU cycles to write 16 to 32-bit fixed data
pattern into GPU memory. These API's will use user specified channel
apperture to access memory directly and are equipped with Lock and Unlock
routines to be thread safe.
*/
/** Fill memory with fixed data pattern on a particular channel.
Function locks and unlocks the channel automatically.
@param ChHandle User-specified channel to use.
@param memHandle GPU memory handle to write fixed 32-bit data.
@param offset Byte offset relative to memHandle block,
must be 32-bit aligned.
@param fill 32-bit fixed data pattern.
@param words Number of DWORDs to write.
*/
void
GFRmChMemFill32(GFRmChHandle ChHandle, GFRmMemHandle memHandle, NvU32 offset,
NvU32 fill, NvU32 words);
/** Fill memory with fixed data pattern on a particular channel.
Function locks and unlocks the channel automatically.
@param ChHandle User-specified channel to use.
@param memHandle GPU memory handle to write fixed 16-bit data.
@param offset Byte offset relative to memHandle block,
must be 32-bit aligned.
@param fill 16-bit fixed data pattern.
@param words Number of DWORDs to write.
*/
void
GFRmChMemFill16(GFRmChHandle ChHandle, GFRmMemHandle memHandle, NvU32 offset,
NvU16 fill, NvU32 words);
/** Save/Restore functions - These functions Save embedded memory to system memory.
* This memory can then be restored back to sys mem when required. These functions
* are used during DeepPowerDown.
*/
GF_RETTYPE GFRmSaveMemory(GFRmHandle pRm,
void *sysMemPtr,
NvU32 memSize);
GF_RETTYPE GFRmRestoreMemory(GFRmHandle pRm,
void *sysMemPtr,
NvU32 memSize);
/* Linear video memory functions:
These functions are used for transferring system memory to video memory,
filling video memory, and video memory to video memory operations. These
set of functions use the "1d" engine in hardware. All operations use
channels and will be synchronized with other commands. Optionally each
operation can be passed a flag to insert a "clear/raise/wait" sequence
which will guarantee that the operation has completed before processing
more commands in the command stream. For example, if a texture is being
downloaded, it is useful that the download be complete prior to some other
engine (3d maybe) using this memory.
Prior to using functions, the 1d engine must be enabled. Disabling
will cause the channel passed in to be idled. This is required by hardware
so that the command processors state can be updated when the 1d engine
has its clock disabled and put into reset.
*/
/** Callback prototype for GFRmChLinearSetDMACallback(). */
typedef void (*GF_FUNC_DMA_CALLBACK)(void *dstAddr, void *srcAddr, NvU32 lengthInWords);
/** Setup an DMA callback for downloading data to SRAM.
*
* This function allows for the user to to setup a DMA callback when
* downloading code to the frame buffer.
*
* The callback function should return AFTER all data has been transferred to
* the device. The downloader writes all data to the framebuffer through
* the registered frame buffer window. This window is 4KBytes in length,
* so there will be a callback once for each 4Kbytes (or less to handle alignment
* constraints).
*
* Also, it is possible for downloads to be occuring on multiple channels
* concurrently, which means that this Callback function must be able to
* handle calls from different threads, and do whatever arbitration is required.
*
* For indirect addressing modes, inside the GFSDK a semaphore will be taken
* and held for the duration of this transaction, as multiple threads cannot
* access the device concurrently when using an indirect addressing model.
*
* @param ChHandle The channel that will be used for the download (channel aperture is used)
* @param dmaCallback Pointer to the callback function that is called to do the download
*/
GF_RETTYPE
GFRmChLinearSetDMACallback(GFRmChHandle ChHandle,
GF_FUNC_DMA_CALLBACK dmaCallback);
/** Flag for GFRmChLinearSysToVidMemcpy(): use a clear/raise/wait. */
#define GF_RM_LINEAR_USE_CRW 0x01
/** Flag for GFRmChLinearSysToVidMemcpy(): don't synchronize with channel's pushbuffer. */
#define GF_RM_LINEAR_NO_PB_SYNC 0x02
/** Enable 1D engine for GFRmChLinear* functions.
*
* Call before using any GFRmChLinear* function. This enables the hardware that is
* used for these functions. Internally there is a reference count, so it is safe
* to call this multiple times.
*
* @param ChHandle Any valid channel handle should work.
* @see GFRmChLinearDisable()
*/
GF_RETTYPE
GFRmChLinearEnable(GFRmChHandle ChHandle);
/** Disable 1D engine for GFRmChLinear* functions.
*
* When the internal reference count reaches zero, the accelerator's clocks will be turned
* off to save power
*
* @param ChHandle Any valid channel should work.
* @see GFRmChLinearEnable()
*/
GF_RETTYPE
GFRmChLinearDisable(GFRmChHandle ChHandle);
/** Downloads a system memory buffer to the GPU memory buffer.
*
* The main reason for using this is that
* the copy to video memory is serialized with other operations. A typical use would be something
* like: 3d-driver issues draw commands that use a texture. 3d-driver issues a clear/raise/wait to
* know when draw is complete. 3d-driver issues a download to update the texture.
*
* @param pCtx : Current context (channel)
* @param memHandle : Handle returned from the memory allocator
* @param dstOffset : Offset from the beginning of the block referenced in memHandle
* @param pSrc : Source memory address in system memory
* @param len : Length in bytes to copy
* @param flags : Flags to optionally modify copy behavior
*
* flags can be one of:
*
* GF_RM_LINEAR_USE_CRW -- use a clear/raise/wait to make the operation finish prior to other command
* in the command stream being executed.
* GF_RM_LINEAR_NO_PB_SYNC -- This means the download does not need to be synchronous with the pushbuffer
* and the RM can optionally use different more efficient path
* than the pushbuffer.
*
* @return Returns GF_SUCCESS on success
*/
GF_RETTYPE
GFRmChLinearSysToVidMemcpy(GFRmChHandle pCtx,
GFRmMemHandle memHandle,
NvU32 dstOffset,
void *srcPtr,
NvU32 bytes,
NvU32 flags);
/** Fills a region of GPU memory with a constant value, by memory handle.
*
* @param ctx Current context (or channel)
* @param memHandle Handle to the memory to fill
* @param dstOffset Offset inside the memory handle
* @param data32 The value being replicated in memory. This value is
* interpreted differently depending on the align parameter.
* if align==4 all of data32 is used
* if align==2 lower 16-bits of data32 is used
* if align==1 lower 8-bits of data32 is used
*
* @param bytes Number of bytes to fill
* @param align must 1,2,4
* @param flags Can be 0 or GF_RM_LINEAR_USE_CRW
*/
GF_RETTYPE
GFRmChLinearVidMemFill(GFRmChHandle ctx,
GFRmMemHandle memHandle,
NvU32 dstOffset,
NvU32 data32,
NvU32 bytes,
NvU32 align,
NvU32 flags);
/** Copies memory within GPU memory, by memory handle.
*
* @param ctx The channel handle
* @param dstMemHandle memory handle returned from memalloc
* @param dstOffset Offset from the beginning of dstMemHandle
* @param srcMemhandle memory handle of the src memory
* @param srcOffset Offset from the beginning of srcMemHandle
* @param bytes Number of bytes to be copied.
* @param flags Must be 0 or GF_RM_LINEAR_USE_CRW
*
*/
GF_RETTYPE
GFRmChLinearVidMemcpy(GFRmChHandle ctx,
GFRmMemHandle dstMemHandle,
NvU32 dstOffset,
GFRmMemHandle srcMemHandle,
NvU32 srcOffset,
NvU32 bytes,
NvU32 flags);
/** @name OS Manager
@{*/
/** Enter Critical section, extended version.
@param id GF_CRITICAL_SECTION_xxx
*/
void GFRmOSEnterCSExt(GFRmHandle hRm, NvU32 id);
/** Exit Critical section, extended version.
@param id GF_CRITICAL_SECTION_xxx
*/
void GFRmOSExitCSExt(GFRmHandle hRm, NvU32 id);
/** Enter Hardware Access Critical section.
*/
void GFRmOSEnterCS(GFRmHandle hRm);
/** Exit Hardware Access Critical section.
*/
void GFRmOSExitCS(GFRmHandle hRm);
/** Waits for some number of milliseconds.
@param msec Number of milliseconds to wait.
*/
void GFRmOSWaitMSec(NvU32 msec);
/** Get the current OS tick counter.
@return Low 32 bits of millisecond counter.
*/
NvU32 GFRmGetTickCountMSec(void);
/** Get the current OS tick counter.
NOTE: This function is NOT guaranteed to exist on all
platforms. Drivers should NOT call this function; it's
meant only for benchmarking.
@return 64 bit microsecond counter.
*/
NvU64 GFRmGetTickCountUSec(void);
/** Waits for a keypress with a timeout, and returns the key.
@param timeOutMSec (NvU32) Milliseconds to wait for the keypress.
@retval (int) The code for the key, or zero if we timed out.
*/
int GFRmWaitKey(NvU32 timeOutMSec);
/*@}*/
/** @name Read/Write functions
We provide APIs to read and write GPU registers and memory, independent of
which bus addressing mode is in use (direct or indirect, 16 or 32).
WARNING: These functions are not safe in all cases.
1. They do not take into account handshake mode. With fixed timings it may
be unsafe, for example, to use GFRmMemRd/Wr32 to access external memory.
2. They do not take into account limitations on the # of address bits. On
some direct addressing platforms, not all the address bits are wired up,
so it is impossible to directly access all of memory. For example, it
may be unsafe to use GFRmMemRd/Wr32 to access external memory.
3. Some buses do not have full byte enable support. It is possible that
GFRmMemWr08, for example, may clobber the other byte in the word.
It is believed that the first two pitfalls only apply to external memory.
You can probably use these APIs safely to access internal memory, subject to
caveat (3) (i.e. you should stick to 16-bit or 32-bit writes). For external
memory, "use at your own risk."
@{*/
/** Read or write an 8-, 16-, or 32-bit register in the device. */
NvU8 GFRmRegRd08(GFRmHandle hRm, NvU32 offset);
NvU16 GFRmRegRd16(GFRmHandle hRm, NvU32 offset);
NvU32 GFRmRegRd32(GFRmHandle hRm, NvU32 offset);
void GFRmRegWr08(GFRmHandle hRm, NvU32 offset, NvU8 data);
void GFRmRegWr16(GFRmHandle hRm, NvU32 offset, NvU16 data);
void GFRmRegWr32(GFRmHandle hRm, NvU32 offset, NvU32 data);
/** Read or write 8, 16, or 32 bits of data to a given offset in a block of memory.
Offset is relative to the memory handle AND not the absolute one.
*/
NvU8 GFRmMemRd08(GFRmHandle hRm, GFRmMemHandle hMem, NvU32 offset);
NvU16 GFRmMemRd16(GFRmHandle hRm, GFRmMemHandle hMem, NvU32 offset);
NvU32 GFRmMemRd32(GFRmHandle hRm, GFRmMemHandle hMem, NvU32 offset);
void GFRmMemWr08(GFRmHandle hRm, GFRmMemHandle hMem, NvU32 offset, NvU8 data);
void GFRmMemWr16(GFRmHandle hRm, GFRmMemHandle hMem, NvU32 offset, NvU16 data);
void GFRmMemWr32(GFRmHandle hRm, GFRmMemHandle hMem, NvU32 offset, NvU32 data);
/** Read or write a region of a block of memory. Size is in bytes */
void GFRmMemRead(GFRmHandle hRm, GFRmMemHandle hMem, NvU32 offset,
void *pDst, NvU32 size);
void GFRmMemWrite(GFRmHandle hRm, GFRmMemHandle hMem, NvU32 offset,
const void *pSrc, NvU32 size);
/** Fill a block of memory with a given 8-, 16-, or 32-bit word. Size is in words, not bytes */
void GFRmMemFill08(GFRmHandle hRm, GFRmMemHandle hMem,
NvU32 offset, NvU32 size, NvU8 data);
void GFRmMemFill16(GFRmHandle hRm, GFRmMemHandle hMem,
NvU32 offset, NvU32 size, NvU16 data);
void GFRmMemFill32(GFRmHandle hRm, GFRmMemHandle hMem,
NvU32 offset, NvU32 size, NvU32 data);
/** Write to a FIFO in the chip. */
void GFRmFifoWrite(GFRmHandle hRm, const void *srcPtr,
NvU32 dstOffset, NvU32 sizeIn32bits);
/** Waits for the host to idle.
@retval GF_SUCCESS on success
@retval GF_ERROR on error
*/
GF_RETTYPE
GFRmWaitForHostIdle( GFRmHandle RmHandle );
/*@}*/
/** Dispatch DSP2Host messages.
This function can be called from an IST in response to the DSP2Host
interrupt. It will perform the following sequence:
- read the DSP2Host message from the DSP2Host registers, i.e. GFRmGetMessage()
- identify DSP task from the task ID in message parameter 0
- add the message to that task's queue
- set an event registered with that task to notify it about the new message
- clear DSP2Host interrupt register, i.e. GFRmClearDspCommInterrupt()
If the task ID from the message is unknown, the interrupt is still cleared,
but the message is ignored.
@param ChHandle Channel to use, should be the protected channel (GF_PROTECTED_CHANNEL)
@return Returns the DSP task ID the received message belonged to, or 0 if unknown
*/
NvU32 GFRmDispatchMessage(GFRmChHandle ChHandle);
NvU32 GFRmDispatchMessageDual(GFRmChHandle ChHandle, NvU32 dspModule);
/** Descriptor for circular buffer in DSP memory.
This structure is intended for shared use between DSP tasks.
If GF_RM_DSP_CBUFFER::wr == GF_RM_DSP_CBUFFER::rd, the circular buffer is empty.
If GF_RM_DSP_CBUFFER::wr != GF_RM_DSP_CBUFFER::rd, the buffer contains
(wr>=rd)?wr-rd:size+wr-rd bytes of data, starting at offset rd, wrapping on the buffer end.
*/
typedef struct _GFRM_DSP_CIRCBUFFER
{
NvU8* adr; //!< buffer address, DSP address space in GPU memory
NvU32 size; //!< Buffer size in bytes
NvU32 wr; //!< Current write offset relative to buffer address
NvU32 rd; //!< Current read offset relative to buffer address
NvU32 userData[4]; //!< User defined, specific depending on usage
} GF_RM_DSP_CIRCBUFFER;
/*
* Pins that can be used as GPIOs once the corresponding module
* has been enabled
*/
typedef enum {
/* SD PINS */
GPIO_SD_PIN_DATA0 = 1,
GPIO_SD_PIN_DATA1,
GPIO_SD_PIN_DATA2,
GPIO_SD_PIN_DATA3,
GPIO_SD_PIN_CLK,
GPIO_SD_PIN_CMD,
GPIO_SD_PIN_SDGP0,
GPIO_SD_PIN_SDGP1,
/* VI PINS */
GPIO_VI_PIN_VD0,
GPIO_VI_PIN_VD1,
GPIO_VI_PIN_VD2,
GPIO_VI_PIN_VD3,
GPIO_VI_PIN_VD4,
GPIO_VI_PIN_VD5,
GPIO_VI_PIN_VD6,
GPIO_VI_PIN_VD7,
GPIO_VI_PIN_VD8,
GPIO_VI_PIN_VD9,
GPIO_VI_PIN_VD10,
GPIO_VI_PIN_VD11,
GPIO_VI_PIN_VSCK,
GPIO_VI_PIN_VHS,
GPIO_VI_PIN_VVS,
GPIO_VI_PIN_VGP0,
GPIO_VI_PIN_VGP1,
GPIO_VI_PIN_VGP2,
GPIO_VI_PIN_VGP3,
GPIO_VI_PIN_VGP4,
GPIO_VI_PIN_VGP5,
GPIO_VI_PIN_VGP6
} GFGPIOPin;
/*
* I/O options for pins
*/
typedef enum {
GPIO_OPTION_DISABLE = 1,
GPIO_OPTION_INPUT,
GPIO_OPTION_OUTPUT
} GFGPIOOption;
/*
* Enable/Disable I/O for GPIOS
*/
typedef enum {
GPIO_MODE_DISABLE = 1,
GPIO_MODE_ENABLE
} GFGPIOMode;
/*
* Pin groups whose selects are tied together
*/
typedef enum {
GPIO_SD_PINGRP_D0_CLK_CMD = 1,
GPIO_SD_PINGRP_D1_D2
} GFGPIOPinGrp;
/*
* Pin select for GPIOS
*/
typedef enum {
GPIO_SELECT_GPIO = 1,
GPIO_SELECT_FUNC
} GFGPIOSelect;
/**
*
* Sets all the pins of a specific module to GPIO mode
*
* @param RmHandle Handle specific to the GFRm
* @param modid Module
*
* @return GF_SUCCESS on success
*
*/
GF_RETTYPE
GFRmGPIOEnable(GFRmHandle RmHandle, eGFModuleIDs modid);
/**
* Initializes the GPIO API
*
*
* @param RmHandle Handle specific to the GFRm
* @param modid Module
*
* @return GF_SUCCESS on success
*
*/
GF_RETTYPE
GFRmGPIODisable(GFRmHandle RmHandle, eGFModuleIDs modid);
/**
*
* Modifies the pin's input/output modes
*
* @param ChHandle Channel to write to modules through
* @param pin Pin to set
* @param options One of GPIO_OPTION_DISABLE (ignores mode),
* GPIO_OPTION_INPUT, GPIO_OPTION_OUTPUT
* @param mode One of GPIO_MODE_ENABLE, GPIO_MODE_DISABLE
*
* @return GF_SUCCESS on success
*
*/
GF_RETTYPE
GFRmGPIOSetPinMode(GFRmChHandle ChHandle, GFGPIOPin pin, GFGPIOOption option, GFGPIOMode mode);
/**
*
* Sets a particular pin's output select
*
* @param ChHandle Channel to write to modules through
* @param pin Pin to set
* @param select One of GPIO_SELECT_GPIO, GPIO_SELECT_FUNC
*
* @return GF_SUCCESS on success
*
*/
GF_RETTYPE
GFRmGPIOSetPinSelect(GFRmChHandle ChHandle, GFGPIOPin pin, GFGPIOSelect select);
/**
*
* Sets a particular pin group's output select
*
* @param ChHandle Channel to write to modules through
* @param group Pin group to set
* @param select One of GPIO_SELECT_GPIO, GPIO_SELECT_FUNC
*
* @return GF_SUCCESS on success
*
*/
GF_RETTYPE
GFRmGPIOSetPinGrpSelect(GFRmChHandle ChHandle, GFGPIOPinGrp group, GFGPIOSelect select);
/**
*
* Sets the status (high/low) of a pin
*
* @param ChHandle Channel to write to modules through
* @param pin Pin to set
* @param value Value to write to pin
*
*/
void
GFRmGPIOSetPin(GFRmChHandle ChHandle, GFGPIOPin pin, NvU8 value);
/**
* Gets the status (high/low) of a pin
*
* @param ChHandle Channel to write to modules through
* @param pin Pin to set
*
* @return Status (high/low) of pin
*
*/
NvU32
GFRmGPIOGetPin(GFRmChHandle ChHandle, GFGPIOPin pin);
/** @ name Bootflags
List of flags inidicating all the devices which are booted
@{*/
/** Chip is initalized in other words IxInit is called */
#define GFRM_BOOT_IXINIT 0x1
/** Display is initalized */
#define GFRM_BOOT_DXINIT 0x2
/*@}*/
/**
* Writes to some scratch register with a log of all the components which are
* initalized. GFRM_BOOT_* are passed as bootflags.
*/
GF_RETTYPE GFRmBootPostInit(GFRmHandle hRm, NvU32 bootflags);
#ifdef __cplusplus
}
#endif /* __cplusplus */
/*@}*/
/** @page pageRmAppNotes RmAPI Application Notes
@section pageRmAppNotes1 Todo
*/
#endif /* __GFRM_H__ */
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