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msm: clock-local: Consolidate definitions of clk_ops

Browse Source 
Move clk_ops_rcg and clk_ops_branch into clock-local.c and stop
exporting a handful of local clock functions to arch specific
drivers. Only expose the clk_ops structs.

This cuts down on the lines of code and discourages use of the
clock-local code outside of clock-local.c.

Change-Id: Iba248a4d11714b91e945bb1846a42924d1d4f8db
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Stephen Boyd
2012-04-10 12:12:56 -07:00
parent 94b4c83b8c
commit 409b8b431d
6 changed files with 195 additions and 298 deletions
Download Patch File Download Diff File Expand all files Collapse all files

102
arch/arm/mach-msm/clock-7x30.c
View File

@@ -157,8 +157,6 @@
.ns_val = N8(nmsb, nlsb, m, n) | SPDIV(SRC_SEL_##s, div), \
}
static struct clk_ops clk_ops_rcg_7x30;
enum vdd_dig_levels {
VDD_DIG_NONE,
VDD_DIG_LOW,
@@ -324,8 +322,6 @@ static struct pll_vote_clk pll4_clk = {
},
};
static struct clk_ops clk_ops_branch;
static struct clk_freq_tbl clk_tbl_axi[] = {
F_RAW(1, &lpxo_clk.c, 0, 0, 0, NULL),
F_END,
@@ -344,7 +340,7 @@ static struct rcg_clk glbl_root_clk = {
.set_rate = set_rate_nop,
.c = {
.dbg_name = "glbl_root_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 1),
CLK_INIT(glbl_root_clk.c),
},
@@ -1011,7 +1007,7 @@ static struct rcg_clk csi0_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "csi0_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 384000000),
CLK_INIT(csi0_clk.c),
},
@@ -1036,7 +1032,7 @@ static struct rcg_clk i2c_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "i2c_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_clk.c),
},
@@ -1056,7 +1052,7 @@ static struct rcg_clk i2c_2_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "i2c_2_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(i2c_2_clk.c),
},
@@ -1076,7 +1072,7 @@ static struct rcg_clk qup_i2c_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "qup_i2c_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(qup_i2c_clk.c),
},
@@ -1096,7 +1092,7 @@ static struct rcg_clk uart1_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "uart1_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart1_clk.c),
},
@@ -1116,7 +1112,7 @@ static struct rcg_clk uart2_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "uart2_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 19200000),
CLK_INIT(uart2_clk.c),
},
@@ -1156,7 +1152,7 @@ static struct rcg_clk uart1dm_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "uart1dm_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart1dm_clk.c),
},
@@ -1180,7 +1176,7 @@ static struct rcg_clk uart2dm_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "uart2dm_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(uart2dm_clk.c),
},
@@ -1214,7 +1210,7 @@ static struct rcg_clk emdh_clk = {
.c = {
.dbg_name = "emdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(emdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
@@ -1236,7 +1232,7 @@ static struct rcg_clk pmdh_clk = {
.c = {
.dbg_name = "pmdh_clk",
.flags = CLKFLAG_MIN | CLKFLAG_MAX,
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 445500000),
CLK_INIT(pmdh_clk.c),
.depends = &axi_li_adsp_a_clk.c,
@@ -1281,7 +1277,7 @@ static struct rcg_clk grp_2d_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "grp_2d_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_2d_clk.c),
.depends = &axi_grp_2d_clk.c,
@@ -1301,7 +1297,7 @@ static struct rcg_clk grp_3d_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "grp_3d_src_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(NOMINAL, 192000000, HIGH, 245760000),
CLK_INIT(grp_3d_src_clk.c),
.depends = &axi_li_grp_clk.c,
@@ -1370,7 +1366,7 @@ static struct rcg_clk sdc1_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "sdc1_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc1_clk.c),
},
@@ -1394,7 +1390,7 @@ static struct rcg_clk sdc3_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "sdc3_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc3_clk.c),
},
@@ -1430,7 +1426,7 @@ static struct rcg_clk sdc2_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "sdc2_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc2_clk.c),
},
@@ -1454,7 +1450,7 @@ static struct rcg_clk sdc4_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "sdc4_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 49152000),
CLK_INIT(sdc4_clk.c),
},
@@ -1489,7 +1485,7 @@ static struct rcg_clk mdp_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(mdp_clk.c),
.depends = &axi_mdp_clk.c,
@@ -1524,7 +1520,7 @@ static struct rcg_clk mdp_lcdc_pclk_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_lcdc_pclk_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 73728000),
CLK_INIT(mdp_lcdc_pclk_clk.c),
},
@@ -1567,7 +1563,7 @@ static struct rcg_clk mdp_vsync_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 24576000),
CLK_INIT(mdp_vsync_clk.c),
},
@@ -1598,7 +1594,7 @@ static struct rcg_clk mi2s_codec_rx_m_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mi2s_codec_rx_m_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_rx_m_clk.c),
},
@@ -1638,7 +1634,7 @@ static struct rcg_clk mi2s_codec_tx_m_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mi2s_codec_tx_m_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_codec_tx_m_clk.c),
},
@@ -1684,7 +1680,7 @@ static struct rcg_clk mi2s_m_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mi2s_m_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 12288000),
CLK_INIT(mi2s_m_clk.c),
},
@@ -1745,7 +1741,7 @@ static struct rcg_clk sdac_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "sdac_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 1536000),
CLK_INIT(sdac_clk.c),
},
@@ -1789,7 +1785,7 @@ static struct rcg_clk tv_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "tv_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 74250000),
CLK_INIT(tv_clk.c),
},
@@ -1881,7 +1877,7 @@ static struct rcg_clk usb_hs_src_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "usb_hs_src_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs_src_clk.c),
.depends = &axi_li_adsp_a_clk.c,
@@ -2018,7 +2014,7 @@ static struct rcg_clk jpeg_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "jpeg_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(jpeg_clk.c),
.depends = &axi_li_jpeg_clk.c,
@@ -2043,7 +2039,7 @@ static struct rcg_clk vfe_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(NOMINAL, 153600000, HIGH, 192000000),
CLK_INIT(vfe_clk.c),
.depends = &axi_li_vfe_clk.c,
@@ -2128,7 +2124,7 @@ static struct rcg_clk cam_m_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "cam_m_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 64000000),
CLK_INIT(cam_m_clk.c),
},
@@ -2163,7 +2159,7 @@ static struct rcg_clk vpe_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 153600000),
CLK_INIT(vpe_clk.c),
.depends = &axi_vpe_clk.c,
@@ -2200,7 +2196,7 @@ static struct rcg_clk mfc_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "mfc_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 170667000),
CLK_INIT(mfc_clk.c),
.depends = &axi_mfc_clk.c,
@@ -2249,7 +2245,7 @@ static struct rcg_clk spi_clk = {
.set_rate = set_rate_mnd,
.c = {
.dbg_name = "spi_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 26331429),
CLK_INIT(spi_clk.c),
},
@@ -2278,7 +2274,7 @@ static struct rcg_clk lpa_codec_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "lpa_codec_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 4),
CLK_INIT(lpa_codec_clk.c),
},
@@ -2304,7 +2300,7 @@ static struct rcg_clk mdc_clk = {
.set_rate = set_rate_nop,
.c = {
.dbg_name = "mdc_clk",
.ops = &clk_ops_rcg_7x30,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 1),
CLK_INIT(mdc_clk.c),
},
@@ -2975,6 +2971,10 @@ static void __init msm7x30_clock_pre_init(void)
int i;
uint32_t val;
clk_ops_branch.reset = soc_branch_clk_reset;
clk_ops_rcg.reset = msm7x30_clk_reset;
clk_ops_rcg.set_flags = soc_clk_set_flags;
cache_ownership();
print_ownership();
set_clock_ownership();
@@ -3015,29 +3015,3 @@ struct clock_init_data msm7x30_clock_init_data __initdata = {
.pre_init = msm7x30_clock_pre_init,
.post_init = msm7x30_clock_post_init,
};
/*
* Clock operation handler registration
*/
static struct clk_ops clk_ops_rcg_7x30 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
.auto_off = rcg_clk_disable,
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.is_enabled = rcg_clk_is_enabled,
.round_rate = rcg_clk_round_rate,
.reset = msm7x30_clk_reset,
.set_flags = soc_clk_set_flags,
.get_parent = rcg_clk_get_parent,
};
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
.auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = soc_branch_clk_reset,
.set_flags = soc_clk_set_flags,
.get_parent = branch_clk_get_parent,
};

123
arch/arm/mach-msm/clock-8960.c
View File

@@ -556,41 +556,6 @@ static struct pll_clk pll15_clk = {
},
};
static struct clk_ops clk_ops_rcg_8960 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
.enable_hwcg = rcg_clk_enable_hwcg,
.disable_hwcg = rcg_clk_disable_hwcg,
.in_hwcg_mode = rcg_clk_in_hwcg_mode,
.auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.is_enabled = rcg_clk_is_enabled,
.round_rate = rcg_clk_round_rate,
.reset = rcg_clk_reset,
.get_parent = rcg_clk_get_parent,
.set_flags = rcg_clk_set_flags,
};
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
.enable_hwcg = branch_clk_enable_hwcg,
.disable_hwcg = branch_clk_disable_hwcg,
.in_hwcg_mode = branch_clk_in_hwcg_mode,
.auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.get_parent = branch_clk_get_parent,
.handoff = branch_clk_handoff,
.set_flags = branch_clk_set_flags,
};
static struct clk_ops clk_ops_reset = {
.reset = branch_clk_reset,
};
/* AXI Interfaces */
static struct branch_clk gmem_axi_clk = {
.b = {
@@ -1238,7 +1203,7 @@ static struct branch_clk vcap_p_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1288,7 +1253,7 @@ static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1352,7 +1317,7 @@ static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1420,7 +1385,7 @@ static struct rcg_clk pdm_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
@@ -1465,7 +1430,7 @@ static struct rcg_clk prng_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
@@ -1491,7 +1456,7 @@ static struct rcg_clk prng_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, fmax_low, NOMINAL, fmax_nom), \
CLK_INIT(name.c), \
}, \
@@ -1554,7 +1519,7 @@ static struct rcg_clk tsif_ref_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tsif_ref_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 27000000, NOMINAL, 54000000),
CLK_INIT(tsif_ref_clk.c),
},
@@ -1586,7 +1551,7 @@ static struct rcg_clk tssc_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
@@ -1612,7 +1577,7 @@ static struct rcg_clk tssc_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(NOMINAL, 64000000), \
CLK_INIT(name.c), \
}, \
@@ -1658,7 +1623,7 @@ static struct rcg_clk usb_hsic_xcvr_fs_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hsic_xcvr_fs_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 60000000),
CLK_INIT(usb_hsic_xcvr_fs_clk.c),
},
@@ -1702,7 +1667,7 @@ static struct rcg_clk usb_hsic_hsic_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hsic_hsic_src_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 480000000),
CLK_INIT(usb_hsic_hsic_src_clk.c),
},
@@ -1745,7 +1710,7 @@ static struct rcg_clk usb_hsic_hsio_cal_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hsic_hsio_cal_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 10000000),
CLK_INIT(usb_hsic_hsio_cal_clk.c),
},
@@ -1779,7 +1744,7 @@ static struct branch_clk usb_phy0_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(NOMINAL, fmax_nom), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1913,7 +1878,7 @@ static struct rcg_clk ce3_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "ce3_src_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 50000000, NOMINAL, 100000000),
CLK_INIT(ce3_src_clk.c),
},
@@ -2504,7 +2469,7 @@ static struct branch_clk rpm_msg_ram_p_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000), \
CLK_INIT(name.c), \
}, \
@@ -2569,7 +2534,7 @@ static struct rcg_clk csi0_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "csi0_src_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi0_src_clk.c),
},
@@ -2625,7 +2590,7 @@ static struct rcg_clk csi1_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "csi1_src_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi1_src_clk.c),
},
@@ -2681,7 +2646,7 @@ static struct rcg_clk csi2_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "csi2_src_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csi2_src_clk.c),
},
@@ -3011,7 +2976,7 @@ static struct rcg_clk csiphy_timer_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "csiphy_timer_src_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 86000000, NOMINAL, 178000000),
CLK_INIT(csiphy_timer_src_clk.c),
},
@@ -3099,7 +3064,7 @@ static struct rcg_clk dsi1_byte_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "dsi1_byte_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
CLK_INIT(dsi1_byte_clk.c),
},
};
@@ -3123,7 +3088,7 @@ static struct rcg_clk dsi2_byte_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "dsi2_byte_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
CLK_INIT(dsi2_byte_clk.c),
},
};
@@ -3144,7 +3109,7 @@ static struct rcg_clk dsi1_esc_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "dsi1_esc_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
CLK_INIT(dsi1_esc_clk.c),
},
};
@@ -3164,7 +3129,7 @@ static struct rcg_clk dsi2_esc_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "dsi2_esc_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
CLK_INIT(dsi2_esc_clk.c),
},
};
@@ -3231,7 +3196,7 @@ static struct rcg_clk gfx2d0_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
@@ -3275,7 +3240,7 @@ static struct rcg_clk gfx2d1_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
@@ -3403,7 +3368,7 @@ static struct rcg_clk gfx3d_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 128000000, NOMINAL, 300000000,
HIGH, 400000000),
CLK_INIT(gfx3d_clk.c),
@@ -3465,7 +3430,7 @@ static struct rcg_clk vcap_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vcap_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
.depends = &vcap_axi_clk.c,
VDD_DIG_FMAX_MAP2(LOW, 100000000, NOMINAL, 200000000),
CLK_INIT(vcap_clk.c),
@@ -3540,7 +3505,7 @@ static struct rcg_clk ijpeg_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
HIGH, 320000000),
CLK_INIT(ijpeg_clk.c),
@@ -3583,7 +3548,7 @@ static struct rcg_clk jpegd_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
@@ -3660,7 +3625,7 @@ static struct rcg_clk mdp_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(mdp_clk.c),
.depends = &mdp_axi_clk.c,
@@ -3711,7 +3676,7 @@ static struct rcg_clk mdp_vsync_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
@@ -3772,7 +3737,7 @@ static struct rcg_clk rot_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
@@ -3883,7 +3848,7 @@ static struct rcg_clk tv_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
@@ -4075,7 +4040,7 @@ static struct rcg_clk vcodec_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
@@ -4121,7 +4086,7 @@ static struct rcg_clk vpe_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 76800000, NOMINAL, 160000000),
CLK_INIT(vpe_clk.c),
.depends = &vpe_axi_clk.c,
@@ -4187,7 +4152,7 @@ static struct rcg_clk vfe_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 266667000,
HIGH, 320000000),
CLK_INIT(vfe_clk.c),
@@ -4259,7 +4224,7 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -4285,7 +4250,7 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8960, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -4396,7 +4361,7 @@ static struct rcg_clk pcm_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
@@ -4422,7 +4387,7 @@ static struct rcg_clk audio_slimbus_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_8960,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
@@ -6097,10 +6062,10 @@ static void __init msm8960_clock_post_init(void)
* The halt status bits for these clocks may be incorrect at boot.
* Toggle these clocks on and off to refresh them.
*/
rcg_clk_enable(&pdm_clk.c);
rcg_clk_disable(&pdm_clk.c);
rcg_clk_enable(&tssc_clk.c);
rcg_clk_disable(&tssc_clk.c);
clk_prepare_enable(&pdm_clk.c);
clk_disable_unprepare(&pdm_clk.c);
clk_prepare_enable(&tssc_clk.c);
clk_disable_unprepare(&tssc_clk.c);
clk_prepare_enable(&usb_hsic_hsic_clk.c);
clk_disable_unprepare(&usb_hsic_hsic_clk.c);

92
arch/arm/mach-msm/clock-8x60.c
View File

@@ -431,34 +431,6 @@ static void set_rate_tv(struct rcg_clk *clk, struct clk_freq_tbl *nf)
writel_relaxed(pll_mode, MM_PLL2_MODE_REG);
}
static struct clk_ops clk_ops_rcg_8x60 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
.auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.is_enabled = rcg_clk_is_enabled,
.round_rate = rcg_clk_round_rate,
.reset = rcg_clk_reset,
.get_parent = rcg_clk_get_parent,
.set_flags = rcg_clk_set_flags,
};
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
.auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.get_parent = branch_clk_get_parent,
.set_flags = branch_clk_set_flags,
};
static struct clk_ops clk_ops_reset = {
.reset = branch_clk_reset,
};
/*
* Clock Descriptions
*/
@@ -965,7 +937,7 @@ static struct branch_clk vpe_p_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(LOW, 27000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1010,7 +982,7 @@ static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1074,7 +1046,7 @@ static CLK_GSBI_UART(gsbi12_uart, 12, CLK_HALT_CFPB_STATEC_REG, 13);
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1142,7 +1114,7 @@ static struct rcg_clk pdm_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(pdm_clk.c),
},
@@ -1185,7 +1157,7 @@ static struct rcg_clk prng_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
@@ -1211,7 +1183,7 @@ static struct rcg_clk prng_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 25000000, NOMINAL, 50000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -1271,7 +1243,7 @@ static struct rcg_clk tsif_ref_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tsif_ref_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
CLK_INIT(tsif_ref_clk.c),
},
};
@@ -1302,7 +1274,7 @@ static struct rcg_clk tssc_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tssc_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(tssc_clk.c),
},
@@ -1340,7 +1312,7 @@ static struct rcg_clk usb_hs1_xcvr_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
@@ -1374,7 +1346,7 @@ static struct branch_clk usb_phy0_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(NOMINAL, 60000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -2001,7 +1973,7 @@ static struct rcg_clk cam_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "cam_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 64000000, NOMINAL, 128000000),
CLK_INIT(cam_clk.c),
},
@@ -2033,7 +2005,7 @@ static struct rcg_clk csi_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "csi_src_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 192000000, NOMINAL, 384000000),
CLK_INIT(csi_src_clk.c),
},
@@ -2107,7 +2079,7 @@ static struct rcg_clk dsi_byte_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "dsi_byte_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
CLK_INIT(dsi_byte_clk.c),
},
};
@@ -2188,7 +2160,7 @@ static struct rcg_clk gfx2d0_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx2d0_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(gfx2d0_clk.c),
@@ -2232,7 +2204,7 @@ static struct rcg_clk gfx2d1_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx2d1_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(gfx2d1_clk.c),
@@ -2303,7 +2275,7 @@ static struct rcg_clk gfx3d_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "gfx3d_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 96000000, NOMINAL, 200000000,
HIGH, 320000000),
CLK_INIT(gfx3d_clk.c),
@@ -2355,7 +2327,7 @@ static struct rcg_clk ijpeg_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "ijpeg_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 110000000, NOMINAL, 228571000),
CLK_INIT(ijpeg_clk.c),
.depends = &ijpeg_axi_clk.c,
@@ -2397,7 +2369,7 @@ static struct rcg_clk jpegd_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "jpegd_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 96000000, NOMINAL, 200000000),
CLK_INIT(jpegd_clk.c),
.depends = &jpegd_axi_clk.c,
@@ -2468,7 +2440,7 @@ static struct rcg_clk mdp_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 85330000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(mdp_clk.c),
@@ -2503,7 +2475,7 @@ static struct rcg_clk mdp_vsync_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "mdp_vsync_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 27000000),
CLK_INIT(mdp_vsync_clk.c),
},
@@ -2555,7 +2527,7 @@ static struct rcg_clk pixel_mdp_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pixel_mdp_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 85333000, NOMINAL, 170000000),
CLK_INIT(pixel_mdp_clk.c),
},
@@ -2630,7 +2602,7 @@ static struct rcg_clk rot_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "rot_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 80000000, NOMINAL, 160000000),
CLK_INIT(rot_clk.c),
.depends = &rot_axi_clk.c,
@@ -2682,7 +2654,7 @@ static struct rcg_clk tv_src_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "tv_src_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 27030000, NOMINAL, 149000000),
CLK_INIT(tv_src_clk.c),
},
@@ -2813,7 +2785,7 @@ static struct rcg_clk vcodec_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vcodec_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 200000000,
HIGH, 228571000),
CLK_INIT(vcodec_clk.c),
@@ -2860,7 +2832,7 @@ static struct rcg_clk vpe_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vpe_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 76800000, NOMINAL, 160000000,
HIGH, 200000000),
CLK_INIT(vpe_clk.c),
@@ -2919,7 +2891,7 @@ static struct rcg_clk vfe_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "vfe_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 110000000, NOMINAL, 228570000,
HIGH, 266667000),
CLK_INIT(vfe_clk.c),
@@ -3007,7 +2979,7 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_8x60, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(LOW, 24576000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -3099,7 +3071,7 @@ static struct rcg_clk pcm_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_8x60,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 24580000),
CLK_INIT(pcm_clk.c),
},
@@ -3843,10 +3815,10 @@ static void __init msm8660_clock_post_init(void)
/* The halt status bits for PDM and TSSC may be incorrect at boot.
* Toggle these clocks on and off to refresh them. */
rcg_clk_enable(&pdm_clk.c);
rcg_clk_disable(&pdm_clk.c);
rcg_clk_enable(&tssc_clk.c);
rcg_clk_disable(&tssc_clk.c);
clk_prepare_enable(&pdm_clk.c);
clk_disable_unprepare(&pdm_clk.c);
clk_prepare_enable(&tssc_clk.c);
clk_disable_unprepare(&tssc_clk.c);
}
static int __init msm8660_clock_late_init(void)

63
arch/arm/mach-msm/clock-9615.c
View File

@@ -366,35 +366,6 @@ static struct pll_vote_clk pll14_clk = {
},
};
static struct clk_ops clk_ops_rcg_9615 = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
.auto_off = rcg_clk_disable,
.enable_hwcg = rcg_clk_enable_hwcg,
.disable_hwcg = rcg_clk_disable_hwcg,
.in_hwcg_mode = rcg_clk_in_hwcg_mode,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.is_enabled = rcg_clk_is_enabled,
.round_rate = rcg_clk_round_rate,
.reset = rcg_clk_reset,
.get_parent = rcg_clk_get_parent,
};
static struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
.auto_off = branch_clk_disable,
.enable_hwcg = branch_clk_enable_hwcg,
.disable_hwcg = branch_clk_disable_hwcg,
.in_hwcg_mode = branch_clk_in_hwcg_mode,
.handoff = branch_clk_handoff,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.get_parent = branch_clk_get_parent,
};
/*
* Peripheral Clocks
*/
@@ -416,7 +387,7 @@ static struct clk_ops clk_ops_branch = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP1(LOW, 27000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -459,7 +430,7 @@ static CLK_GP(gp2, 2, CLK_HALT_SFPB_MISC_STATE_REG, 5);
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 64000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -515,7 +486,7 @@ static CLK_GSBI_UART(gsbi5_uart, 5, CLK_HALT_CFPB_STATEB_REG, 22);
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 24000000, NOMINAL, 52000000), \
CLK_INIT(i##_clk.c), \
}, \
@@ -575,7 +546,7 @@ static struct rcg_clk pdm_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pdm_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 19200000),
CLK_INIT(pdm_clk.c),
},
@@ -620,7 +591,7 @@ static struct rcg_clk prng_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "prng_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP2(LOW, 32000000, NOMINAL, 65000000),
CLK_INIT(prng_clk.c),
},
@@ -646,7 +617,7 @@ static struct rcg_clk prng_clk = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #name, \
.ops = &clk_ops_rcg_9615, \
.ops = &clk_ops_rcg, \
VDD_DIG_FMAX_MAP2(LOW, 26000000, NOMINAL, 52000000), \
CLK_INIT(name.c), \
}, \
@@ -714,7 +685,7 @@ static struct rcg_clk usb_hs1_xcvr_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hs1_xcvr_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_xcvr_clk.c),
},
@@ -739,7 +710,7 @@ static struct rcg_clk usb_hs1_sys_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hs1_sys_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(NOMINAL, 60000000),
CLK_INIT(usb_hs1_sys_clk.c),
},
@@ -764,7 +735,7 @@ static struct rcg_clk usb_hsic_xcvr_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hsic_xcvr_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 60000000),
CLK_INIT(usb_hsic_xcvr_clk.c),
},
@@ -789,7 +760,7 @@ static struct rcg_clk usb_hsic_sys_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hsic_sys_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 64000000),
CLK_INIT(usb_hsic_sys_clk.c),
},
@@ -818,7 +789,7 @@ static struct rcg_clk usb_hsic_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "usb_hsic_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 480000000),
CLK_INIT(usb_hsic_clk.c),
},
@@ -1155,7 +1126,7 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
.ops = &clk_ops_rcg, \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -1180,7 +1151,7 @@ static struct clk_freq_tbl clk_tbl_aif_osr[] = {
.current_freq = &rcg_dummy_freq, \
.c = { \
.dbg_name = #i "_clk", \
.ops = &clk_ops_rcg_9615, \
.ops = &clk_ops_rcg, \
CLK_INIT(i##_clk.c), \
}, \
}
@@ -1290,7 +1261,7 @@ static struct rcg_clk pcm_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "pcm_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(pcm_clk.c),
},
@@ -1316,7 +1287,7 @@ static struct rcg_clk audio_slimbus_clk = {
.current_freq = &rcg_dummy_freq,
.c = {
.dbg_name = "audio_slimbus_clk",
.ops = &clk_ops_rcg_9615,
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP1(LOW, 24576000),
CLK_INIT(audio_slimbus_clk.c),
},
@@ -1858,8 +1829,8 @@ static void __init msm9615_clock_post_init(void)
* The halt status bits for PDM may be incorrect at boot.
* Toggle these clocks on and off to refresh them.
*/
rcg_clk_enable(&pdm_clk.c);
rcg_clk_disable(&pdm_clk.c);
clk_prepare_enable(&pdm_clk.c);
clk_disable_unprepare(&pdm_clk.c);
}
static int __init msm9615_clock_late_init(void)

83
arch/arm/mach-msm/clock-local.c
View File

@@ -268,7 +268,7 @@ static int branch_clk_is_halted(const struct branch *clk)
return invert ? !status_bit : status_bit;
}
int branch_in_hwcg_mode(const struct branch *b)
static int branch_in_hwcg_mode(const struct branch *b)
{
if (!b->hwcg_mask)
return 0;
@@ -420,7 +420,7 @@ static void __rcg_clk_disable_reg(struct rcg_clk *clk)
}
/* Enable a rate-settable clock. */
int rcg_clk_enable(struct clk *c)
static int rcg_clk_enable(struct clk *c)
{
unsigned long flags;
struct rcg_clk *clk = to_rcg_clk(c);
@@ -434,7 +434,7 @@ int rcg_clk_enable(struct clk *c)
}
/* Disable a rate-settable clock. */
void rcg_clk_disable(struct clk *c)
static void rcg_clk_disable(struct clk *c)
{
unsigned long flags;
struct rcg_clk *clk = to_rcg_clk(c);
@@ -450,7 +450,7 @@ void rcg_clk_disable(struct clk *c)
*/
/* Set a clock to an exact rate. */
int rcg_clk_set_rate(struct clk *c, unsigned long rate)
static int rcg_clk_set_rate(struct clk *c, unsigned long rate)
{
struct rcg_clk *clk = to_rcg_clk(c);
struct clk_freq_tbl *nf, *cf;
@@ -527,13 +527,13 @@ int rcg_clk_set_rate(struct clk *c, unsigned long rate)
}
/* Check if a clock is currently enabled. */
int rcg_clk_is_enabled(struct clk *clk)
static int rcg_clk_is_enabled(struct clk *clk)
{
return to_rcg_clk(clk)->enabled;
}
/* Return a supported rate that's at least the specified rate. */
long rcg_clk_round_rate(struct clk *c, unsigned long rate)
static long rcg_clk_round_rate(struct clk *c, unsigned long rate)
{
struct rcg_clk *clk = to_rcg_clk(c);
struct clk_freq_tbl *f;
@@ -546,7 +546,7 @@ long rcg_clk_round_rate(struct clk *c, unsigned long rate)
}
/* Return the nth supported frequency for a given clock. */
int rcg_clk_list_rate(struct clk *c, unsigned n)
static int rcg_clk_list_rate(struct clk *c, unsigned n)
{
struct rcg_clk *clk = to_rcg_clk(c);
@@ -556,7 +556,7 @@ int rcg_clk_list_rate(struct clk *c, unsigned n)
return (clk->freq_tbl + n)->freq_hz;
}
struct clk *rcg_clk_get_parent(struct clk *clk)
static struct clk *rcg_clk_get_parent(struct clk *clk)
{
return to_rcg_clk(clk)->current_freq->src_clk;
}
@@ -575,13 +575,13 @@ enum handoff branch_handoff(struct branch *clk, struct clk *c)
return HANDOFF_DISABLED_CLK;
}
enum handoff branch_clk_handoff(struct clk *c)
static enum handoff branch_clk_handoff(struct clk *c)
{
struct branch_clk *clk = to_branch_clk(c);
return branch_handoff(&clk->b, &clk->c);
}
enum handoff rcg_clk_handoff(struct clk *c)
static enum handoff rcg_clk_handoff(struct clk *c)
{
struct rcg_clk *clk = to_rcg_clk(c);
uint32_t ctl_val, ns_val, md_val, ns_mask;
@@ -641,7 +641,7 @@ struct fixed_clk gnd_clk = {
struct clk_ops clk_ops_measure = {
};
int branch_clk_enable(struct clk *clk)
static int branch_clk_enable(struct clk *clk)
{
unsigned long flags;
struct branch_clk *branch = to_branch_clk(clk);
@@ -654,7 +654,7 @@ int branch_clk_enable(struct clk *clk)
return 0;
}
void branch_clk_disable(struct clk *clk)
static void branch_clk_disable(struct clk *clk)
{
unsigned long flags;
struct branch_clk *branch = to_branch_clk(clk);
@@ -665,13 +665,13 @@ void branch_clk_disable(struct clk *clk)
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
struct clk *branch_clk_get_parent(struct clk *clk)
static struct clk *branch_clk_get_parent(struct clk *clk)
{
struct branch_clk *branch = to_branch_clk(clk);
return branch->parent;
}
int branch_clk_is_enabled(struct clk *clk)
static int branch_clk_is_enabled(struct clk *clk)
{
struct branch_clk *branch = to_branch_clk(clk);
return branch->enabled;
@@ -701,13 +701,13 @@ static void branch_disable_hwcg(struct branch *b)
spin_unlock_irqrestore(&local_clock_reg_lock, flags);
}
void branch_clk_enable_hwcg(struct clk *clk)
static void branch_clk_enable_hwcg(struct clk *clk)
{
struct branch_clk *branch = to_branch_clk(clk);
branch_enable_hwcg(&branch->b);
}
void branch_clk_disable_hwcg(struct clk *clk)
static void branch_clk_disable_hwcg(struct clk *clk)
{
struct branch_clk *branch = to_branch_clk(clk);
branch_disable_hwcg(&branch->b);
@@ -740,36 +740,36 @@ static int branch_set_flags(struct branch *b, unsigned flags)
return ret;
}
int branch_clk_set_flags(struct clk *clk, unsigned flags)
static int branch_clk_set_flags(struct clk *clk, unsigned flags)
{
return branch_set_flags(&to_branch_clk(clk)->b, flags);
}
int branch_clk_in_hwcg_mode(struct clk *c)
static int branch_clk_in_hwcg_mode(struct clk *c)
{
struct branch_clk *clk = to_branch_clk(c);
return branch_in_hwcg_mode(&clk->b);
}
void rcg_clk_enable_hwcg(struct clk *clk)
static void rcg_clk_enable_hwcg(struct clk *clk)
{
struct rcg_clk *rcg = to_rcg_clk(clk);
branch_enable_hwcg(&rcg->b);
}
void rcg_clk_disable_hwcg(struct clk *clk)
static void rcg_clk_disable_hwcg(struct clk *clk)
{
struct rcg_clk *rcg = to_rcg_clk(clk);
branch_disable_hwcg(&rcg->b);
}
int rcg_clk_in_hwcg_mode(struct clk *c)
static int rcg_clk_in_hwcg_mode(struct clk *c)
{
struct rcg_clk *clk = to_rcg_clk(c);
return branch_in_hwcg_mode(&clk->b);
}
int rcg_clk_set_flags(struct clk *clk, unsigned flags)
static int rcg_clk_set_flags(struct clk *clk, unsigned flags)
{
return branch_set_flags(&to_rcg_clk(clk)->b, flags);
}
@@ -811,16 +811,51 @@ int branch_reset(struct branch *b, enum clk_reset_action action)
return ret;
}
int branch_clk_reset(struct clk *clk, enum clk_reset_action action)
static int branch_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_branch_clk(clk)->b, action);
}
int rcg_clk_reset(struct clk *clk, enum clk_reset_action action)
struct clk_ops clk_ops_branch = {
.enable = branch_clk_enable,
.disable = branch_clk_disable,
.enable_hwcg = branch_clk_enable_hwcg,
.disable_hwcg = branch_clk_disable_hwcg,
.in_hwcg_mode = branch_clk_in_hwcg_mode,
.auto_off = branch_clk_disable,
.is_enabled = branch_clk_is_enabled,
.reset = branch_clk_reset,
.get_parent = branch_clk_get_parent,
.handoff = branch_clk_handoff,
.set_flags = branch_clk_set_flags,
};
struct clk_ops clk_ops_reset = {
.reset = branch_clk_reset,
};
static int rcg_clk_reset(struct clk *clk, enum clk_reset_action action)
{
return branch_reset(&to_rcg_clk(clk)->b, action);
}
struct clk_ops clk_ops_rcg = {
.enable = rcg_clk_enable,
.disable = rcg_clk_disable,
.enable_hwcg = rcg_clk_enable_hwcg,
.disable_hwcg = rcg_clk_disable_hwcg,
.in_hwcg_mode = rcg_clk_in_hwcg_mode,
.auto_off = rcg_clk_disable,
.handoff = rcg_clk_handoff,
.set_rate = rcg_clk_set_rate,
.list_rate = rcg_clk_list_rate,
.is_enabled = rcg_clk_is_enabled,
.round_rate = rcg_clk_round_rate,
.reset = rcg_clk_reset,
.get_parent = rcg_clk_get_parent,
.set_flags = rcg_clk_set_flags,
};
static int cdiv_clk_enable(struct clk *c)
{
unsigned long flags;

30
arch/arm/mach-msm/clock-local.h
View File

@@ -152,12 +152,13 @@ struct branch {
const u32 retain_mask;
};
extern struct clk_ops clk_ops_branch;
extern struct clk_ops clk_ops_reset;
int branch_reset(struct branch *b, enum clk_reset_action action);
void __branch_clk_enable_reg(const struct branch *clk, const char *name);
u32 __branch_clk_disable_reg(const struct branch *clk, const char *name);
enum handoff branch_clk_handoff(struct clk *c);
enum handoff branch_handoff(struct branch *clk, struct clk *c);
int branch_clk_set_flags(struct clk *clk, unsigned flags);
/*
* Generic clock-definition struct and macros
@@ -187,21 +188,9 @@ static inline struct rcg_clk *to_rcg_clk(struct clk *clk)
return container_of(clk, struct rcg_clk, c);
}
extern struct clk_freq_tbl rcg_dummy_freq;
extern struct clk_ops clk_ops_rcg;
int rcg_clk_enable(struct clk *clk);
void rcg_clk_disable(struct clk *clk);
int rcg_clk_set_rate(struct clk *clk, unsigned long rate);
int rcg_clk_list_rate(struct clk *clk, unsigned n);
int rcg_clk_is_enabled(struct clk *clk);
long rcg_clk_round_rate(struct clk *clk, unsigned long rate);
struct clk *rcg_clk_get_parent(struct clk *c);
enum handoff rcg_clk_handoff(struct clk *c);
int rcg_clk_reset(struct clk *clk, enum clk_reset_action action);
void rcg_clk_enable_hwcg(struct clk *clk);
void rcg_clk_disable_hwcg(struct clk *clk);
int rcg_clk_in_hwcg_mode(struct clk *c);
int rcg_clk_set_flags(struct clk *clk, unsigned flags);
extern struct clk_freq_tbl rcg_dummy_freq;
/**
* struct cdiv_clk - integer divider clock with external source selection
@@ -261,15 +250,6 @@ static inline struct branch_clk *to_branch_clk(struct clk *clk)
return container_of(clk, struct branch_clk, c);
}
int branch_clk_enable(struct clk *clk);
void branch_clk_disable(struct clk *clk);
struct clk *branch_clk_get_parent(struct clk *clk);
int branch_clk_is_enabled(struct clk *clk);
int branch_clk_reset(struct clk *c, enum clk_reset_action action);
void branch_clk_enable_hwcg(struct clk *clk);
void branch_clk_disable_hwcg(struct clk *clk);
int branch_clk_in_hwcg_mode(struct clk *c);
/**
* struct measure_clk - for rate measurement debug use
* @sample_ticks: sample period in reference clock ticks