crypto: Add bus scaling request.

Add bus bandwidth request in crypto driver modules.
Add bus scaling request information to platform data files.
Currently the support for bandwidth request is enabled and tested on
msm8960 only.

Change-Id: I77edb827b1633218405cecf3a494c13b7b982c05
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>

arch/arm/mach-msm/board-8064.c

@@ -333,6 +333,7 @@ static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	.bus_scale_table = NULL,
 };
 
 static struct platform_device qcrypto_device = {
@@ -355,6 +356,7 @@ static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	.bus_scale_table = NULL,
 };
 
 static struct platform_device qcedev_device = {

arch/arm/mach-msm/board-8960.c

@@ -605,6 +605,55 @@ static struct platform_device msm_device_wcnss_wlan = {
 #define QCE_SHARE_CE_RESOURCE	1
 #define QCE_CE_SHARED		0
 
+/* Begin Bus scaling definitions */
+static struct msm_bus_vectors crypto_hw_init_vectors[] = {
+	{
+		.src = MSM_BUS_MASTER_ADM_PORT0,
+		.dst = MSM_BUS_SLAVE_EBI_CH0,
+		.ab = 0,
+		.ib = 0,
+	},
+	{
+		.src = MSM_BUS_MASTER_ADM_PORT1,
+		.dst = MSM_BUS_SLAVE_GSBI1_UART,
+		.ab = 0,
+		.ib = 0,
+	},
+};
+
+static struct msm_bus_vectors crypto_hw_active_vectors[] = {
+	{
+		.src = MSM_BUS_MASTER_ADM_PORT0,
+		.dst = MSM_BUS_SLAVE_EBI_CH0,
+		.ab = 70000000UL,
+		.ib = 70000000UL,
+	},
+	{
+		.src = MSM_BUS_MASTER_ADM_PORT1,
+		.dst = MSM_BUS_SLAVE_GSBI1_UART,
+		.ab = 2480000000UL,
+		.ib = 2480000000UL,
+	},
+};
+
+static struct msm_bus_paths crypto_hw_bus_scale_usecases[] = {
+	{
+		ARRAY_SIZE(crypto_hw_init_vectors),
+		crypto_hw_init_vectors,
+	},
+	{
+		ARRAY_SIZE(crypto_hw_active_vectors),
+		crypto_hw_active_vectors,
+	},
+};
+
+static struct msm_bus_scale_pdata crypto_hw_bus_scale_pdata = {
+		crypto_hw_bus_scale_usecases,
+		ARRAY_SIZE(crypto_hw_bus_scale_usecases),
+		.name = "cryptohw",
+};
+/* End Bus Scaling Definitions*/
+
 static struct resource qcrypto_resources[] = {
 	[0] = {
 		.start = QCE_0_BASE,
@@ -667,6 +716,7 @@ static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	.bus_scale_table = &crypto_hw_bus_scale_pdata,
 };
 
 static struct platform_device qcrypto_device = {
@@ -689,6 +739,7 @@ static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	.bus_scale_table = &crypto_hw_bus_scale_pdata,
 };
 
 static struct platform_device qcedev_device = {

arch/arm/mach-msm/board-fsm9xxx.c

@@ -696,6 +696,7 @@ static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
 	.shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_NO_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_NO_SHA_HMAC_SUPPORT,
+	.bus_scale_table = NULL,
 };
 
 struct platform_device qcrypto_device = {
@@ -746,6 +747,7 @@ static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
 	.shared_ce_resource = QCE_NO_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_NO_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_NO_SHA_HMAC_SUPPORT,
+	.bus_scale_table = NULL,
 };
 
 static struct platform_device qcedev_device = {

arch/arm/mach-msm/board-msm7x30.c

@@ -3862,6 +3862,8 @@ static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	/* Bus Scaling declaration*/
+	.bus_scale_table = NULL,
 };
 
 static struct platform_device qcrypto_device = {
@@ -3884,6 +3886,8 @@ static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	/* Bus Scaling declaration*/
+	.bus_scale_table = NULL,
 };
 static struct platform_device qcedev_device = {
 	.name		= "qce",

arch/arm/mach-msm/board-msm8x60.c

@@ -602,6 +602,7 @@ static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	.bus_scale_table = NULL,
 };
 
 static struct platform_device qcrypto_device = {
@@ -624,6 +625,7 @@ static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	.bus_scale_table = NULL,
 };
 
 static struct platform_device qcedev_device = {

arch/arm/mach-msm/devices-9615.c

@@ -480,6 +480,7 @@ static struct msm_ce_hw_support qcrypto_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	.bus_scale_table = NULL,
 };
 
 struct platform_device msm9615_qcrypto_device = {
@@ -502,6 +503,7 @@ static struct msm_ce_hw_support qcedev_ce_hw_suppport = {
 	.shared_ce_resource = QCE_SHARE_CE_RESOURCE,
 	.hw_key_support = QCE_HW_KEY_SUPPORT,
 	.sha_hmac = QCE_SHA_HMAC_SUPPORT,
+	.bus_scale_table = NULL,
 };
 
 struct platform_device msm9615_qcedev_device = {

drivers/crypto/msm/qcedev.c

@@ -31,6 +31,7 @@
 #include <crypto/hash.h>
 #include <linux/platform_data/qcom_crypto_device.h>
 #include <mach/scm.h>
+#include <mach/msm_bus.h>
 #include <linux/qcedev.h>
 #include "qce.h"
 
@@ -97,7 +98,7 @@ struct qcedev_async_req {
 };
 
 static DEFINE_MUTEX(send_cmd_lock);
-
+static DEFINE_MUTEX(sent_bw_req);
 /**********************************************************************
  * Register ourselves as a misc device to be able to access the dev driver
  * from userspace. */
@@ -111,9 +112,13 @@ struct qcedev_control{
 	struct msm_ce_hw_support platform_support;
 
 	uint32_t ce_lock_count;
+	uint32_t high_bw_req_count;
+
 	/* CE features/algorithms supported by HW engine*/
 	struct ce_hw_support ce_support;
 
+	uint32_t  bus_scale_handle;
+
 	/* misc device */
 	struct miscdevice miscdevice;
 
@@ -167,6 +172,29 @@ static int qcedev_scm_cmd(int resource, int cmd, int *response)
 #endif
 }
 
+static int qcedev_ce_high_bw_req(struct qcedev_control *podev,
+							bool high_bw_req)
+{
+	int ret = 0;
+
+	mutex_lock(&sent_bw_req);
+	if (high_bw_req) {
+		if (podev->high_bw_req_count == 0)
+			msm_bus_scale_client_update_request(
+					podev->bus_scale_handle, 1);
+		podev->high_bw_req_count++;
+	} else {
+		if (podev->high_bw_req_count == 1)
+			msm_bus_scale_client_update_request(
+					podev->bus_scale_handle, 0);
+		podev->high_bw_req_count--;
+	}
+	mutex_unlock(&sent_bw_req);
+
+	return ret;
+}
+
+
 static int qcedev_unlock_ce(struct qcedev_control *podev)
 {
 	int ret = 0;
@@ -302,7 +330,8 @@ static int qcedev_open(struct inode *inode, struct file *file)
 
 	handle->cntl = podev;
 	file->private_data = handle;
-
+	if (podev->platform_support.bus_scale_table != NULL)
+		return qcedev_ce_high_bw_req(podev, true);
 	return 0;
 }
 
@@ -319,7 +348,8 @@ static int qcedev_release(struct inode *inode, struct file *file)
 	}
 	kzfree(handle);
 	file->private_data = NULL;
-
+	if (podev->platform_support.bus_scale_table != NULL)
+		return qcedev_ce_high_bw_req(podev, false);
 	return 0;
 }
 
@@ -1992,7 +2022,10 @@ static int qcedev_probe(struct platform_device *pdev)
 				platform_support->shared_ce_resource;
 	podev->platform_support.hw_key_support =
 				platform_support->hw_key_support;
+	podev->platform_support.bus_scale_table =
+				platform_support->bus_scale_table;
 	podev->ce_lock_count = 0;
+	podev->high_bw_req_count = 0;
 	INIT_LIST_HEAD(&podev->ready_commands);
 	podev->active_command = NULL;
 
@@ -2011,10 +2044,28 @@ static int qcedev_probe(struct platform_device *pdev)
 	podev->pdev = pdev;
 	platform_set_drvdata(pdev, podev);
 	qce_hw_support(podev->qce, &podev->ce_support);
+
+	if (podev->platform_support.bus_scale_table != NULL) {
+		podev->bus_scale_handle =
+			msm_bus_scale_register_client(
+				(struct msm_bus_scale_pdata *)
+				podev->platform_support.bus_scale_table);
+		if (!podev->bus_scale_handle) {
+			printk(KERN_ERR "%s not able to get bus scale\n",
+								__func__);
+			rc =  -ENOMEM;
+			goto err;
+		}
+	}
 	rc = misc_register(&podev->miscdevice);
 
 	if (rc >= 0)
 		return 0;
+	else
+		if (podev->platform_support.bus_scale_table != NULL)
+			msm_bus_scale_unregister_client(
+						podev->bus_scale_handle);
+err:
 
 	if (handle)
 		qce_close(handle);
@@ -2034,6 +2085,9 @@ static int qcedev_remove(struct platform_device *pdev)
 	if (podev->qce)
 		qce_close(podev->qce);
 
+	if (podev->platform_support.bus_scale_table != NULL)
+		msm_bus_scale_unregister_client(podev->bus_scale_handle);
+
 	if (podev->miscdevice.minor != MISC_DYNAMIC_MINOR)
 		misc_deregister(&podev->miscdevice);
 	tasklet_kill(&podev->done_tasklet);
@@ -2164,7 +2218,7 @@ static void qcedev_exit(void)
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
 MODULE_DESCRIPTION("Qualcomm DEV Crypto driver");
-MODULE_VERSION("1.24");
+MODULE_VERSION("1.25");
 
 module_init(qcedev_init);
 module_exit(qcedev_exit);

drivers/crypto/msm/qcrypto.c

@@ -37,6 +37,7 @@
 
 #include <mach/scm.h>
 #include <linux/platform_data/qcom_crypto_device.h>
+#include <mach/msm_bus.h>
 #include "qce.h"
 
 
@@ -80,6 +81,8 @@ struct crypto_priv {
 
 	/* CE features/algorithms supported by HW engine*/
 	struct ce_hw_support ce_support;
+
+	uint32_t  bus_scale_handle;
 	/* the lock protects queue and req*/
 	spinlock_t lock;
 
@@ -100,6 +103,7 @@ struct crypto_priv {
 	struct crypto_queue queue;
 
 	uint32_t ce_lock_count;
+	uint32_t high_bw_req_count;
 
 	struct work_struct unlock_ce_ws;
 
@@ -116,6 +120,8 @@ struct crypto_priv {
 #define NUM_RETRY				1000
 #define CE_BUSY				        55
 
+static DEFINE_MUTEX(sent_bw_req);
+
 static int qcrypto_scm_cmd(int resource, int cmd, int *response)
 {
 #ifdef CONFIG_MSM_SCM
@@ -323,6 +329,27 @@ static void _words_to_byte_stream(uint32_t *iv, unsigned char *b,
 	}
 }
 
+static int qcrypto_ce_high_bw_req(struct crypto_priv *cp, bool high_bw_req)
+{
+	int ret = 0;
+
+	mutex_lock(&sent_bw_req);
+	if (high_bw_req) {
+		if (cp->high_bw_req_count == 0)
+			ret = msm_bus_scale_client_update_request(
+				cp->bus_scale_handle, 1);
+		cp->high_bw_req_count++;
+	} else {
+		if (cp->high_bw_req_count == 1)
+			ret = msm_bus_scale_client_update_request(
+				cp->bus_scale_handle, 0);
+		cp->high_bw_req_count--;
+	}
+	mutex_unlock(&sent_bw_req);
+
+	return ret;
+}
+
 static void _start_qcrypto_process(struct crypto_priv *cp);
 
 static struct qcrypto_alg *_qcrypto_sha_alg_alloc(struct crypto_priv *cp,
@@ -375,6 +402,8 @@ static int _qcrypto_cipher_cra_init(struct crypto_tfm *tfm)
 
 	/* random first IV */
 	get_random_bytes(ctx->iv, QCRYPTO_MAX_IV_LENGTH);
+	if (ctx->cp->platform_support.bus_scale_table != NULL)
+		return  qcrypto_ce_high_bw_req(ctx->cp, true);
 
 	return 0;
 };
@@ -410,6 +439,9 @@ static int _qcrypto_ahash_cra_init(struct crypto_tfm *tfm)
 	}
 
 	sha_ctx->ahash_req = NULL;
+	if (sha_ctx->cp->platform_support.bus_scale_table != NULL)
+		return qcrypto_ce_high_bw_req(sha_ctx->cp, true);
+
 	return 0;
 };
 
@@ -429,6 +461,8 @@ static void _qcrypto_ahash_cra_exit(struct crypto_tfm *tfm)
 		ahash_request_free(sha_ctx->ahash_req);
 		sha_ctx->ahash_req = NULL;
 	}
+	if (sha_ctx->cp->platform_support.bus_scale_table != NULL)
+		qcrypto_ce_high_bw_req(sha_ctx->cp, false);
 };
 
 
@@ -458,6 +492,9 @@ static int _qcrypto_ahash_hmac_cra_init(struct crypto_tfm *tfm)
 				&sha_ctx->ahash_req_complete);
 	crypto_ahash_clear_flags(ahash, ~0);
 
+	if (sha_ctx->cp->platform_support.bus_scale_table != NULL)
+		qcrypto_ce_high_bw_req(sha_ctx->cp, true);
+
 	return 0;
 };
 
@@ -473,6 +510,22 @@ static int _qcrypto_cra_aead_init(struct crypto_tfm *tfm)
 	return _qcrypto_cipher_cra_init(tfm);
 };
 
+static void _qcrypto_cra_ablkcipher_exit(struct crypto_tfm *tfm)
+{
+	struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
+
+	if (ctx->cp->platform_support.bus_scale_table != NULL)
+		qcrypto_ce_high_bw_req(ctx->cp, false);
+};
+
+static void _qcrypto_cra_aead_exit(struct crypto_tfm *tfm)
+{
+	struct qcrypto_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
+
+	if (ctx->cp->platform_support.bus_scale_table != NULL)
+		qcrypto_ce_high_bw_req(ctx->cp, false);
+};
+
 static int _disp_stats(int id)
 {
 	struct crypto_stat *pstat;
@@ -577,6 +630,9 @@ static int _qcrypto_remove(struct platform_device *pdev)
 	if (!cp)
 		return 0;
 
+	if (cp->platform_support.bus_scale_table != NULL)
+		msm_bus_scale_unregister_client(cp->bus_scale_handle);
+
 	list_for_each_entry_safe(q_alg, n, &cp->alg_list, entry) {
 		if (q_alg->alg_type == QCRYPTO_ALG_CIPHER)
 			crypto_unregister_alg(&q_alg->cipher_alg);
@@ -2676,6 +2732,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_algos[] = {
 		.cra_type	= &crypto_ablkcipher_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_ablkcipher_init,
+		.cra_exit	= _qcrypto_cra_ablkcipher_exit,
 		.cra_u		= {
 			.ablkcipher = {
 				.min_keysize	= AES_MIN_KEY_SIZE,
@@ -2697,6 +2754,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_algos[] = {
 		.cra_type	= &crypto_ablkcipher_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_ablkcipher_init,
+		.cra_exit	= _qcrypto_cra_ablkcipher_exit,
 		.cra_u		= {
 			.ablkcipher = {
 				.ivsize		= AES_BLOCK_SIZE,
@@ -2719,6 +2777,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_algos[] = {
 		.cra_type	= &crypto_ablkcipher_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_ablkcipher_init,
+		.cra_exit	= _qcrypto_cra_ablkcipher_exit,
 		.cra_u		= {
 			.ablkcipher = {
 				.ivsize		= AES_BLOCK_SIZE,
@@ -2741,6 +2800,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_algos[] = {
 		.cra_type	= &crypto_ablkcipher_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_ablkcipher_init,
+		.cra_exit	= _qcrypto_cra_ablkcipher_exit,
 		.cra_u		= {
 			.ablkcipher = {
 				.min_keysize	= DES_KEY_SIZE,
@@ -2762,6 +2822,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_algos[] = {
 		.cra_type	= &crypto_ablkcipher_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_ablkcipher_init,
+		.cra_exit	= _qcrypto_cra_ablkcipher_exit,
 		.cra_u		= {
 			.ablkcipher = {
 				.ivsize		= DES_BLOCK_SIZE,
@@ -2784,6 +2845,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_algos[] = {
 		.cra_type	= &crypto_ablkcipher_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_ablkcipher_init,
+		.cra_exit	= _qcrypto_cra_ablkcipher_exit,
 		.cra_u		= {
 			.ablkcipher = {
 				.min_keysize	= DES3_EDE_KEY_SIZE,
@@ -2805,6 +2867,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_algos[] = {
 		.cra_type	= &crypto_ablkcipher_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_ablkcipher_init,
+		.cra_exit	= _qcrypto_cra_ablkcipher_exit,
 		.cra_u		= {
 			.ablkcipher = {
 				.ivsize		= DES3_EDE_BLOCK_SIZE,
@@ -2829,6 +2892,7 @@ static struct crypto_alg _qcrypto_ablk_cipher_xts_algo = {
 	.cra_type	= &crypto_ablkcipher_type,
 	.cra_module	= THIS_MODULE,
 	.cra_init	= _qcrypto_cra_ablkcipher_init,
+	.cra_exit	= _qcrypto_cra_ablkcipher_exit,
 	.cra_u		= {
 		.ablkcipher = {
 			.ivsize		= AES_BLOCK_SIZE,
@@ -2853,6 +2917,7 @@ static struct crypto_alg _qcrypto_aead_sha1_hmac_algos[] = {
 		.cra_type	= &crypto_aead_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_aead_init,
+		.cra_exit	= _qcrypto_cra_aead_exit,
 		.cra_u		= {
 			.aead = {
 				.ivsize         = AES_BLOCK_SIZE,
@@ -2879,6 +2944,7 @@ static struct crypto_alg _qcrypto_aead_sha1_hmac_algos[] = {
 		.cra_type	= &crypto_aead_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_aead_init,
+		.cra_exit	= _qcrypto_cra_aead_exit,
 		.cra_u		= {
 			.aead = {
 				.ivsize         = AES_BLOCK_SIZE,
@@ -2904,6 +2970,7 @@ static struct crypto_alg _qcrypto_aead_sha1_hmac_algos[] = {
 		.cra_type	= &crypto_aead_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_aead_init,
+		.cra_exit	= _qcrypto_cra_aead_exit,
 		.cra_u		= {
 			.aead = {
 				.ivsize         = DES_BLOCK_SIZE,
@@ -2928,6 +2995,7 @@ static struct crypto_alg _qcrypto_aead_sha1_hmac_algos[] = {
 		.cra_type	= &crypto_aead_type,
 		.cra_module	= THIS_MODULE,
 		.cra_init	= _qcrypto_cra_aead_init,
+		.cra_exit	= _qcrypto_cra_aead_exit,
 		.cra_u		= {
 			.aead = {
 				.ivsize         = DES3_EDE_BLOCK_SIZE,
@@ -2954,6 +3022,7 @@ static struct crypto_alg _qcrypto_aead_ccm_algo = {
 	.cra_type	= &crypto_aead_type,
 	.cra_module	= THIS_MODULE,
 	.cra_init	= _qcrypto_cra_aead_init,
+	.cra_exit	= _qcrypto_cra_aead_exit,
 	.cra_u		= {
 		.aead = {
 			.ivsize         = AES_BLOCK_SIZE,
@@ -3011,12 +3080,28 @@ static int  _qcrypto_probe(struct platform_device *pdev)
 				platform_support->shared_ce_resource;
 	cp->platform_support.hw_key_support =
 				platform_support->hw_key_support;
+	cp->platform_support.bus_scale_table =
+				platform_support->bus_scale_table;
+	cp->high_bw_req_count = 0;
 	cp->ce_lock_count = 0;
 	cp->platform_support.sha_hmac = platform_support->sha_hmac;
 
 	if (cp->platform_support.ce_shared)
 		INIT_WORK(&cp->unlock_ce_ws, qcrypto_unlock_ce);
 
+	if (cp->platform_support.bus_scale_table != NULL) {
+		cp->bus_scale_handle =
+			msm_bus_scale_register_client(
+				(struct msm_bus_scale_pdata *)
+					cp->platform_support.bus_scale_table);
+		if (!cp->bus_scale_handle) {
+			printk(KERN_ERR "%s not able to get bus scale\n",
+				__func__);
+			rc =  -ENOMEM;
+			goto err;
+		}
+	}
+
 	/* register crypto cipher algorithms the device supports */
 	for (i = 0; i < ARRAY_SIZE(_qcrypto_ablk_cipher_algos); i++) {
 		struct qcrypto_alg *q_alg;
@@ -3274,4 +3359,4 @@ module_exit(_qcrypto_exit);
 MODULE_LICENSE("GPL v2");
 MODULE_AUTHOR("Mona Hossain <mhossain@codeaurora.org>");
 MODULE_DESCRIPTION("Qualcomm Crypto driver");
-MODULE_VERSION("1.19");
+MODULE_VERSION("1.20");

include/linux/platform_data/qcom_crypto_device.h

@@ -18,6 +18,7 @@ struct msm_ce_hw_support {
 	uint32_t shared_ce_resource;
 	uint32_t hw_key_support;
 	uint32_t sha_hmac;
+	void *bus_scale_table;
 };
 
 #endif /* __QCOM_CRYPTO_DEVICE__H */