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Merge "msm: rpm: Refactor Low Power Mgmt drivers to support single binary" into msm-3.0

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This commit is contained in:
Linux Build Service Account
2012-01-24 04:45:34 -08:00
committed by QuIC Gerrit Code Review
parent 4d4d5c59e7 784990121c
commit b46aff9f4a
24 changed files with 4944 additions and 1652 deletions
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3
arch/arm/mach-msm/Kconfig
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@@ -208,6 +208,9 @@ config ARCH_APQ8064
select MSM_QDSP6_APR
select MSM_AUDIO_QDSP6 if SND_SOC
select MULTI_IRQ_HANDLER
select MSM_RPM
select MSM_SPM_V2
select MSM_L2_SPM
config ARCH_MSMCOPPER
bool "MSM Copper"

4
arch/arm/mach-msm/Makefile
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@@ -141,6 +141,7 @@ obj-$(CONFIG_MSM8X60_AUDIO) += qdsp6v2/
obj-$(CONFIG_MSM_AUDIO_QDSP6) += qdsp6v2/
obj-$(CONFIG_MSM_HW3D) += hw3d.o
ifdef CONFIG_PM
obj-$(CONFIG_ARCH_APQ8064) += pm-8x60.o
obj-$(CONFIG_ARCH_MSM8960) += pm-8x60.o
obj-$(CONFIG_ARCH_MSM8X60) += pm-8x60.o
obj-$(CONFIG_ARCH_MSM9615) += pm-8x60.o
@@ -193,6 +194,7 @@ obj-$(CONFIG_MSM_LPASS_8960) += lpass-8960.o
obj-$(CONFIG_MSM_WCNSS_SSR_8960) += wcnss-ssr-8960.o
ifdef CONFIG_CPU_IDLE
obj-$(CONFIG_ARCH_APQ8064) += cpuidle.o
obj-$(CONFIG_ARCH_MSM8960) += cpuidle.o
obj-$(CONFIG_ARCH_MSM8X60) += cpuidle.o
obj-$(CONFIG_ARCH_MSM9615) += cpuidle.o
@@ -236,7 +238,7 @@ obj-$(CONFIG_ARCH_MSM8960) += saw-regulator.o
obj-$(CONFIG_ARCH_MSM8960) += devices-8960.o
obj-$(CONFIG_ARCH_APQ8064) += devices-8960.o devices-8064.o
board-8960-all-objs += board-8960.o board-8960-camera.o board-8960-display.o board-8960-pmic.o board-8960-storage.o board-8960-gpiomux.o
board-8930-all-objs += board-8930.o board-8930-camera.o board-8930-display.o board-8930-pmic.o board-8930-storage.o board-8930-gpiomux.o
board-8930-all-objs += board-8930.o board-8930-camera.o board-8930-display.o board-8930-pmic.o board-8930-storage.o board-8930-gpiomux.o devices-8930.o
board-8064-all-objs += board-8064.o board-8064-pmic.o board-8064-storage.o board-8064-gpiomux.o
obj-$(CONFIG_MACH_MSM8960_SIM) += board-8960-all.o board-8960-regulator.o
obj-$(CONFIG_MACH_MSM8960_RUMI3) += board-8960-all.o board-8960-regulator.o

388
arch/arm/mach-msm/board-8064.c
View File

@@ -40,6 +40,7 @@
#include "devices.h"
#include <mach/gpio.h>
#include <mach/gpiomux.h>
#include <mach/rpm.h>
#ifdef CONFIG_ANDROID_PMEM
#include <linux/android_pmem.h>
#endif
@@ -48,10 +49,16 @@
#include <asm/setup.h>
#include <mach/dma.h>
#include <mach/msm_bus_board.h>
#include <mach/pm.h>
#include <mach/cpuidle.h>
#include "msm_watchdog.h"
#include "board-8064.h"
#include "acpuclock.h"
#include "spm.h"
#include "mpm.h"
#include "rpm_resources.h"
#include "pm-boot.h"
#define MSM_PMEM_ADSP_SIZE 0x7800000
#define MSM_PMEM_AUDIO_SIZE 0x2B4000
@@ -565,6 +572,13 @@ static void __init apq8064_map_io(void)
static void __init apq8064_init_irq(void)
{
struct msm_mpm_device_data *data = NULL;
#ifdef CONFIG_MSM_MPM
data = &apq8064_mpm_dev_data;
#endif
msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
@@ -604,6 +618,368 @@ static struct platform_device msm8064_device_saw_regulator_core3 = {
.id = 3,
.dev = {
.platform_data = &msm8064_saw_regulator_pdata_8821_s1,
},
};
static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
{
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT,
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
true,
100, 8000, 100000, 1,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
true,
2000, 6000, 60100000, 3000,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(ON, GDHS, MAX, ACTIVE),
false,
4200, 5000, 60350000, 3500,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(ON, HSFS_OPEN, MAX, ACTIVE),
false,
6300, 4500, 65350000, 4800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, GDHS, MAX, ACTIVE),
false,
11700, 2500, 67850000, 5500,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, MAX, ACTIVE),
false,
13800, 2000, 71850000, 6800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, ACTIVE, RET_HIGH),
false,
29700, 500, 75850000, 8800,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE,
MSM_RPMRS_LIMITS(OFF, HSFS_OPEN, RET_HIGH, RET_LOW),
false,
29700, 0, 76350000, 9800,
},
};
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
.mode = MSM_PM_BOOT_CONFIG_TZ,
};
static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
.levels = &msm_rpmrs_levels[0],
.num_levels = ARRAY_SIZE(msm_rpmrs_levels),
.vdd_mem_levels = {
[MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
[MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
[MSM_RPMRS_VDD_MEM_MAX] = 1150000,
},
.vdd_dig_levels = {
[MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
[MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
[MSM_RPMRS_VDD_DIG_MAX] = 1150000,
},
.vdd_mask = 0x7FFFFF,
.rpmrs_target_id = {
[MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
[MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
[MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8921_S3_0,
[MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8921_S3_1,
[MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8921_L24_0,
[MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8921_L24_1,
[MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
},
};
static struct msm_cpuidle_state msm_cstates[] __initdata = {
{0, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
{0, 1, "C1", "STANDALONE_POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
{0, 2, "C2", "POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE},
{1, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
{1, 1, "C1", "STANDALONE_POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
{2, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
{2, 1, "C1", "STANDALONE_POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
{3, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
{3, 1, "C1", "STANDALONE_POWER_COLLAPSE",
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE},
};
static struct msm_pm_platform_data msm_pm_data[] = {
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(0, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 1,
.suspend_enabled = 1,
},
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 0,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(1, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
.idle_supported = 1,
.suspend_supported = 0,
.idle_enabled = 1,
.suspend_enabled = 0,
},
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 0,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(2, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
.idle_supported = 1,
.suspend_supported = 0,
.idle_enabled = 1,
.suspend_enabled = 0,
},
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE)] = {
.idle_supported = 0,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE)] = {
.idle_supported = 1,
.suspend_supported = 1,
.idle_enabled = 0,
.suspend_enabled = 0,
},
[MSM_PM_MODE(3, MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT)] = {
.idle_supported = 1,
.suspend_supported = 0,
.idle_enabled = 1,
.suspend_enabled = 0,
},
};
static uint8_t spm_wfi_cmd_sequence[] __initdata = {
0x03, 0x0f,
};
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x03, 0x01,
0x10, 0x54, 0x30, 0x0C,
0x24, 0x30, 0x0f,
};
static uint8_t spm_power_collapse_with_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x07, 0x01, 0x0B,
0x10, 0x54, 0x30, 0x0C,
0x24, 0x30, 0x0f,
};
static struct msm_spm_seq_entry msm_spm_seq_list[] __initdata = {
[0] = {
.mode = MSM_SPM_MODE_CLOCK_GATING,
.notify_rpm = false,
.cmd = spm_wfi_cmd_sequence,
},
[1] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = false,
.cmd = spm_power_collapse_without_rpm,
},
[2] = {
.mode = MSM_SPM_MODE_POWER_COLLAPSE,
.notify_rpm = true,
.cmd = spm_power_collapse_with_rpm,
},
};
static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = {
0x00, 0x20, 0x03, 0x20,
0x00, 0x0f,
};
static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = {
0x00, 0x20, 0x34, 0x64,
0x48, 0x07, 0x48, 0x20,
0x50, 0x64, 0x04, 0x34,
0x50, 0x0f,
};
static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = {
0x00, 0x10, 0x34, 0x64,
0x48, 0x07, 0x48, 0x10,
0x50, 0x64, 0x04, 0x34,
0x50, 0x0F,
};
static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = {
[0] = {
.mode = MSM_SPM_L2_MODE_RETENTION,
.notify_rpm = false,
.cmd = l2_spm_wfi_cmd_sequence,
},
[1] = {
.mode = MSM_SPM_L2_MODE_GDHS,
.notify_rpm = true,
.cmd = l2_spm_gdhs_cmd_sequence,
},
[2] = {
.mode = MSM_SPM_L2_MODE_POWER_COLLAPSE,
.notify_rpm = true,
.cmd = l2_spm_power_off_cmd_sequence,
},
};
static struct msm_spm_platform_data msm_spm_l2_data[] __initdata = {
[0] = {
.reg_base_addr = MSM_SAW_L2_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x00A000AE,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x00A00020,
.modes = msm_spm_l2_seq_list,
.num_modes = ARRAY_SIZE(msm_spm_l2_seq_list),
},
};
static struct msm_spm_platform_data msm_spm_data[] __initdata = {
[0] = {
.reg_base_addr = MSM_SAW0_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
.reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
#if defined(CONFIG_MSM_AVS_HW)
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
[1] = {
.reg_base_addr = MSM_SAW1_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
.reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
#if defined(CONFIG_MSM_AVS_HW)
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
[2] = {
.reg_base_addr = MSM_SAW2_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
.reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
#if defined(CONFIG_MSM_AVS_HW)
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
[3] = {
.reg_base_addr = MSM_SAW3_BASE,
.reg_init_values[MSM_SPM_REG_SAW2_SECURE] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_CFG] = 0x1F,
.reg_init_values[MSM_SPM_REG_SAW2_VCTL] = 0x9C,
#if defined(CONFIG_MSM_AVS_HW)
.reg_init_values[MSM_SPM_REG_SAW2_AVS_CTL] = 0x00,
.reg_init_values[MSM_SPM_REG_SAW2_AVS_HYSTERESIS] = 0x00,
#endif
.reg_init_values[MSM_SPM_REG_SAW2_SPM_CTL] = 0x01,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DLY] = 0x02020202,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_0] = 0x0060009C,
.reg_init_values[MSM_SPM_REG_SAW2_PMIC_DATA_1] = 0x0000001C,
.vctl_timeout_us = 50,
.num_modes = ARRAY_SIZE(msm_spm_seq_list),
.modes = msm_spm_seq_list,
},
};
@@ -684,6 +1060,9 @@ static struct platform_device *common_devices[] __initdata = {
&apq_pcm_afe,
&apq_cpudai_auxpcm_rx,
&apq_cpudai_auxpcm_tx,
&apq8064_rpm_device,
&apq8064_rpm_log_device,
&apq8064_rpm_stat_device,
&msm_bus_8064_apps_fabric,
&msm_bus_8064_sys_fabric,
&msm_bus_8064_mm_fabric,
@@ -779,6 +1158,8 @@ static void __init apq8064_common_init(void)
{
if (socinfo_init() < 0)
pr_err("socinfo_init() failed!\n");
BUG_ON(msm_rpm_init(&apq8064_rpm_data));
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
apq8064_clock_init();
apq8064_init_gpiomux();
apq8064_i2c_init();
@@ -793,6 +1174,13 @@ static void __init apq8064_common_init(void)
slim_register_board_info(apq8064_slim_devices,
ARRAY_SIZE(apq8064_slim_devices));
acpuclk_init(&acpuclk_8064_soc_data);
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
msm_spm_l2_init(msm_spm_l2_data);
msm_pm_set_platform_data(msm_pm_data, ARRAY_SIZE(msm_pm_data));
msm_pm_set_rpm_wakeup_irq(RPM_APCC_CPU0_WAKE_UP_IRQ);
msm_cpuidle_set_states(msm_cstates, ARRAY_SIZE(msm_cstates),
msm_pm_data);
BUG_ON(msm_pm_boot_init(&msm_pm_boot_pdata));
}
static void __init apq8064_sim_init(void)

213
arch/arm/mach-msm/board-8930.c
View File

@@ -87,7 +87,6 @@
#include "rpm_resources.h"
#include "mpm.h"
#include "acpuclock.h"
#include "rpm_log.h"
#include "smd_private.h"
#include "pm-boot.h"
#include "msm_watchdog.h"
@@ -787,6 +786,102 @@ static struct platform_device *mdm_devices[] __initdata = {
&mdm_device,
};
#ifdef CONFIG_MSM_MPM
static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
[1] = MSM_GPIO_TO_INT(46),
[2] = MSM_GPIO_TO_INT(150),
[4] = MSM_GPIO_TO_INT(103),
[5] = MSM_GPIO_TO_INT(104),
[6] = MSM_GPIO_TO_INT(105),
[7] = MSM_GPIO_TO_INT(106),
[8] = MSM_GPIO_TO_INT(107),
[9] = MSM_GPIO_TO_INT(7),
[10] = MSM_GPIO_TO_INT(11),
[11] = MSM_GPIO_TO_INT(15),
[12] = MSM_GPIO_TO_INT(19),
[13] = MSM_GPIO_TO_INT(23),
[14] = MSM_GPIO_TO_INT(27),
[15] = MSM_GPIO_TO_INT(31),
[16] = MSM_GPIO_TO_INT(35),
[19] = MSM_GPIO_TO_INT(90),
[20] = MSM_GPIO_TO_INT(92),
[23] = MSM_GPIO_TO_INT(85),
[24] = MSM_GPIO_TO_INT(83),
[25] = USB1_HS_IRQ,
[27] = HDMI_IRQ,
[29] = MSM_GPIO_TO_INT(10),
[30] = MSM_GPIO_TO_INT(102),
[31] = MSM_GPIO_TO_INT(81),
[32] = MSM_GPIO_TO_INT(78),
[33] = MSM_GPIO_TO_INT(94),
[34] = MSM_GPIO_TO_INT(72),
[35] = MSM_GPIO_TO_INT(39),
[36] = MSM_GPIO_TO_INT(43),
[37] = MSM_GPIO_TO_INT(61),
[38] = MSM_GPIO_TO_INT(50),
[39] = MSM_GPIO_TO_INT(42),
[41] = MSM_GPIO_TO_INT(62),
[42] = MSM_GPIO_TO_INT(76),
[43] = MSM_GPIO_TO_INT(75),
[44] = MSM_GPIO_TO_INT(70),
[45] = MSM_GPIO_TO_INT(69),
[46] = MSM_GPIO_TO_INT(67),
[47] = MSM_GPIO_TO_INT(65),
[48] = MSM_GPIO_TO_INT(58),
[49] = MSM_GPIO_TO_INT(54),
[50] = MSM_GPIO_TO_INT(52),
[51] = MSM_GPIO_TO_INT(49),
[52] = MSM_GPIO_TO_INT(40),
[53] = MSM_GPIO_TO_INT(37),
[54] = MSM_GPIO_TO_INT(24),
[55] = MSM_GPIO_TO_INT(14),
};
static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
TLMM_MSM_SUMMARY_IRQ,
RPM_APCC_CPU0_GP_HIGH_IRQ,
RPM_APCC_CPU0_GP_MEDIUM_IRQ,
RPM_APCC_CPU0_GP_LOW_IRQ,
RPM_APCC_CPU0_WAKE_UP_IRQ,
RPM_APCC_CPU1_GP_HIGH_IRQ,
RPM_APCC_CPU1_GP_MEDIUM_IRQ,
RPM_APCC_CPU1_GP_LOW_IRQ,
RPM_APCC_CPU1_WAKE_UP_IRQ,
MSS_TO_APPS_IRQ_0,
MSS_TO_APPS_IRQ_1,
MSS_TO_APPS_IRQ_2,
MSS_TO_APPS_IRQ_3,
MSS_TO_APPS_IRQ_4,
MSS_TO_APPS_IRQ_5,
MSS_TO_APPS_IRQ_6,
MSS_TO_APPS_IRQ_7,
MSS_TO_APPS_IRQ_8,
MSS_TO_APPS_IRQ_9,
LPASS_SCSS_GP_LOW_IRQ,
LPASS_SCSS_GP_MEDIUM_IRQ,
LPASS_SCSS_GP_HIGH_IRQ,
SPS_MTI_30,
SPS_MTI_31,
RIVA_APSS_SPARE_IRQ,
RIVA_APPS_WLAN_SMSM_IRQ,
RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
};
struct msm_mpm_device_data msm8930_mpm_dev_data __initdata = {
.irqs_m2a = msm_mpm_irqs_m2a,
.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
.bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
.mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
.mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
.mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
.mpm_apps_ipc_val = BIT(1),
.mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
};
#endif
#define MSM_SHARED_RAM_PHYS 0x80000000
static void __init msm8930_map_io(void)
@@ -800,7 +895,12 @@ static void __init msm8930_map_io(void)
static void __init msm8930_init_irq(void)
{
msm_mpm_irq_extn_init();
struct msm_mpm_device_data *data = NULL;
#ifdef CONFIG_MSM_MPM
data = &msm8930_mpm_dev_data;
#endif
msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
@@ -918,21 +1018,21 @@ static struct platform_device android_usb_device = {
};
static uint8_t spm_wfi_cmd_sequence[] __initdata = {
0x03, 0x0f,
0x03, 0x0f,
};
static uint8_t spm_power_collapse_without_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x03, 0x01,
0x10, 0x54, 0x30, 0x0C,
0x24, 0x30, 0x0f,
0x00, 0x24, 0x54, 0x10,
0x09, 0x03, 0x01,
0x10, 0x54, 0x30, 0x0C,
0x24, 0x30, 0x0f,
};
static uint8_t spm_power_collapse_with_rpm[] __initdata = {
0x00, 0x24, 0x54, 0x10,
0x09, 0x07, 0x01, 0x0B,
0x10, 0x54, 0x30, 0x0C,
0x24, 0x30, 0x0f,
0x00, 0x24, 0x54, 0x10,
0x09, 0x07, 0x01, 0x0B,
0x10, 0x54, 0x30, 0x0C,
0x24, 0x30, 0x0f,
};
static struct msm_spm_seq_entry msm_spm_seq_list[] __initdata = {
@@ -991,21 +1091,21 @@ static struct msm_spm_platform_data msm_spm_data[] __initdata = {
};
static uint8_t l2_spm_wfi_cmd_sequence[] __initdata = {
0x00, 0x20, 0x03, 0x20,
0x00, 0x0f,
0x00, 0x20, 0x03, 0x20,
0x00, 0x0f,
};
static uint8_t l2_spm_gdhs_cmd_sequence[] __initdata = {
0x00, 0x20, 0x34, 0x64,
0x48, 0x07, 0x48, 0x20,
0x50, 0x64, 0x04, 0x34,
0x50, 0x0f,
0x00, 0x20, 0x34, 0x64,
0x48, 0x07, 0x48, 0x20,
0x50, 0x64, 0x04, 0x34,
0x50, 0x0f,
};
static uint8_t l2_spm_power_off_cmd_sequence[] __initdata = {
0x00, 0x10, 0x34, 0x64,
0x48, 0x07, 0x48, 0x10,
0x50, 0x64, 0x04, 0x34,
0x50, 0x0F,
0x00, 0x10, 0x34, 0x64,
0x48, 0x07, 0x48, 0x10,
0x50, 0x64, 0x04, 0x34,
0x50, 0x0F,
};
static struct msm_spm_seq_entry msm_spm_l2_seq_list[] __initdata = {
@@ -1553,20 +1653,6 @@ static struct msm_i2c_platform_data msm8960_i2c_qup_gsbi12_pdata = {
.src_clk_rate = 24000000,
};
static struct msm_rpm_platform_data msm_rpm_data = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
.irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
.irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
.irq_vmpm = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
.msm_apps_ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
.msm_apps_ipc_rpm_val = 4,
};
static struct ks8851_pdata spi_eth_pdata = {
.irq_gpio = KS8851_IRQ_GPIO,
@@ -1687,25 +1773,6 @@ static struct platform_device msm8930_device_rpm_regulator __devinitdata = {
},
};
static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
.phys_addr_base = 0x0010C000,
.reg_offsets = {
[MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
[MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
},
.phys_size = SZ_8K,
.log_len = 4096, /* log's buffer length in bytes */
.log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
};
static struct platform_device msm_rpm_log_device = {
.name = "msm_rpm_log",
.id = -1,
.dev = {
.platform_data = &msm_rpm_log_pdata,
},
};
static struct platform_device *common_devices[] __initdata = {
&msm8960_device_dmov,
&msm_device_smd,
@@ -1763,12 +1830,12 @@ static struct platform_device *common_devices[] __initdata = {
#ifdef CONFIG_HW_RANDOM_MSM
&msm_device_rng,
#endif
&msm_rpm_device,
&msm8930_rpm_device,
&msm8930_rpm_log_device,
&msm8930_rpm_stat_device,
#ifdef CONFIG_ION_MSM
&ion_dev,
#endif
&msm_rpm_log_device,
&msm_rpm_stat_device,
&msm_device_tz_log,
#ifdef CONFIG_MSM_QDSS
@@ -1982,6 +2049,33 @@ static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
},
};
static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
.levels = &msm_rpmrs_levels[0],
.num_levels = ARRAY_SIZE(msm_rpmrs_levels),
.vdd_mem_levels = {
[MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
[MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
[MSM_RPMRS_VDD_MEM_MAX] = 1150000,
},
.vdd_dig_levels = {
[MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
[MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
[MSM_RPMRS_VDD_DIG_MAX] = 1150000,
},
.vdd_mask = 0x7FFFFF,
.rpmrs_target_id = {
[MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
[MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
[MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8038_S1_0,
[MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8038_S1_1,
[MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8038_L24_0,
[MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8038_L24_1,
[MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
},
};
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
.mode = MSM_PM_BOOT_CONFIG_TZ,
};
@@ -2123,9 +2217,8 @@ static void __init msm8930_cdp_init(void)
if (meminfo_init(SYS_MEMORY, SZ_256M) < 0)
pr_err("meminfo_init() failed!\n");
BUG_ON(msm_rpm_init(&msm_rpm_data));
BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
ARRAY_SIZE(msm_rpmrs_levels)));
BUG_ON(msm_rpm_init(&msm8930_rpm_data));
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
if (msm_xo_init())

93
arch/arm/mach-msm/board-8960.c
View File

@@ -92,7 +92,6 @@
#include "rpm_resources.h"
#include "mpm.h"
#include "acpuclock.h"
#include "rpm_log.h"
#include "smd_private.h"
#include "pm-boot.h"
#include "msm_watchdog.h"
@@ -890,7 +889,13 @@ static void __init msm8960_map_io(void)
static void __init msm8960_init_irq(void)
{
msm_mpm_irq_extn_init();
struct msm_mpm_device_data *data = NULL;
#ifdef CONFIG_MSM_MPM
data = &msm8960_mpm_dev_data;
#endif
msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);
@@ -1514,21 +1519,6 @@ static struct msm_i2c_platform_data msm8960_i2c_qup_gsbi12_pdata = {
.src_clk_rate = 24000000,
};
static struct msm_rpm_platform_data msm_rpm_data = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
.irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
.irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
.irq_vmpm = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
.msm_apps_ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
.msm_apps_ipc_rpm_val = 4,
};
static struct msm_pm_sleep_status_data msm_pm_slp_sts_data = {
.base_addr = MSM_ACC0_BASE + 0x08,
.cpu_offset = MSM_ACC1_BASE - MSM_ACC0_BASE,
@@ -1638,25 +1628,6 @@ static struct platform_device msm8960_device_rpm_regulator __devinitdata = {
},
};
static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
.phys_addr_base = 0x0010C000,
.reg_offsets = {
[MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
[MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
},
.phys_size = SZ_8K,
.log_len = 4096, /* log's buffer length in bytes */
.log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
};
static struct platform_device msm_rpm_log_device = {
.name = "msm_rpm_log",
.id = -1,
.dev = {
.platform_data = &msm_rpm_log_pdata,
},
};
static struct platform_device *common_devices[] __initdata = {
&msm8960_device_dmov,
&msm_device_smd,
@@ -1707,14 +1678,13 @@ static struct platform_device *common_devices[] __initdata = {
#ifdef CONFIG_HW_RANDOM_MSM
&msm_device_rng,
#endif
&msm_rpm_device,
#ifdef CONFIG_ION_MSM
&ion_dev,
#endif
&msm_rpm_log_device,
&msm_rpm_stat_device,
&msm8960_rpm_device,
&msm8960_rpm_log_device,
&msm8960_rpm_stat_device,
&msm_device_tz_log,
#ifdef CONFIG_MSM_QDSS
&msm_etb_device,
&msm_tpiu_device,
@@ -1857,6 +1827,7 @@ static void __init msm8960_gfx_init(void)
}
static struct msm_cpuidle_state msm_cstates[] __initdata = {
{0, 0, "C0", "WFI",
MSM_PM_SLEEP_MODE_WAIT_FOR_INTERRUPT},
@@ -1981,6 +1952,33 @@ static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
},
};
static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
.levels = &msm_rpmrs_levels[0],
.num_levels = ARRAY_SIZE(msm_rpmrs_levels),
.vdd_mem_levels = {
[MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
[MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
[MSM_RPMRS_VDD_MEM_MAX] = 1150000,
},
.vdd_dig_levels = {
[MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
[MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
[MSM_RPMRS_VDD_DIG_MAX] = 1150000,
},
.vdd_mask = 0x7FFFFF,
.rpmrs_target_id = {
[MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
[MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
[MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8921_S3_0,
[MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8921_S3_1,
[MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8921_L24_0,
[MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8921_L24_1,
[MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
},
};
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
.mode = MSM_PM_BOOT_CONFIG_TZ,
};
@@ -2179,9 +2177,8 @@ static void __init msm8960_sim_init(void)
&msm8960_device_watchdog.dev.platform_data;
wdog_pdata->bark_time = 15000;
BUG_ON(msm_rpm_init(&msm_rpm_data));
BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
ARRAY_SIZE(msm_rpmrs_levels)));
BUG_ON(msm_rpm_init(&msm8960_rpm_data));
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
platform_device_register(&msm8960_device_rpm_regulator);
msm_clock_init(&msm8960_clock_init_data);
@@ -2216,9 +2213,8 @@ static void __init msm8960_sim_init(void)
static void __init msm8960_rumi3_init(void)
{
BUG_ON(msm_rpm_init(&msm_rpm_data));
BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
ARRAY_SIZE(msm_rpmrs_levels)));
BUG_ON(msm_rpm_init(&msm8960_rpm_data));
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
platform_device_register(&msm8960_device_rpm_regulator);
msm_clock_init(&msm8960_dummy_clock_init_data);
@@ -2251,9 +2247,8 @@ static void __init msm8960_cdp_init(void)
if (meminfo_init(SYS_MEMORY, SZ_256M) < 0)
pr_err("meminfo_init() failed!\n");
BUG_ON(msm_rpm_init(&msm_rpm_data));
BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
ARRAY_SIZE(msm_rpmrs_levels)));
BUG_ON(msm_rpm_init(&msm8960_rpm_data));
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
regulator_suppress_info_printing();
if (msm_xo_init())

4
arch/arm/mach-msm/board-9615.c
View File

@@ -448,7 +448,7 @@ static struct platform_device *common_devices[] = {
&msm9615_device_tsens,
&msm_device_nand,
&msm_device_bam_dmux,
&msm_rpm_device,
&msm9615_rpm_device,
#ifdef CONFIG_HW_RANDOM_MSM
&msm_device_rng,
#endif
@@ -465,6 +465,8 @@ static struct platform_device *common_devices[] = {
&msm9615_device_watchdog,
&msm_bus_9615_sys_fabric,
&msm_bus_def_fab,
&msm9615_rpm_log_device,
&msm9615_rpm_stat_device,
};
static void __init msm9615_i2c_init(void)

79
arch/arm/mach-msm/board-msm8x60.c
View File

@@ -918,6 +918,33 @@ static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
},
};
static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
.levels = &msm_rpmrs_levels[0],
.num_levels = ARRAY_SIZE(msm_rpmrs_levels),
.vdd_mem_levels = {
[MSM_RPMRS_VDD_MEM_RET_LOW] = 500,
[MSM_RPMRS_VDD_MEM_RET_HIGH] = 750,
[MSM_RPMRS_VDD_MEM_ACTIVE] = 1000,
[MSM_RPMRS_VDD_MEM_MAX] = 1250,
},
.vdd_dig_levels = {
[MSM_RPMRS_VDD_DIG_RET_LOW] = 500,
[MSM_RPMRS_VDD_DIG_RET_HIGH] = 750,
[MSM_RPMRS_VDD_DIG_ACTIVE] = 1000,
[MSM_RPMRS_VDD_DIG_MAX] = 1250,
},
.vdd_mask = 0xFFF,
.rpmrs_target_id = {
[MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_PXO_CLK,
[MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_APPS_L2_CACHE_CTL,
[MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_SMPS1_0,
[MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_SMPS1_1,
[MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_SMPS0_0,
[MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_SMPS0_1,
[MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_TRIGGER_SET_FROM,
},
};
static struct msm_pm_boot_platform_data msm_pm_boot_pdata __initdata = {
.mode = MSM_PM_BOOT_CONFIG_TZ,
};
@@ -3727,28 +3754,6 @@ static struct platform_device fluid_leds_gpio = {
#endif
#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
.phys_addr_base = 0x00106000,
.reg_offsets = {
[MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
[MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
},
.phys_size = SZ_8K,
.log_len = 4096, /* log's buffer length in bytes */
.log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
};
static struct platform_device msm_rpm_log_device = {
.name = "msm_rpm_log",
.id = -1,
.dev = {
.platform_data = &msm_rpm_log_pdata,
},
};
#endif
#ifdef CONFIG_BATTERY_MSM8X60
static struct msm_charger_platform_data msm_charger_data = {
.safety_time = 180,
@@ -5193,10 +5198,10 @@ static struct platform_device *surf_devices[] __initdata = {
#endif
#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
&msm_rpm_log_device,
&msm8660_rpm_log_device,
#endif
#if defined(CONFIG_MSM_RPM_STATS_LOG)
&msm_rpm_stat_device,
&msm8660_rpm_stat_device,
#endif
&msm_device_vidc,
#if (defined(CONFIG_MARIMBA_CORE)) && \
@@ -5232,7 +5237,7 @@ static struct platform_device *surf_devices[] __initdata = {
#endif
&msm_tsens_device,
&msm_rpm_device,
&msm8660_rpm_device,
#ifdef CONFIG_ION_MSM
&ion_dev,
#endif
@@ -10045,23 +10050,6 @@ static void __init msm8x60_cfg_smsc911x(void)
PM8058_GPIO_IRQ(PM8058_IRQ_BASE, 6);
}
#ifdef CONFIG_MSM_RPM
static struct msm_rpm_platform_data msm_rpm_data = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
.irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
.irq_err = RPM_SCSS_CPU0_GP_LOW_IRQ,
.irq_vmpm = RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
.msm_apps_ipc_rpm_reg = MSM_GCC_BASE + 0x008,
.msm_apps_ipc_rpm_val = 4,
};
#endif
void msm_fusion_setup_pinctrl(void)
{
struct msm_xo_voter *a1;
@@ -10129,11 +10117,8 @@ static void __init msm8x60_init(struct msm_board_data *board_data)
* Initialize RPM first as other drivers and devices may need
* it for their initialization.
*/
#ifdef CONFIG_MSM_RPM
BUG_ON(msm_rpm_init(&msm_rpm_data));
#endif
BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
ARRAY_SIZE(msm_rpmrs_levels)));
BUG_ON(msm_rpm_init(&msm8660_rpm_data));
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
if (msm_xo_init())
pr_err("Failed to initialize XO votes\n");

387
arch/arm/mach-msm/devices-8064.c
View File

@@ -25,9 +25,13 @@
#include <sound/msm-dai-q6.h>
#include <sound/apr_audio.h>
#include <mach/msm_bus_board.h>
#include <mach/rpm.h>
#include "clock.h"
#include "devices.h"
#include "msm_watchdog.h"
#include "rpm_stats.h"
#include "rpm_log.h"
#include "mpm.h"
/* Address of GSBI blocks */
#define MSM_GSBI1_PHYS 0x12440000
@@ -942,3 +946,386 @@ struct clock_init_data apq8064_dummy_clock_init_data __initdata = {
.table = msm_clocks_8064_dummy,
.size = ARRAY_SIZE(msm_clocks_8064_dummy),
};
struct msm_rpm_platform_data apq8064_rpm_data __initdata = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
.irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
.ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
.ipc_rpm_val = 4,
.target_id = {
MSM_RPM_MAP(8064, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
MSM_RPM_MAP(8064, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
MSM_RPM_MAP(8064, INVALIDATE_0, INVALIDATE, 8),
MSM_RPM_MAP(8064, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
MSM_RPM_MAP(8064, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
MSM_RPM_MAP(8064, RPM_CTL, RPM_CTL, 1),
MSM_RPM_MAP(8064, CXO_CLK, CXO_CLK, 1),
MSM_RPM_MAP(8064, PXO_CLK, PXO_CLK, 1),
MSM_RPM_MAP(8064, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
MSM_RPM_MAP(8064, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
MSM_RPM_MAP(8064, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
MSM_RPM_MAP(8064, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
MSM_RPM_MAP(8064, SFPB_CLK, SFPB_CLK, 1),
MSM_RPM_MAP(8064, CFPB_CLK, CFPB_CLK, 1),
MSM_RPM_MAP(8064, MMFPB_CLK, MMFPB_CLK, 1),
MSM_RPM_MAP(8064, EBI1_CLK, EBI1_CLK, 1),
MSM_RPM_MAP(8064, APPS_FABRIC_CFG_HALT_0,
APPS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8064, APPS_FABRIC_CFG_CLKMOD_0,
APPS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8064, APPS_FABRIC_CFG_IOCTL,
APPS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8064, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
MSM_RPM_MAP(8064, SYS_FABRIC_CFG_HALT_0,
SYS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8064, SYS_FABRIC_CFG_CLKMOD_0,
SYS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8064, SYS_FABRIC_CFG_IOCTL,
SYS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8064, SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 30),
MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_HALT_0,
MMSS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_CLKMOD_0,
MMSS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8064, MMSS_FABRIC_CFG_IOCTL,
MMSS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8064, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 21),
MSM_RPM_MAP(8064, PM8921_S1_0, PM8921_S1, 2),
MSM_RPM_MAP(8064, PM8921_S2_0, PM8921_S2, 2),
MSM_RPM_MAP(8064, PM8921_S3_0, PM8921_S3, 2),
MSM_RPM_MAP(8064, PM8921_S4_0, PM8921_S4, 2),
MSM_RPM_MAP(8064, PM8921_S5_0, PM8921_S5, 2),
MSM_RPM_MAP(8064, PM8921_S6_0, PM8921_S6, 2),
MSM_RPM_MAP(8064, PM8921_S7_0, PM8921_S7, 2),
MSM_RPM_MAP(8064, PM8921_S8_0, PM8921_S8, 2),
MSM_RPM_MAP(8064, PM8921_L1_0, PM8921_L1, 2),
MSM_RPM_MAP(8064, PM8921_L2_0, PM8921_L2, 2),
MSM_RPM_MAP(8064, PM8921_L3_0, PM8921_L3, 2),
MSM_RPM_MAP(8064, PM8921_L4_0, PM8921_L4, 2),
MSM_RPM_MAP(8064, PM8921_L5_0, PM8921_L5, 2),
MSM_RPM_MAP(8064, PM8921_L6_0, PM8921_L6, 2),
MSM_RPM_MAP(8064, PM8921_L7_0, PM8921_L7, 2),
MSM_RPM_MAP(8064, PM8921_L8_0, PM8921_L8, 2),
MSM_RPM_MAP(8064, PM8921_L9_0, PM8921_L9, 2),
MSM_RPM_MAP(8064, PM8921_L10_0, PM8921_L10, 2),
MSM_RPM_MAP(8064, PM8921_L11_0, PM8921_L11, 2),
MSM_RPM_MAP(8064, PM8921_L12_0, PM8921_L12, 2),
MSM_RPM_MAP(8064, PM8921_L13_0, PM8921_L13, 2),
MSM_RPM_MAP(8064, PM8921_L14_0, PM8921_L14, 2),
MSM_RPM_MAP(8064, PM8921_L15_0, PM8921_L15, 2),
MSM_RPM_MAP(8064, PM8921_L16_0, PM8921_L16, 2),
MSM_RPM_MAP(8064, PM8921_L17_0, PM8921_L17, 2),
MSM_RPM_MAP(8064, PM8921_L18_0, PM8921_L18, 2),
MSM_RPM_MAP(8064, PM8921_L19_0, PM8921_L19, 2),
MSM_RPM_MAP(8064, PM8921_L20_0, PM8921_L20, 2),
MSM_RPM_MAP(8064, PM8921_L21_0, PM8921_L21, 2),
MSM_RPM_MAP(8064, PM8921_L22_0, PM8921_L22, 2),
MSM_RPM_MAP(8064, PM8921_L23_0, PM8921_L23, 2),
MSM_RPM_MAP(8064, PM8921_L24_0, PM8921_L24, 2),
MSM_RPM_MAP(8064, PM8921_L25_0, PM8921_L25, 2),
MSM_RPM_MAP(8064, PM8921_L26_0, PM8921_L26, 2),
MSM_RPM_MAP(8064, PM8921_L27_0, PM8921_L27, 2),
MSM_RPM_MAP(8064, PM8921_L28_0, PM8921_L28, 2),
MSM_RPM_MAP(8064, PM8921_L29_0, PM8921_L29, 2),
MSM_RPM_MAP(8064, PM8921_CLK1_0, PM8921_CLK1, 2),
MSM_RPM_MAP(8064, PM8921_CLK2_0, PM8921_CLK2, 2),
MSM_RPM_MAP(8064, PM8921_LVS1, PM8921_LVS1, 1),
MSM_RPM_MAP(8064, PM8921_LVS2, PM8921_LVS2, 1),
MSM_RPM_MAP(8064, PM8921_LVS3, PM8921_LVS3, 1),
MSM_RPM_MAP(8064, PM8921_LVS4, PM8921_LVS4, 1),
MSM_RPM_MAP(8064, PM8921_LVS5, PM8921_LVS5, 1),
MSM_RPM_MAP(8064, PM8921_LVS6, PM8921_LVS6, 1),
MSM_RPM_MAP(8064, PM8921_LVS7, PM8921_LVS7, 1),
MSM_RPM_MAP(8064, PM8821_S1_0, PM8821_S1, 2),
MSM_RPM_MAP(8064, PM8821_S2_0, PM8821_S2, 2),
MSM_RPM_MAP(8064, PM8821_L1_0, PM8821_L1, 2),
MSM_RPM_MAP(8064, NCP_0, NCP, 2),
MSM_RPM_MAP(8064, CXO_BUFFERS, CXO_BUFFERS, 1),
MSM_RPM_MAP(8064, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
MSM_RPM_MAP(8064, HDMI_SWITCH, HDMI_SWITCH, 1),
MSM_RPM_MAP(8064, DDR_DMM_0, DDR_DMM, 2),
MSM_RPM_MAP(8064, QDSS_CLK, QDSS_CLK, 1),
},
.target_status = {
MSM_RPM_STATUS_ID_MAP(8064, VERSION_MAJOR),
MSM_RPM_STATUS_ID_MAP(8064, VERSION_MINOR),
MSM_RPM_STATUS_ID_MAP(8064, VERSION_BUILD),
MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_1),
MSM_RPM_STATUS_ID_MAP(8064, SUPPORTED_RESOURCES_2),
MSM_RPM_STATUS_ID_MAP(8064, RESERVED_SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(8064, SEQUENCE),
MSM_RPM_STATUS_ID_MAP(8064, RPM_CTL),
MSM_RPM_STATUS_ID_MAP(8064, CXO_CLK),
MSM_RPM_STATUS_ID_MAP(8064, PXO_CLK),
MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8064, DAYTONA_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8064, SFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8064, CFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8064, MMFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8064, EBI1_CLK),
MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8064, APPS_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8064, SYS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8064, SYSTEM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8064, MMSS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8064, MM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S1_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S2_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S3_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S4_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S5_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S6_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S7_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_S8_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L1_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L2_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L3_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L4_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L5_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L6_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L7_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L8_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L9_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L10_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L11_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L12_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L13_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L14_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L15_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L16_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L17_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L18_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L19_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L20_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L21_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L22_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L23_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L24_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L25_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L26_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L27_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L28_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_L29_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK1_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_CLK2_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS1),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS2),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS3),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS4),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS5),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS6),
MSM_RPM_STATUS_ID_MAP(8064, PM8921_LVS7),
MSM_RPM_STATUS_ID_MAP(8064, NCP_0),
MSM_RPM_STATUS_ID_MAP(8064, NCP_1),
MSM_RPM_STATUS_ID_MAP(8064, CXO_BUFFERS),
MSM_RPM_STATUS_ID_MAP(8064, USB_OTG_SWITCH),
MSM_RPM_STATUS_ID_MAP(8064, HDMI_SWITCH),
MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_0),
MSM_RPM_STATUS_ID_MAP(8064, DDR_DMM_1),
MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH0_RANGE),
MSM_RPM_STATUS_ID_MAP(8064, EBI1_CH1_RANGE),
MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8821_S1_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8821_S2_1),
MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_0),
MSM_RPM_STATUS_ID_MAP(8064, PM8821_L1_1),
},
.target_ctrl_id = {
MSM_RPM_CTRL_MAP(8064, VERSION_MAJOR),
MSM_RPM_CTRL_MAP(8064, VERSION_MINOR),
MSM_RPM_CTRL_MAP(8064, VERSION_BUILD),
MSM_RPM_CTRL_MAP(8064, REQ_CTX_0),
MSM_RPM_CTRL_MAP(8064, REQ_SEL_0),
MSM_RPM_CTRL_MAP(8064, ACK_CTX_0),
MSM_RPM_CTRL_MAP(8064, ACK_SEL_0),
},
.sel_invalidate = MSM_RPM_8064_SEL_INVALIDATE,
.sel_notification = MSM_RPM_8064_SEL_NOTIFICATION,
.sel_last = MSM_RPM_8064_SEL_LAST,
.ver = {3, 0, 0},
};
struct platform_device apq8064_rpm_device = {
.name = "msm_rpm",
.id = -1,
};
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
.phys_addr_base = 0x0010D204,
.phys_size = SZ_8K,
};
struct platform_device apq8064_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
.dev = {
.platform_data = &msm_rpm_stat_pdata,
},
};
static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
.phys_addr_base = 0x0010C000,
.reg_offsets = {
[MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
[MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
},
.phys_size = SZ_8K,
.log_len = 4096, /* log's buffer length in bytes */
.log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
};
struct platform_device apq8064_rpm_log_device = {
.name = "msm_rpm_log",
.id = -1,
.dev = {
.platform_data = &msm_rpm_log_pdata,
},
};
#ifdef CONFIG_MSM_MPM
static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
[1] = MSM_GPIO_TO_INT(26),
[2] = MSM_GPIO_TO_INT(88),
[4] = MSM_GPIO_TO_INT(73),
[5] = MSM_GPIO_TO_INT(74),
[6] = MSM_GPIO_TO_INT(75),
[7] = MSM_GPIO_TO_INT(76),
[8] = MSM_GPIO_TO_INT(77),
[9] = MSM_GPIO_TO_INT(36),
[10] = MSM_GPIO_TO_INT(84),
[11] = MSM_GPIO_TO_INT(7),
[12] = MSM_GPIO_TO_INT(11),
[13] = MSM_GPIO_TO_INT(52),
[14] = MSM_GPIO_TO_INT(15),
[15] = MSM_GPIO_TO_INT(83),
[16] = USB3_HS_IRQ,
[19] = MSM_GPIO_TO_INT(61),
[20] = MSM_GPIO_TO_INT(58),
[23] = MSM_GPIO_TO_INT(65),
[24] = MSM_GPIO_TO_INT(63),
[25] = USB1_HS_IRQ,
[27] = HDMI_IRQ,
[29] = MSM_GPIO_TO_INT(22),
[30] = MSM_GPIO_TO_INT(72),
[31] = USB4_HS_IRQ,
[33] = MSM_GPIO_TO_INT(44),
[34] = MSM_GPIO_TO_INT(39),
[35] = MSM_GPIO_TO_INT(19),
[36] = MSM_GPIO_TO_INT(23),
[37] = MSM_GPIO_TO_INT(41),
[38] = MSM_GPIO_TO_INT(30),
[41] = MSM_GPIO_TO_INT(42),
[42] = MSM_GPIO_TO_INT(56),
[43] = MSM_GPIO_TO_INT(55),
[44] = MSM_GPIO_TO_INT(50),
[45] = MSM_GPIO_TO_INT(49),
[46] = MSM_GPIO_TO_INT(47),
[47] = MSM_GPIO_TO_INT(45),
[48] = MSM_GPIO_TO_INT(38),
[49] = MSM_GPIO_TO_INT(34),
[50] = MSM_GPIO_TO_INT(32),
[51] = MSM_GPIO_TO_INT(29),
[52] = MSM_GPIO_TO_INT(18),
[53] = MSM_GPIO_TO_INT(10),
[54] = MSM_GPIO_TO_INT(81),
[55] = MSM_GPIO_TO_INT(6),
};
static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
TLMM_MSM_SUMMARY_IRQ,
RPM_APCC_CPU0_GP_HIGH_IRQ,
RPM_APCC_CPU0_GP_MEDIUM_IRQ,
RPM_APCC_CPU0_GP_LOW_IRQ,
RPM_APCC_CPU0_WAKE_UP_IRQ,
RPM_APCC_CPU1_GP_HIGH_IRQ,
RPM_APCC_CPU1_GP_MEDIUM_IRQ,
RPM_APCC_CPU1_GP_LOW_IRQ,
RPM_APCC_CPU1_WAKE_UP_IRQ,
MSS_TO_APPS_IRQ_0,
MSS_TO_APPS_IRQ_1,
MSS_TO_APPS_IRQ_2,
MSS_TO_APPS_IRQ_3,
MSS_TO_APPS_IRQ_4,
MSS_TO_APPS_IRQ_5,
MSS_TO_APPS_IRQ_6,
MSS_TO_APPS_IRQ_7,
MSS_TO_APPS_IRQ_8,
MSS_TO_APPS_IRQ_9,
LPASS_SCSS_GP_LOW_IRQ,
LPASS_SCSS_GP_MEDIUM_IRQ,
LPASS_SCSS_GP_HIGH_IRQ,
SPS_MTI_30,
SPS_MTI_31,
RIVA_APSS_SPARE_IRQ,
RIVA_APPS_WLAN_SMSM_IRQ,
RIVA_APPS_WLAN_RX_DATA_AVAIL_IRQ,
RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
};
struct msm_mpm_device_data apq8064_mpm_dev_data __initdata = {
.irqs_m2a = msm_mpm_irqs_m2a,
.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
.bypassed_apps_irqs_size = ARRAY_SIZE(msm_mpm_bypassed_apps_irqs),
.mpm_request_reg_base = MSM_RPM_BASE + 0x9d8,
.mpm_status_reg_base = MSM_RPM_BASE + 0xdf8,
.mpm_apps_ipc_reg = MSM_APCS_GCC_BASE + 0x008,
.mpm_apps_ipc_val = BIT(1),
.mpm_ipc_irq = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
};
#endif

272
arch/arm/mach-msm/devices-8930.c Normal file
View File

@@ -0,0 +1,272 @@
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <mach/msm_iomap.h>
#include <mach/irqs-8930.h>
#include <mach/rpm.h>
#include "devices.h"
#include "rpm_log.h"
#include "rpm_stats.h"
#ifdef CONFIG_MSM_MPM
#include "mpm.h"
#endif
struct msm_rpm_platform_data msm8930_rpm_data __initdata = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
.irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
.ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
.ipc_rpm_val = 4,
.target_id = {
MSM_RPM_MAP(8930, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
MSM_RPM_MAP(8930, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
MSM_RPM_MAP(8930, INVALIDATE_0, INVALIDATE, 8),
MSM_RPM_MAP(8930, TRIGGER_TIMED_0, TRIGGER_TIMED_0, 2),
MSM_RPM_MAP(8930, RPM_CTL, RPM_CTL, 1),
MSM_RPM_MAP(8930, CXO_CLK, CXO_CLK, 1),
MSM_RPM_MAP(8930, PXO_CLK, PXO_CLK, 1),
MSM_RPM_MAP(8930, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
MSM_RPM_MAP(8930, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
MSM_RPM_MAP(8930, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
MSM_RPM_MAP(8930, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
MSM_RPM_MAP(8930, SFPB_CLK, SFPB_CLK, 1),
MSM_RPM_MAP(8930, CFPB_CLK, CFPB_CLK, 1),
MSM_RPM_MAP(8930, MMFPB_CLK, MMFPB_CLK, 1),
MSM_RPM_MAP(8930, EBI1_CLK, EBI1_CLK, 1),
MSM_RPM_MAP(8930, APPS_FABRIC_CFG_HALT_0,
APPS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8930, APPS_FABRIC_CFG_CLKMOD_0,
APPS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8930, APPS_FABRIC_CFG_IOCTL,
APPS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8930, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
MSM_RPM_MAP(8930, SYS_FABRIC_CFG_HALT_0,
SYS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8930, SYS_FABRIC_CFG_CLKMOD_0,
SYS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8930, SYS_FABRIC_CFG_IOCTL,
SYS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8930, SYSTEM_FABRIC_ARB_0,
SYSTEM_FABRIC_ARB, 20),
MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_HALT_0,
MMSS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_CLKMOD_0,
MMSS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8930, MMSS_FABRIC_CFG_IOCTL,
MMSS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8930, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 11),
MSM_RPM_MAP(8930, PM8038_S1_0, PM8038_S1, 2),
MSM_RPM_MAP(8930, PM8038_S2_0, PM8038_S2, 2),
MSM_RPM_MAP(8930, PM8038_S3_0, PM8038_S3, 2),
MSM_RPM_MAP(8930, PM8038_S4_0, PM8038_S4, 2),
MSM_RPM_MAP(8930, PM8038_S5_0, PM8038_S5, 2),
MSM_RPM_MAP(8930, PM8038_S6_0, PM8038_S6, 2),
MSM_RPM_MAP(8930, PM8038_L1_0, PM8038_L1, 2),
MSM_RPM_MAP(8930, PM8038_L2_0, PM8038_L2, 2),
MSM_RPM_MAP(8930, PM8038_L3_0, PM8038_L3, 2),
MSM_RPM_MAP(8930, PM8038_L4_0, PM8038_L4, 2),
MSM_RPM_MAP(8930, PM8038_L5_0, PM8038_L5, 2),
MSM_RPM_MAP(8930, PM8038_L6_0, PM8038_L6, 2),
MSM_RPM_MAP(8930, PM8038_L7_0, PM8038_L7, 2),
MSM_RPM_MAP(8930, PM8038_L8_0, PM8038_L8, 2),
MSM_RPM_MAP(8930, PM8038_L9_0, PM8038_L9, 2),
MSM_RPM_MAP(8930, PM8038_L10_0, PM8038_L10, 2),
MSM_RPM_MAP(8930, PM8038_L11_0, PM8038_L11, 2),
MSM_RPM_MAP(8930, PM8038_L12_0, PM8038_L12, 2),
MSM_RPM_MAP(8930, PM8038_L13_0, PM8038_L13, 2),
MSM_RPM_MAP(8930, PM8038_L14_0, PM8038_L14, 2),
MSM_RPM_MAP(8930, PM8038_L15_0, PM8038_L15, 2),
MSM_RPM_MAP(8930, PM8038_L16_0, PM8038_L16, 2),
MSM_RPM_MAP(8930, PM8038_L17_0, PM8038_L17, 2),
MSM_RPM_MAP(8930, PM8038_L18_0, PM8038_L18, 2),
MSM_RPM_MAP(8930, PM8038_L19_0, PM8038_L19, 2),
MSM_RPM_MAP(8930, PM8038_L20_0, PM8038_L20, 2),
MSM_RPM_MAP(8930, PM8038_L21_0, PM8038_L21, 2),
MSM_RPM_MAP(8930, PM8038_L22_0, PM8038_L22, 2),
MSM_RPM_MAP(8930, PM8038_L23_0, PM8038_L23, 2),
MSM_RPM_MAP(8930, PM8038_L24_0, PM8038_L24, 2),
MSM_RPM_MAP(8930, PM8038_L25_0, PM8038_L25, 2),
MSM_RPM_MAP(8930, PM8038_L26_0, PM8038_L26, 2),
MSM_RPM_MAP(8930, PM8038_L27_0, PM8038_L27, 2),
MSM_RPM_MAP(8930, PM8038_CLK1_0, PM8038_CLK1, 2),
MSM_RPM_MAP(8930, PM8038_CLK2_0, PM8038_CLK2, 2),
MSM_RPM_MAP(8930, PM8038_LVS1, PM8038_LVS1, 1),
MSM_RPM_MAP(8930, PM8038_LVS2, PM8038_LVS2, 1),
MSM_RPM_MAP(8930, NCP_0, NCP, 2),
MSM_RPM_MAP(8930, CXO_BUFFERS, CXO_BUFFERS, 1),
MSM_RPM_MAP(8930, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
MSM_RPM_MAP(8930, HDMI_SWITCH, HDMI_SWITCH, 1),
MSM_RPM_MAP(8930, QDSS_CLK, QDSS_CLK, 1),
},
.target_status = {
MSM_RPM_STATUS_ID_MAP(8930, VERSION_MAJOR),
MSM_RPM_STATUS_ID_MAP(8930, VERSION_MINOR),
MSM_RPM_STATUS_ID_MAP(8930, VERSION_BUILD),
MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_1),
MSM_RPM_STATUS_ID_MAP(8930, SUPPORTED_RESOURCES_2),
MSM_RPM_STATUS_ID_MAP(8930, RESERVED_SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(8930, SEQUENCE),
MSM_RPM_STATUS_ID_MAP(8930, RPM_CTL),
MSM_RPM_STATUS_ID_MAP(8930, CXO_CLK),
MSM_RPM_STATUS_ID_MAP(8930, PXO_CLK),
MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8930, DAYTONA_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8930, SFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8930, CFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8930, MMFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8930, EBI1_CLK),
MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8930, APPS_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8930, SYS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8930, SYSTEM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8930, MMSS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8930, MM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_S1_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_S2_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_S3_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_S4_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L1_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L2_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L3_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L4_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L5_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L6_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L7_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L8_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L9_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L10_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L11_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L12_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L13_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L14_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L15_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L16_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L17_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L18_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L19_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L20_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L21_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L22_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L23_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L24_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_L25_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK1_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_0),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_CLK2_1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS1),
MSM_RPM_STATUS_ID_MAP(8930, PM8038_LVS2),
MSM_RPM_STATUS_ID_MAP(8930, NCP_0),
MSM_RPM_STATUS_ID_MAP(8930, NCP_1),
MSM_RPM_STATUS_ID_MAP(8930, CXO_BUFFERS),
MSM_RPM_STATUS_ID_MAP(8930, USB_OTG_SWITCH),
MSM_RPM_STATUS_ID_MAP(8930, HDMI_SWITCH),
},
.target_ctrl_id = {
MSM_RPM_CTRL_MAP(8930, VERSION_MAJOR),
MSM_RPM_CTRL_MAP(8930, VERSION_MINOR),
MSM_RPM_CTRL_MAP(8930, VERSION_BUILD),
MSM_RPM_CTRL_MAP(8930, REQ_CTX_0),
MSM_RPM_CTRL_MAP(8930, REQ_SEL_0),
MSM_RPM_CTRL_MAP(8930, ACK_CTX_0),
MSM_RPM_CTRL_MAP(8930, ACK_SEL_0),
},
.sel_invalidate = MSM_RPM_8930_SEL_INVALIDATE,
.sel_notification = MSM_RPM_8930_SEL_NOTIFICATION,
.sel_last = MSM_RPM_8930_SEL_LAST,
.ver = {3, 0, 0},
};
struct platform_device msm8930_rpm_device = {
.name = "msm_rpm",
.id = -1,
};
static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
.phys_addr_base = 0x0010C000,
.reg_offsets = {
[MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
[MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
},
.phys_size = SZ_8K,
.log_len = 4096, /* log's buffer length in bytes */
.log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
};
struct platform_device msm8930_rpm_log_device = {
.name = "msm_rpm_log",
.id = -1,
.dev = {
.platform_data = &msm_rpm_log_pdata,
},
};
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
.phys_addr_base = 0x0010D204,
.phys_size = SZ_8K,
};
struct platform_device msm8930_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
.dev = {
.platform_data = &msm_rpm_stat_pdata,
},
};

358
arch/arm/mach-msm/devices-8960.c
View File

@@ -38,6 +38,7 @@
#include "devices-msm8x60.h"
#include "footswitch.h"
#include "msm_watchdog.h"
#include "rpm_log.h"
#include "rpm_stats.h"
#include "pil-q6v4.h"
#include "scm-pas.h"
@@ -1714,7 +1715,7 @@ struct platform_device msm_device_sps = {
};
#ifdef CONFIG_MSM_MPM
static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
[1] = MSM_GPIO_TO_INT(46),
[2] = MSM_GPIO_TO_INT(150),
[4] = MSM_GPIO_TO_INT(103),
@@ -1764,7 +1765,7 @@ static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
[55] = MSM_GPIO_TO_INT(14),
};
static uint16_t msm_mpm_bypassed_apps_irqs[] = {
static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
TLMM_MSM_SUMMARY_IRQ,
RPM_APCC_CPU0_GP_HIGH_IRQ,
RPM_APCC_CPU0_GP_MEDIUM_IRQ,
@@ -1795,7 +1796,7 @@ static uint16_t msm_mpm_bypassed_apps_irqs[] = {
RIVA_APPS_WLAN_DATA_XFER_DONE_IRQ,
};
struct msm_mpm_device_data msm_mpm_dev_data = {
struct msm_mpm_device_data msm8960_mpm_dev_data __initdata = {
.irqs_m2a = msm_mpm_irqs_m2a,
.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
@@ -2414,105 +2415,280 @@ struct platform_device msm8960_gemini_device = {
};
#endif
struct msm_rpm_map_data rpm_map_data[] __initdata = {
MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
MSM_RPM_MAP(RPM_CTL, RPM_CTL, 1),
MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
MSM_RPM_MAP(PXO_CLK, PXO_CLK, 1),
MSM_RPM_MAP(APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
MSM_RPM_MAP(MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
MSM_RPM_MAP(MMFPB_CLK, MMFPB_CLK, 1),
MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
MSM_RPM_MAP(APPS_FABRIC_CFG_HALT_0, APPS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(APPS_FABRIC_CFG_CLKMOD_0, APPS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(APPS_FABRIC_CFG_IOCTL, APPS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
MSM_RPM_MAP(SYS_FABRIC_CFG_HALT_0, SYS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(SYS_FABRIC_CFG_CLKMOD_0, SYS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(SYS_FABRIC_CFG_IOCTL, SYS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 29),
MSM_RPM_MAP(MMSS_FABRIC_CFG_HALT_0, MMSS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(MMSS_FABRIC_CFG_CLKMOD_0, MMSS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(MMSS_FABRIC_CFG_IOCTL, MMSS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
MSM_RPM_MAP(PM8921_S1_0, PM8921_S1, 2),
MSM_RPM_MAP(PM8921_S2_0, PM8921_S2, 2),
MSM_RPM_MAP(PM8921_S3_0, PM8921_S3, 2),
MSM_RPM_MAP(PM8921_S4_0, PM8921_S4, 2),
MSM_RPM_MAP(PM8921_S5_0, PM8921_S5, 2),
MSM_RPM_MAP(PM8921_S6_0, PM8921_S6, 2),
MSM_RPM_MAP(PM8921_S7_0, PM8921_S7, 2),
MSM_RPM_MAP(PM8921_S8_0, PM8921_S8, 2),
MSM_RPM_MAP(PM8921_L1_0, PM8921_L1, 2),
MSM_RPM_MAP(PM8921_L2_0, PM8921_L2, 2),
MSM_RPM_MAP(PM8921_L3_0, PM8921_L3, 2),
MSM_RPM_MAP(PM8921_L4_0, PM8921_L4, 2),
MSM_RPM_MAP(PM8921_L5_0, PM8921_L5, 2),
MSM_RPM_MAP(PM8921_L6_0, PM8921_L6, 2),
MSM_RPM_MAP(PM8921_L7_0, PM8921_L7, 2),
MSM_RPM_MAP(PM8921_L8_0, PM8921_L8, 2),
MSM_RPM_MAP(PM8921_L9_0, PM8921_L9, 2),
MSM_RPM_MAP(PM8921_L10_0, PM8921_L10, 2),
MSM_RPM_MAP(PM8921_L11_0, PM8921_L11, 2),
MSM_RPM_MAP(PM8921_L12_0, PM8921_L12, 2),
MSM_RPM_MAP(PM8921_L13_0, PM8921_L13, 2),
MSM_RPM_MAP(PM8921_L14_0, PM8921_L14, 2),
MSM_RPM_MAP(PM8921_L15_0, PM8921_L15, 2),
MSM_RPM_MAP(PM8921_L16_0, PM8921_L16, 2),
MSM_RPM_MAP(PM8921_L17_0, PM8921_L17, 2),
MSM_RPM_MAP(PM8921_L18_0, PM8921_L18, 2),
MSM_RPM_MAP(PM8921_L19_0, PM8921_L19, 2),
MSM_RPM_MAP(PM8921_L20_0, PM8921_L20, 2),
MSM_RPM_MAP(PM8921_L21_0, PM8921_L21, 2),
MSM_RPM_MAP(PM8921_L22_0, PM8921_L22, 2),
MSM_RPM_MAP(PM8921_L23_0, PM8921_L23, 2),
MSM_RPM_MAP(PM8921_L24_0, PM8921_L24, 2),
MSM_RPM_MAP(PM8921_L25_0, PM8921_L25, 2),
MSM_RPM_MAP(PM8921_L26_0, PM8921_L26, 2),
MSM_RPM_MAP(PM8921_L27_0, PM8921_L27, 2),
MSM_RPM_MAP(PM8921_L28_0, PM8921_L28, 2),
MSM_RPM_MAP(PM8921_L29_0, PM8921_L29, 2),
MSM_RPM_MAP(PM8921_CLK1_0, PM8921_CLK1, 2),
MSM_RPM_MAP(PM8921_CLK2_0, PM8921_CLK2, 2),
MSM_RPM_MAP(PM8921_LVS1, PM8921_LVS1, 1),
MSM_RPM_MAP(PM8921_LVS2, PM8921_LVS2, 1),
MSM_RPM_MAP(PM8921_LVS3, PM8921_LVS3, 1),
MSM_RPM_MAP(PM8921_LVS4, PM8921_LVS4, 1),
MSM_RPM_MAP(PM8921_LVS5, PM8921_LVS5, 1),
MSM_RPM_MAP(PM8921_LVS6, PM8921_LVS6, 1),
MSM_RPM_MAP(PM8921_LVS7, PM8921_LVS7, 1),
MSM_RPM_MAP(NCP_0, NCP, 2),
MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
MSM_RPM_MAP(USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
MSM_RPM_MAP(HDMI_SWITCH, HDMI_SWITCH, 1),
MSM_RPM_MAP(DDR_DMM_0, DDR_DMM, 2),
MSM_RPM_MAP(QDSS_CLK, QDSS_CLK, 1),
struct msm_rpm_platform_data msm8960_rpm_data __initdata = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
.irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
.ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
.ipc_rpm_val = 4,
.target_id = {
MSM_RPM_MAP(8960, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
MSM_RPM_MAP(8960, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
MSM_RPM_MAP(8960, INVALIDATE_0, INVALIDATE, 8),
MSM_RPM_MAP(8960, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
MSM_RPM_MAP(8960, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
MSM_RPM_MAP(8960, RPM_CTL, RPM_CTL, 1),
MSM_RPM_MAP(8960, CXO_CLK, CXO_CLK, 1),
MSM_RPM_MAP(8960, PXO_CLK, PXO_CLK, 1),
MSM_RPM_MAP(8960, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
MSM_RPM_MAP(8960, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
MSM_RPM_MAP(8960, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
MSM_RPM_MAP(8960, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
MSM_RPM_MAP(8960, SFPB_CLK, SFPB_CLK, 1),
MSM_RPM_MAP(8960, CFPB_CLK, CFPB_CLK, 1),
MSM_RPM_MAP(8960, MMFPB_CLK, MMFPB_CLK, 1),
MSM_RPM_MAP(8960, EBI1_CLK, EBI1_CLK, 1),
MSM_RPM_MAP(8960, APPS_FABRIC_CFG_HALT_0,
APPS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8960, APPS_FABRIC_CFG_CLKMOD_0,
APPS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8960, APPS_FABRIC_CFG_IOCTL,
APPS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8960, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 12),
MSM_RPM_MAP(8960, SYS_FABRIC_CFG_HALT_0,
SYS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8960, SYS_FABRIC_CFG_CLKMOD_0,
SYS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8960, SYS_FABRIC_CFG_IOCTL,
SYS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8960, SYSTEM_FABRIC_ARB_0,
SYSTEM_FABRIC_ARB, 29),
MSM_RPM_MAP(8960, MMSS_FABRIC_CFG_HALT_0,
MMSS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(8960, MMSS_FABRIC_CFG_CLKMOD_0,
MMSS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(8960, MMSS_FABRIC_CFG_IOCTL,
MMSS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(8960, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
MSM_RPM_MAP(8960, PM8921_S1_0, PM8921_S1, 2),
MSM_RPM_MAP(8960, PM8921_S2_0, PM8921_S2, 2),
MSM_RPM_MAP(8960, PM8921_S3_0, PM8921_S3, 2),
MSM_RPM_MAP(8960, PM8921_S4_0, PM8921_S4, 2),
MSM_RPM_MAP(8960, PM8921_S5_0, PM8921_S5, 2),
MSM_RPM_MAP(8960, PM8921_S6_0, PM8921_S6, 2),
MSM_RPM_MAP(8960, PM8921_S7_0, PM8921_S7, 2),
MSM_RPM_MAP(8960, PM8921_S8_0, PM8921_S8, 2),
MSM_RPM_MAP(8960, PM8921_L1_0, PM8921_L1, 2),
MSM_RPM_MAP(8960, PM8921_L2_0, PM8921_L2, 2),
MSM_RPM_MAP(8960, PM8921_L3_0, PM8921_L3, 2),
MSM_RPM_MAP(8960, PM8921_L4_0, PM8921_L4, 2),
MSM_RPM_MAP(8960, PM8921_L5_0, PM8921_L5, 2),
MSM_RPM_MAP(8960, PM8921_L6_0, PM8921_L6, 2),
MSM_RPM_MAP(8960, PM8921_L7_0, PM8921_L7, 2),
MSM_RPM_MAP(8960, PM8921_L8_0, PM8921_L8, 2),
MSM_RPM_MAP(8960, PM8921_L9_0, PM8921_L9, 2),
MSM_RPM_MAP(8960, PM8921_L10_0, PM8921_L10, 2),
MSM_RPM_MAP(8960, PM8921_L11_0, PM8921_L11, 2),
MSM_RPM_MAP(8960, PM8921_L12_0, PM8921_L12, 2),
MSM_RPM_MAP(8960, PM8921_L13_0, PM8921_L13, 2),
MSM_RPM_MAP(8960, PM8921_L14_0, PM8921_L14, 2),
MSM_RPM_MAP(8960, PM8921_L15_0, PM8921_L15, 2),
MSM_RPM_MAP(8960, PM8921_L16_0, PM8921_L16, 2),
MSM_RPM_MAP(8960, PM8921_L17_0, PM8921_L17, 2),
MSM_RPM_MAP(8960, PM8921_L18_0, PM8921_L18, 2),
MSM_RPM_MAP(8960, PM8921_L19_0, PM8921_L19, 2),
MSM_RPM_MAP(8960, PM8921_L20_0, PM8921_L20, 2),
MSM_RPM_MAP(8960, PM8921_L21_0, PM8921_L21, 2),
MSM_RPM_MAP(8960, PM8921_L22_0, PM8921_L22, 2),
MSM_RPM_MAP(8960, PM8921_L23_0, PM8921_L23, 2),
MSM_RPM_MAP(8960, PM8921_L24_0, PM8921_L24, 2),
MSM_RPM_MAP(8960, PM8921_L25_0, PM8921_L25, 2),
MSM_RPM_MAP(8960, PM8921_L26_0, PM8921_L26, 2),
MSM_RPM_MAP(8960, PM8921_L27_0, PM8921_L27, 2),
MSM_RPM_MAP(8960, PM8921_L28_0, PM8921_L28, 2),
MSM_RPM_MAP(8960, PM8921_L29_0, PM8921_L29, 2),
MSM_RPM_MAP(8960, PM8921_CLK1_0, PM8921_CLK1, 2),
MSM_RPM_MAP(8960, PM8921_CLK2_0, PM8921_CLK2, 2),
MSM_RPM_MAP(8960, PM8921_LVS1, PM8921_LVS1, 1),
MSM_RPM_MAP(8960, PM8921_LVS2, PM8921_LVS2, 1),
MSM_RPM_MAP(8960, PM8921_LVS3, PM8921_LVS3, 1),
MSM_RPM_MAP(8960, PM8921_LVS4, PM8921_LVS4, 1),
MSM_RPM_MAP(8960, PM8921_LVS5, PM8921_LVS5, 1),
MSM_RPM_MAP(8960, PM8921_LVS6, PM8921_LVS6, 1),
MSM_RPM_MAP(8960, PM8921_LVS7, PM8921_LVS7, 1),
MSM_RPM_MAP(8960, NCP_0, NCP, 2),
MSM_RPM_MAP(8960, CXO_BUFFERS, CXO_BUFFERS, 1),
MSM_RPM_MAP(8960, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
MSM_RPM_MAP(8960, HDMI_SWITCH, HDMI_SWITCH, 1),
MSM_RPM_MAP(8960, DDR_DMM_0, DDR_DMM, 2),
MSM_RPM_MAP(8960, QDSS_CLK, QDSS_CLK, 1),
},
.target_status = {
MSM_RPM_STATUS_ID_MAP(8960, VERSION_MAJOR),
MSM_RPM_STATUS_ID_MAP(8960, VERSION_MINOR),
MSM_RPM_STATUS_ID_MAP(8960, VERSION_BUILD),
MSM_RPM_STATUS_ID_MAP(8960, SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(8960, SUPPORTED_RESOURCES_1),
MSM_RPM_STATUS_ID_MAP(8960, SUPPORTED_RESOURCES_2),
MSM_RPM_STATUS_ID_MAP(8960, RESERVED_SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(8960, SEQUENCE),
MSM_RPM_STATUS_ID_MAP(8960, RPM_CTL),
MSM_RPM_STATUS_ID_MAP(8960, CXO_CLK),
MSM_RPM_STATUS_ID_MAP(8960, PXO_CLK),
MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8960, SYSTEM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8960, MM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8960, DAYTONA_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8960, SFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8960, CFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8960, MMFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8960, EBI1_CLK),
MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8960, APPS_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8960, SYS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8960, SYS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8960, SYS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8960, SYSTEM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8960, MMSS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(8960, MMSS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(8960, MMSS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(8960, MM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S1_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S1_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S2_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S2_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S3_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S3_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S4_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S4_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S5_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S5_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S6_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S6_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S7_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S7_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S8_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_S8_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L1_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L1_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L2_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L2_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L3_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L3_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L4_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L4_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L5_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L5_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L6_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L6_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L7_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L7_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L8_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L8_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L9_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L9_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L10_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L10_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L11_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L11_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L12_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L12_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L13_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L13_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L14_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L14_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L15_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L15_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L16_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L16_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L17_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L17_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L18_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L18_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L19_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L19_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L20_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L20_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L21_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L21_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L22_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L22_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L23_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L23_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L24_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L24_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L25_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L25_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L26_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L26_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L27_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L27_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L28_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L28_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L29_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_L29_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_CLK1_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_CLK1_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_CLK2_0),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_CLK2_1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS1),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS2),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS3),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS4),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS5),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS6),
MSM_RPM_STATUS_ID_MAP(8960, PM8921_LVS7),
MSM_RPM_STATUS_ID_MAP(8960, NCP_0),
MSM_RPM_STATUS_ID_MAP(8960, NCP_1),
MSM_RPM_STATUS_ID_MAP(8960, CXO_BUFFERS),
MSM_RPM_STATUS_ID_MAP(8960, USB_OTG_SWITCH),
MSM_RPM_STATUS_ID_MAP(8960, HDMI_SWITCH),
MSM_RPM_STATUS_ID_MAP(8960, DDR_DMM_0),
MSM_RPM_STATUS_ID_MAP(8960, DDR_DMM_1),
MSM_RPM_STATUS_ID_MAP(8960, EBI1_CH0_RANGE),
MSM_RPM_STATUS_ID_MAP(8960, EBI1_CH1_RANGE),
},
.target_ctrl_id = {
MSM_RPM_CTRL_MAP(8960, VERSION_MAJOR),
MSM_RPM_CTRL_MAP(8960, VERSION_MINOR),
MSM_RPM_CTRL_MAP(8960, VERSION_BUILD),
MSM_RPM_CTRL_MAP(8960, REQ_CTX_0),
MSM_RPM_CTRL_MAP(8960, REQ_SEL_0),
MSM_RPM_CTRL_MAP(8960, ACK_CTX_0),
MSM_RPM_CTRL_MAP(8960, ACK_SEL_0),
},
.sel_invalidate = MSM_RPM_8960_SEL_INVALIDATE,
.sel_notification = MSM_RPM_8960_SEL_NOTIFICATION,
.sel_last = MSM_RPM_8960_SEL_LAST,
.ver = {3, 0, 0},
};
unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
struct platform_device msm_rpm_device = {
struct platform_device msm8960_rpm_device = {
.name = "msm_rpm",
.id = -1,
};
static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
.phys_addr_base = 0x0010C000,
.reg_offsets = {
[MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
[MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
},
.phys_size = SZ_8K,
.log_len = 4096, /* log's buffer length in bytes */
.log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
};
struct platform_device msm8960_rpm_log_device = {
.name = "msm_rpm_log",
.id = -1,
.dev = {
.platform_data = &msm_rpm_log_pdata,
},
};
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
.phys_addr_base = 0x0010D204,
.phys_size = SZ_8K,
};
struct platform_device msm_rpm_stat_device = {
struct platform_device msm8960_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
.dev = {

263
arch/arm/mach-msm/devices-9615.c
View File

@@ -30,12 +30,14 @@
#include <asm/hardware/cache-l2x0.h>
#include <mach/msm_sps.h>
#include <mach/dma.h>
#include <mach/pm.h>
#include "devices.h"
#include "mpm.h"
#include "spm.h"
#include <mach/pm.h>
#include "rpm_resources.h"
#include "msm_watchdog.h"
#include "rpm_stats.h"
#include "rpm_log.h"
/* Address of GSBI blocks */
#define MSM_GSBI1_PHYS 0x16000000
@@ -724,72 +726,148 @@ static int __init l2x0_cache_init(void)
static int __init l2x0_cache_init(void){ return 0; }
#endif
struct msm_rpm_map_data rpm_map_data[] __initdata = {
MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
MSM_RPM_MAP(RPM_CTL, RPM_CTL, 1),
MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
MSM_RPM_MAP(SYS_FABRIC_CFG_HALT_0, SYS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(SYS_FABRIC_CFG_CLKMOD_0, SYS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(SYS_FABRIC_CFG_IOCTL, SYS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 27),
MSM_RPM_MAP(PM8018_S1_0, PM8018_S1, 2),
MSM_RPM_MAP(PM8018_S2_0, PM8018_S2, 2),
MSM_RPM_MAP(PM8018_S3_0, PM8018_S3, 2),
MSM_RPM_MAP(PM8018_S4_0, PM8018_S4, 2),
MSM_RPM_MAP(PM8018_S5_0, PM8018_S5, 2),
MSM_RPM_MAP(PM8018_L1_0, PM8018_L1, 2),
MSM_RPM_MAP(PM8018_L2_0, PM8018_L2, 2),
MSM_RPM_MAP(PM8018_L3_0, PM8018_L3, 2),
MSM_RPM_MAP(PM8018_L4_0, PM8018_L4, 2),
MSM_RPM_MAP(PM8018_L5_0, PM8018_L5, 2),
MSM_RPM_MAP(PM8018_L6_0, PM8018_L6, 2),
MSM_RPM_MAP(PM8018_L7_0, PM8018_L7, 2),
MSM_RPM_MAP(PM8018_L8_0, PM8018_L8, 2),
MSM_RPM_MAP(PM8018_L9_0, PM8018_L9, 2),
MSM_RPM_MAP(PM8018_L10_0, PM8018_L10, 2),
MSM_RPM_MAP(PM8018_L11_0, PM8018_L11, 2),
MSM_RPM_MAP(PM8018_L12_0, PM8018_L12, 2),
MSM_RPM_MAP(PM8018_L13_0, PM8018_L13, 2),
MSM_RPM_MAP(PM8018_L14_0, PM8018_L14, 2),
MSM_RPM_MAP(PM8018_LVS1, PM8018_LVS1, 1),
MSM_RPM_MAP(NCP_0, NCP, 2),
MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
MSM_RPM_MAP(USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
MSM_RPM_MAP(HDMI_SWITCH, HDMI_SWITCH, 1),
};
unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
static struct msm_rpm_platform_data msm_rpm_data = {
struct msm_rpm_platform_data msm9615_rpm_data __initdata = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
.irq_ack = RPM_APCC_CPU0_GP_HIGH_IRQ,
.irq_err = RPM_APCC_CPU0_GP_LOW_IRQ,
.irq_vmpm = RPM_APCC_CPU0_GP_MEDIUM_IRQ,
.msm_apps_ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
.msm_apps_ipc_rpm_val = 4,
.ipc_rpm_reg = MSM_APCS_GCC_BASE + 0x008,
.ipc_rpm_val = 4,
.target_id = {
MSM_RPM_MAP(9615, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 4),
MSM_RPM_MAP(9615, NOTIFICATION_REGISTERED_0, NOTIFICATION, 4),
MSM_RPM_MAP(9615, INVALIDATE_0, INVALIDATE, 8),
MSM_RPM_MAP(9615, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
MSM_RPM_MAP(9615, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
MSM_RPM_MAP(9615, RPM_CTL, RPM_CTL, 1),
MSM_RPM_MAP(9615, CXO_CLK, CXO_CLK, 1),
MSM_RPM_MAP(9615, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
MSM_RPM_MAP(9615, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
MSM_RPM_MAP(9615, SFPB_CLK, SFPB_CLK, 1),
MSM_RPM_MAP(9615, CFPB_CLK, CFPB_CLK, 1),
MSM_RPM_MAP(9615, EBI1_CLK, EBI1_CLK, 1),
MSM_RPM_MAP(9615, SYS_FABRIC_CFG_HALT_0,
SYS_FABRIC_CFG_HALT, 2),
MSM_RPM_MAP(9615, SYS_FABRIC_CFG_CLKMOD_0,
SYS_FABRIC_CFG_CLKMOD, 3),
MSM_RPM_MAP(9615, SYS_FABRIC_CFG_IOCTL,
SYS_FABRIC_CFG_IOCTL, 1),
MSM_RPM_MAP(9615, SYSTEM_FABRIC_ARB_0,
SYSTEM_FABRIC_ARB, 27),
MSM_RPM_MAP(9615, PM8018_S1_0, PM8018_S1, 2),
MSM_RPM_MAP(9615, PM8018_S2_0, PM8018_S2, 2),
MSM_RPM_MAP(9615, PM8018_S3_0, PM8018_S3, 2),
MSM_RPM_MAP(9615, PM8018_S4_0, PM8018_S4, 2),
MSM_RPM_MAP(9615, PM8018_S5_0, PM8018_S5, 2),
MSM_RPM_MAP(9615, PM8018_L1_0, PM8018_L1, 2),
MSM_RPM_MAP(9615, PM8018_L2_0, PM8018_L2, 2),
MSM_RPM_MAP(9615, PM8018_L3_0, PM8018_L3, 2),
MSM_RPM_MAP(9615, PM8018_L4_0, PM8018_L4, 2),
MSM_RPM_MAP(9615, PM8018_L5_0, PM8018_L5, 2),
MSM_RPM_MAP(9615, PM8018_L6_0, PM8018_L6, 2),
MSM_RPM_MAP(9615, PM8018_L7_0, PM8018_L7, 2),
MSM_RPM_MAP(9615, PM8018_L8_0, PM8018_L8, 2),
MSM_RPM_MAP(9615, PM8018_L9_0, PM8018_L9, 2),
MSM_RPM_MAP(9615, PM8018_L10_0, PM8018_L10, 2),
MSM_RPM_MAP(9615, PM8018_L11_0, PM8018_L11, 2),
MSM_RPM_MAP(9615, PM8018_L12_0, PM8018_L12, 2),
MSM_RPM_MAP(9615, PM8018_L13_0, PM8018_L13, 2),
MSM_RPM_MAP(9615, PM8018_L14_0, PM8018_L14, 2),
MSM_RPM_MAP(9615, PM8018_LVS1, PM8018_LVS1, 1),
MSM_RPM_MAP(9615, NCP_0, NCP, 2),
MSM_RPM_MAP(9615, CXO_BUFFERS, CXO_BUFFERS, 1),
MSM_RPM_MAP(9615, USB_OTG_SWITCH, USB_OTG_SWITCH, 1),
MSM_RPM_MAP(9615, HDMI_SWITCH, HDMI_SWITCH, 1),
},
.target_status = {
MSM_RPM_STATUS_ID_MAP(9615, VERSION_MAJOR),
MSM_RPM_STATUS_ID_MAP(9615, VERSION_MINOR),
MSM_RPM_STATUS_ID_MAP(9615, VERSION_BUILD),
MSM_RPM_STATUS_ID_MAP(9615, SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(9615, SUPPORTED_RESOURCES_1),
MSM_RPM_STATUS_ID_MAP(9615, SUPPORTED_RESOURCES_2),
MSM_RPM_STATUS_ID_MAP(9615, RESERVED_SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(9615, SEQUENCE),
MSM_RPM_STATUS_ID_MAP(9615, RPM_CTL),
MSM_RPM_STATUS_ID_MAP(9615, CXO_CLK),
MSM_RPM_STATUS_ID_MAP(9615, SYSTEM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(9615, DAYTONA_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(9615, SFPB_CLK),
MSM_RPM_STATUS_ID_MAP(9615, CFPB_CLK),
MSM_RPM_STATUS_ID_MAP(9615, EBI1_CLK),
MSM_RPM_STATUS_ID_MAP(9615, SYS_FABRIC_CFG_HALT),
MSM_RPM_STATUS_ID_MAP(9615, SYS_FABRIC_CFG_CLKMOD),
MSM_RPM_STATUS_ID_MAP(9615, SYS_FABRIC_CFG_IOCTL),
MSM_RPM_STATUS_ID_MAP(9615, SYSTEM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S1_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S1_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S2_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S2_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S3_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S3_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S4_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S4_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S5_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_S5_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L1_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L1_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L2_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L2_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L3_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L3_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L4_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L4_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L5_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L5_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L6_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L6_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L7_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L7_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L8_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L8_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L9_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L9_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L10_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L10_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L11_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L11_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L12_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L12_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L13_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L13_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L14_0),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_L14_1),
MSM_RPM_STATUS_ID_MAP(9615, PM8018_LVS1),
MSM_RPM_STATUS_ID_MAP(9615, NCP_0),
MSM_RPM_STATUS_ID_MAP(9615, NCP_1),
MSM_RPM_STATUS_ID_MAP(9615, CXO_BUFFERS),
MSM_RPM_STATUS_ID_MAP(9615, USB_OTG_SWITCH),
MSM_RPM_STATUS_ID_MAP(9615, HDMI_SWITCH),
},
.target_ctrl_id = {
MSM_RPM_CTRL_MAP(9615, VERSION_MAJOR),
MSM_RPM_CTRL_MAP(9615, VERSION_MINOR),
MSM_RPM_CTRL_MAP(9615, VERSION_BUILD),
MSM_RPM_CTRL_MAP(9615, REQ_CTX_0),
MSM_RPM_CTRL_MAP(9615, REQ_SEL_0),
MSM_RPM_CTRL_MAP(9615, ACK_CTX_0),
MSM_RPM_CTRL_MAP(9615, ACK_SEL_0),
},
.sel_invalidate = MSM_RPM_9615_SEL_INVALIDATE,
.sel_notification = MSM_RPM_9615_SEL_NOTIFICATION,
.sel_last = MSM_RPM_9615_SEL_LAST,
.ver = {3, 0, 0},
};
struct platform_device msm_rpm_device = {
struct platform_device msm9615_rpm_device = {
.name = "msm_rpm",
.id = -1,
};
static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
[4] = MSM_GPIO_TO_INT(30),
[5] = MSM_GPIO_TO_INT(59),
[6] = MSM_GPIO_TO_INT(81),
@@ -833,7 +911,7 @@ static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
[55] = MSM_GPIO_TO_INT(27),
};
static uint16_t msm_mpm_bypassed_apps_irqs[] = {
static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
TLMM_MSM_SUMMARY_IRQ,
RPM_APCC_CPU0_GP_HIGH_IRQ,
RPM_APCC_CPU0_GP_MEDIUM_IRQ,
@@ -848,7 +926,7 @@ static uint16_t msm_mpm_bypassed_apps_irqs[] = {
A2_BAM_IRQ,
};
struct msm_mpm_device_data msm_mpm_dev_data = {
struct msm_mpm_device_data msm9615_mpm_dev_data __initdata = {
.irqs_m2a = msm_mpm_irqs_m2a,
.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
@@ -911,7 +989,6 @@ static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
true,
100, 8000, 100000, 1,
},
{
MSM_PM_SLEEP_MODE_POWER_COLLAPSE_STANDALONE,
MSM_RPMRS_LIMITS(ON, ACTIVE, MAX, ACTIVE),
@@ -938,12 +1015,70 @@ static struct msm_rpmrs_level msm_rpmrs_levels[] __initdata = {
},
};
static struct msm_rpmrs_platform_data msm_rpmrs_data __initdata = {
.levels = &msm_rpmrs_levels[0],
.num_levels = ARRAY_SIZE(msm_rpmrs_levels),
.vdd_mem_levels = {
[MSM_RPMRS_VDD_MEM_RET_LOW] = 750000,
[MSM_RPMRS_VDD_MEM_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_MEM_ACTIVE] = 1050000,
[MSM_RPMRS_VDD_MEM_MAX] = 1150000,
},
.vdd_dig_levels = {
[MSM_RPMRS_VDD_DIG_RET_LOW] = 500000,
[MSM_RPMRS_VDD_DIG_RET_HIGH] = 750000,
[MSM_RPMRS_VDD_DIG_ACTIVE] = 950000,
[MSM_RPMRS_VDD_DIG_MAX] = 1150000,
},
.vdd_mask = 0x7FFFFF,
.rpmrs_target_id = {
[MSM_RPMRS_ID_PXO_CLK] = MSM_RPM_ID_CXO_CLK,
[MSM_RPMRS_ID_L2_CACHE_CTL] = MSM_RPM_ID_LAST,
[MSM_RPMRS_ID_VDD_DIG_0] = MSM_RPM_ID_PM8018_S1_0,
[MSM_RPMRS_ID_VDD_DIG_1] = MSM_RPM_ID_PM8018_S1_1,
[MSM_RPMRS_ID_VDD_MEM_0] = MSM_RPM_ID_PM8018_L9_0,
[MSM_RPMRS_ID_VDD_MEM_1] = MSM_RPM_ID_PM8018_L9_1,
[MSM_RPMRS_ID_RPM_CTL] = MSM_RPM_ID_RPM_CTL,
},
};
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
.phys_addr_base = 0x0010D204,
.phys_size = SZ_8K,
};
struct platform_device msm9615_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
.dev = {
.platform_data = &msm_rpm_stat_pdata,
},
};
static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
.phys_addr_base = 0x0010AC00,
.reg_offsets = {
[MSM_RPM_LOG_PAGE_INDICES] = 0x00000080,
[MSM_RPM_LOG_PAGE_BUFFER] = 0x000000A0,
},
.phys_size = SZ_8K,
.log_len = 4096, /* log's buffer length in bytes */
.log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
};
struct platform_device msm9615_rpm_log_device = {
.name = "msm_rpm_log",
.id = -1,
.dev = {
.platform_data = &msm_rpm_log_pdata,
},
};
void __init msm9615_device_init(void)
{
msm_spm_init(msm_spm_data, ARRAY_SIZE(msm_spm_data));
BUG_ON(msm_rpm_init(&msm_rpm_data));
BUG_ON(msm_rpmrs_levels_init(msm_rpmrs_levels,
ARRAY_SIZE(msm_rpmrs_levels)));
BUG_ON(msm_rpm_init(&msm9615_rpm_data));
BUG_ON(msm_rpmrs_levels_init(&msm_rpmrs_data));
}
#define MSM_SHARED_RAM_PHYS 0x40000000
@@ -958,7 +1093,13 @@ void __init msm9615_map_io(void)
void __init msm9615_init_irq(void)
{
msm_mpm_irq_extn_init();
struct msm_mpm_device_data *data = NULL;
#ifdef CONFIG_MSM_MPM
data = &msm9615_mpm_dev_data;
#endif
msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
(void *)MSM_QGIC_CPU_BASE);

375
arch/arm/mach-msm/devices-msm8x60.c
View File

@@ -52,6 +52,7 @@
#include <mach/rpm.h>
#include <mach/board.h>
#include <sound/apr_audio.h>
#include "rpm_log.h"
#include "rpm_stats.h"
#include "mpm.h"
#include "msm_watchdog.h"
@@ -170,7 +171,13 @@ struct platform_device msm_charm_modem = {
void __init msm8x60_init_irq(void)
{
msm_mpm_irq_extn_init();
struct msm_mpm_device_data *data = NULL;
#ifdef CONFIG_MSM_MPM
data = &msm8660_mpm_dev_data;
#endif
msm_mpm_irq_extn_init(data);
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, (void *)MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
@@ -2175,13 +2182,34 @@ struct platform_device msm_device_vidc = {
},
};
#if defined(CONFIG_MSM_RPM_LOG) || defined(CONFIG_MSM_RPM_LOG_MODULE)
static struct msm_rpm_log_platform_data msm_rpm_log_pdata = {
.phys_addr_base = 0x00106000,
.reg_offsets = {
[MSM_RPM_LOG_PAGE_INDICES] = 0x00000C80,
[MSM_RPM_LOG_PAGE_BUFFER] = 0x00000CA0,
},
.phys_size = SZ_8K,
.log_len = 4096, /* log's buffer length in bytes */
.log_len_mask = (4096 >> 2) - 1, /* length mask in units of u32 */
};
struct platform_device msm8660_rpm_log_device = {
.name = "msm_rpm_log",
.id = -1,
.dev = {
.platform_data = &msm_rpm_log_pdata,
},
};
#endif
#if defined(CONFIG_MSM_RPM_STATS_LOG)
static struct msm_rpmstats_platform_data msm_rpm_stat_pdata = {
.phys_addr_base = 0x00107E04,
.phys_size = SZ_8K,
};
struct platform_device msm_rpm_stat_device = {
struct platform_device msm8660_rpm_stat_device = {
.name = "msm_rpm_stat",
.id = -1,
.dev = {
@@ -2191,7 +2219,7 @@ struct platform_device msm_rpm_stat_device = {
#endif
#ifdef CONFIG_MSM_MPM
static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] __initdata = {
[1] = MSM_GPIO_TO_INT(61),
[4] = MSM_GPIO_TO_INT(87),
[5] = MSM_GPIO_TO_INT(88),
@@ -2246,7 +2274,7 @@ static uint16_t msm_mpm_irqs_m2a[MSM_MPM_NR_MPM_IRQS] = {
[59] = MSM_GPIO_TO_INT(129),
};
static uint16_t msm_mpm_bypassed_apps_irqs[] = {
static uint16_t msm_mpm_bypassed_apps_irqs[] __initdata = {
TLMM_MSM_SUMMARY_IRQ,
RPM_SCSS_CPU0_GP_HIGH_IRQ,
RPM_SCSS_CPU0_GP_MEDIUM_IRQ,
@@ -2273,7 +2301,7 @@ static uint16_t msm_mpm_bypassed_apps_irqs[] = {
SPS_MTI_31,
};
struct msm_mpm_device_data msm_mpm_dev_data = {
struct msm_mpm_device_data msm8660_mpm_dev_data __initdata = {
.irqs_m2a = msm_mpm_irqs_m2a,
.irqs_m2a_size = ARRAY_SIZE(msm_mpm_irqs_m2a),
.bypassed_apps_irqs = msm_mpm_bypassed_apps_irqs,
@@ -2433,104 +2461,265 @@ struct platform_device *msm_footswitch_devices[] = {
};
unsigned msm_num_footswitch_devices = ARRAY_SIZE(msm_footswitch_devices);
#ifdef CONFIG_MSM_RPM
struct msm_rpm_map_data rpm_map_data[] __initdata = {
MSM_RPM_MAP(TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
MSM_RPM_MAP(TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
MSM_RPM_MAP(TRIGGER_SET_FROM, TRIGGER_SET, 1),
MSM_RPM_MAP(TRIGGER_SET_TO, TRIGGER_SET, 1),
MSM_RPM_MAP(TRIGGER_SET_TRIGGER, TRIGGER_SET, 1),
MSM_RPM_MAP(TRIGGER_CLEAR_FROM, TRIGGER_CLEAR, 1),
MSM_RPM_MAP(TRIGGER_CLEAR_TO, TRIGGER_CLEAR, 1),
MSM_RPM_MAP(TRIGGER_CLEAR_TRIGGER, TRIGGER_CLEAR, 1),
struct msm_rpm_platform_data msm8660_rpm_data __initdata = {
.reg_base_addrs = {
[MSM_RPM_PAGE_STATUS] = MSM_RPM_BASE,
[MSM_RPM_PAGE_CTRL] = MSM_RPM_BASE + 0x400,
[MSM_RPM_PAGE_REQ] = MSM_RPM_BASE + 0x600,
[MSM_RPM_PAGE_ACK] = MSM_RPM_BASE + 0xa00,
},
.irq_ack = RPM_SCSS_CPU0_GP_HIGH_IRQ,
.ipc_rpm_reg = MSM_GCC_BASE + 0x008,
.ipc_rpm_val = 4,
.target_id = {
MSM_RPM_MAP(8660, NOTIFICATION_CONFIGURED_0, NOTIFICATION, 8),
MSM_RPM_MAP(8660, NOTIFICATION_REGISTERED_0, NOTIFICATION, 8),
MSM_RPM_MAP(8660, INVALIDATE_0, INVALIDATE, 8),
MSM_RPM_MAP(8660, TRIGGER_TIMED_TO, TRIGGER_TIMED, 1),
MSM_RPM_MAP(8660, TRIGGER_TIMED_SCLK_COUNT, TRIGGER_TIMED, 1),
MSM_RPM_MAP(8660, TRIGGER_SET_FROM, TRIGGER_SET, 1),
MSM_RPM_MAP(8660, TRIGGER_SET_TO, TRIGGER_SET, 1),
MSM_RPM_MAP(8660, TRIGGER_SET_TRIGGER, TRIGGER_SET, 1),
MSM_RPM_MAP(8660, TRIGGER_CLEAR_FROM, TRIGGER_CLEAR, 1),
MSM_RPM_MAP(8660, TRIGGER_CLEAR_TO, TRIGGER_CLEAR, 1),
MSM_RPM_MAP(8660, TRIGGER_CLEAR_TRIGGER, TRIGGER_CLEAR, 1),
MSM_RPM_MAP(CXO_CLK, CXO_CLK, 1),
MSM_RPM_MAP(PXO_CLK, PXO_CLK, 1),
MSM_RPM_MAP(PLL_4, PLL_4, 1),
MSM_RPM_MAP(APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
MSM_RPM_MAP(SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
MSM_RPM_MAP(MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
MSM_RPM_MAP(DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
MSM_RPM_MAP(SFPB_CLK, SFPB_CLK, 1),
MSM_RPM_MAP(CFPB_CLK, CFPB_CLK, 1),
MSM_RPM_MAP(MMFPB_CLK, MMFPB_CLK, 1),
MSM_RPM_MAP(SMI_CLK, SMI_CLK, 1),
MSM_RPM_MAP(EBI1_CLK, EBI1_CLK, 1),
MSM_RPM_MAP(8660, CXO_CLK, CXO_CLK, 1),
MSM_RPM_MAP(8660, PXO_CLK, PXO_CLK, 1),
MSM_RPM_MAP(8660, PLL_4, PLL_4, 1),
MSM_RPM_MAP(8660, APPS_FABRIC_CLK, APPS_FABRIC_CLK, 1),
MSM_RPM_MAP(8660, SYSTEM_FABRIC_CLK, SYSTEM_FABRIC_CLK, 1),
MSM_RPM_MAP(8660, MM_FABRIC_CLK, MM_FABRIC_CLK, 1),
MSM_RPM_MAP(8660, DAYTONA_FABRIC_CLK, DAYTONA_FABRIC_CLK, 1),
MSM_RPM_MAP(8660, SFPB_CLK, SFPB_CLK, 1),
MSM_RPM_MAP(8660, CFPB_CLK, CFPB_CLK, 1),
MSM_RPM_MAP(8660, MMFPB_CLK, MMFPB_CLK, 1),
MSM_RPM_MAP(8660, SMI_CLK, SMI_CLK, 1),
MSM_RPM_MAP(8660, EBI1_CLK, EBI1_CLK, 1),
MSM_RPM_MAP(APPS_L2_CACHE_CTL, APPS_L2_CACHE_CTL, 1),
MSM_RPM_MAP(8660, APPS_L2_CACHE_CTL, APPS_L2_CACHE_CTL, 1),
MSM_RPM_MAP(APPS_FABRIC_HALT_0, APPS_FABRIC_HALT, 2),
MSM_RPM_MAP(APPS_FABRIC_CLOCK_MODE_0, APPS_FABRIC_CLOCK_MODE, 3),
MSM_RPM_MAP(APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
MSM_RPM_MAP(8660, APPS_FABRIC_HALT_0, APPS_FABRIC_HALT, 2),
MSM_RPM_MAP(8660, APPS_FABRIC_CLOCK_MODE_0,
APPS_FABRIC_CLOCK_MODE, 3),
MSM_RPM_MAP(8660, APPS_FABRIC_ARB_0, APPS_FABRIC_ARB, 6),
MSM_RPM_MAP(SYSTEM_FABRIC_HALT_0, SYSTEM_FABRIC_HALT, 2),
MSM_RPM_MAP(SYSTEM_FABRIC_CLOCK_MODE_0, SYSTEM_FABRIC_CLOCK_MODE, 3),
MSM_RPM_MAP(SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 22),
MSM_RPM_MAP(8660, SYSTEM_FABRIC_HALT_0, SYSTEM_FABRIC_HALT, 2),
MSM_RPM_MAP(8660, SYSTEM_FABRIC_CLOCK_MODE_0,
SYSTEM_FABRIC_CLOCK_MODE, 3),
MSM_RPM_MAP(8660, SYSTEM_FABRIC_ARB_0, SYSTEM_FABRIC_ARB, 22),
MSM_RPM_MAP(MM_FABRIC_HALT_0, MM_FABRIC_HALT, 2),
MSM_RPM_MAP(MM_FABRIC_CLOCK_MODE_0, MM_FABRIC_CLOCK_MODE, 3),
MSM_RPM_MAP(MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
MSM_RPM_MAP(8660, MM_FABRIC_HALT_0, MM_FABRIC_HALT, 2),
MSM_RPM_MAP(8660, MM_FABRIC_CLOCK_MODE_0,
MM_FABRIC_CLOCK_MODE, 3),
MSM_RPM_MAP(8660, MM_FABRIC_ARB_0, MM_FABRIC_ARB, 23),
MSM_RPM_MAP(SMPS0B_0, SMPS0B, 2),
MSM_RPM_MAP(SMPS1B_0, SMPS1B, 2),
MSM_RPM_MAP(SMPS2B_0, SMPS2B, 2),
MSM_RPM_MAP(SMPS3B_0, SMPS3B, 2),
MSM_RPM_MAP(SMPS4B_0, SMPS4B, 2),
MSM_RPM_MAP(LDO0B_0, LDO0B, 2),
MSM_RPM_MAP(LDO1B_0, LDO1B, 2),
MSM_RPM_MAP(LDO2B_0, LDO2B, 2),
MSM_RPM_MAP(LDO3B_0, LDO3B, 2),
MSM_RPM_MAP(LDO4B_0, LDO4B, 2),
MSM_RPM_MAP(LDO5B_0, LDO5B, 2),
MSM_RPM_MAP(LDO6B_0, LDO6B, 2),
MSM_RPM_MAP(LVS0B, LVS0B, 1),
MSM_RPM_MAP(LVS1B, LVS1B, 1),
MSM_RPM_MAP(LVS2B, LVS2B, 1),
MSM_RPM_MAP(LVS3B, LVS3B, 1),
MSM_RPM_MAP(MVS, MVS, 1),
MSM_RPM_MAP(8660, SMPS0B_0, SMPS0B, 2),
MSM_RPM_MAP(8660, SMPS1B_0, SMPS1B, 2),
MSM_RPM_MAP(8660, SMPS2B_0, SMPS2B, 2),
MSM_RPM_MAP(8660, SMPS3B_0, SMPS3B, 2),
MSM_RPM_MAP(8660, SMPS4B_0, SMPS4B, 2),
MSM_RPM_MAP(8660, LDO0B_0, LDO0B, 2),
MSM_RPM_MAP(8660, LDO1B_0, LDO1B, 2),
MSM_RPM_MAP(8660, LDO2B_0, LDO2B, 2),
MSM_RPM_MAP(8660, LDO3B_0, LDO3B, 2),
MSM_RPM_MAP(8660, LDO4B_0, LDO4B, 2),
MSM_RPM_MAP(8660, LDO5B_0, LDO5B, 2),
MSM_RPM_MAP(8660, LDO6B_0, LDO6B, 2),
MSM_RPM_MAP(8660, LVS0B, LVS0B, 1),
MSM_RPM_MAP(8660, LVS1B, LVS1B, 1),
MSM_RPM_MAP(8660, LVS2B, LVS2B, 1),
MSM_RPM_MAP(8660, LVS3B, LVS3B, 1),
MSM_RPM_MAP(8660, MVS, MVS, 1),
MSM_RPM_MAP(SMPS0_0, SMPS0, 2),
MSM_RPM_MAP(SMPS1_0, SMPS1, 2),
MSM_RPM_MAP(SMPS2_0, SMPS2, 2),
MSM_RPM_MAP(SMPS3_0, SMPS3, 2),
MSM_RPM_MAP(SMPS4_0, SMPS4, 2),
MSM_RPM_MAP(LDO0_0, LDO0, 2),
MSM_RPM_MAP(LDO1_0, LDO1, 2),
MSM_RPM_MAP(LDO2_0, LDO2, 2),
MSM_RPM_MAP(LDO3_0, LDO3, 2),
MSM_RPM_MAP(LDO4_0, LDO4, 2),
MSM_RPM_MAP(LDO5_0, LDO5, 2),
MSM_RPM_MAP(LDO6_0, LDO6, 2),
MSM_RPM_MAP(LDO7_0, LDO7, 2),
MSM_RPM_MAP(LDO8_0, LDO8, 2),
MSM_RPM_MAP(LDO9_0, LDO9, 2),
MSM_RPM_MAP(LDO10_0, LDO10, 2),
MSM_RPM_MAP(LDO11_0, LDO11, 2),
MSM_RPM_MAP(LDO12_0, LDO12, 2),
MSM_RPM_MAP(LDO13_0, LDO13, 2),
MSM_RPM_MAP(LDO14_0, LDO14, 2),
MSM_RPM_MAP(LDO15_0, LDO15, 2),
MSM_RPM_MAP(LDO16_0, LDO16, 2),
MSM_RPM_MAP(LDO17_0, LDO17, 2),
MSM_RPM_MAP(LDO18_0, LDO18, 2),
MSM_RPM_MAP(LDO19_0, LDO19, 2),
MSM_RPM_MAP(LDO20_0, LDO20, 2),
MSM_RPM_MAP(LDO21_0, LDO21, 2),
MSM_RPM_MAP(LDO22_0, LDO22, 2),
MSM_RPM_MAP(LDO23_0, LDO23, 2),
MSM_RPM_MAP(LDO24_0, LDO24, 2),
MSM_RPM_MAP(LDO25_0, LDO25, 2),
MSM_RPM_MAP(LVS0, LVS0, 1),
MSM_RPM_MAP(LVS1, LVS1, 1),
MSM_RPM_MAP(NCP_0, NCP, 2),
MSM_RPM_MAP(8660, SMPS0_0, SMPS0, 2),
MSM_RPM_MAP(8660, SMPS1_0, SMPS1, 2),
MSM_RPM_MAP(8660, SMPS2_0, SMPS2, 2),
MSM_RPM_MAP(8660, SMPS3_0, SMPS3, 2),
MSM_RPM_MAP(8660, SMPS4_0, SMPS4, 2),
MSM_RPM_MAP(8660, LDO0_0, LDO0, 2),
MSM_RPM_MAP(8660, LDO1_0, LDO1, 2),
MSM_RPM_MAP(8660, LDO2_0, LDO2, 2),
MSM_RPM_MAP(8660, LDO3_0, LDO3, 2),
MSM_RPM_MAP(8660, LDO4_0, LDO4, 2),
MSM_RPM_MAP(8660, LDO5_0, LDO5, 2),
MSM_RPM_MAP(8660, LDO6_0, LDO6, 2),
MSM_RPM_MAP(8660, LDO7_0, LDO7, 2),
MSM_RPM_MAP(8660, LDO8_0, LDO8, 2),
MSM_RPM_MAP(8660, LDO9_0, LDO9, 2),
MSM_RPM_MAP(8660, LDO10_0, LDO10, 2),
MSM_RPM_MAP(8660, LDO11_0, LDO11, 2),
MSM_RPM_MAP(8660, LDO12_0, LDO12, 2),
MSM_RPM_MAP(8660, LDO13_0, LDO13, 2),
MSM_RPM_MAP(8660, LDO14_0, LDO14, 2),
MSM_RPM_MAP(8660, LDO15_0, LDO15, 2),
MSM_RPM_MAP(8660, LDO16_0, LDO16, 2),
MSM_RPM_MAP(8660, LDO17_0, LDO17, 2),
MSM_RPM_MAP(8660, LDO18_0, LDO18, 2),
MSM_RPM_MAP(8660, LDO19_0, LDO19, 2),
MSM_RPM_MAP(8660, LDO20_0, LDO20, 2),
MSM_RPM_MAP(8660, LDO21_0, LDO21, 2),
MSM_RPM_MAP(8660, LDO22_0, LDO22, 2),
MSM_RPM_MAP(8660, LDO23_0, LDO23, 2),
MSM_RPM_MAP(8660, LDO24_0, LDO24, 2),
MSM_RPM_MAP(8660, LDO25_0, LDO25, 2),
MSM_RPM_MAP(8660, LVS0, LVS0, 1),
MSM_RPM_MAP(8660, LVS1, LVS1, 1),
MSM_RPM_MAP(8660, NCP_0, NCP, 2),
MSM_RPM_MAP(8660, CXO_BUFFERS, CXO_BUFFERS, 1),
},
.target_status = {
MSM_RPM_STATUS_ID_MAP(8660, VERSION_MAJOR),
MSM_RPM_STATUS_ID_MAP(8660, VERSION_MINOR),
MSM_RPM_STATUS_ID_MAP(8660, VERSION_BUILD),
MSM_RPM_STATUS_ID_MAP(8660, SUPPORTED_RESOURCES_0),
MSM_RPM_STATUS_ID_MAP(8660, SUPPORTED_RESOURCES_1),
MSM_RPM_STATUS_ID_MAP(8660, SUPPORTED_RESOURCES_2),
MSM_RPM_STATUS_ID_MAP(8660, SEQUENCE),
MSM_RPM_MAP(CXO_BUFFERS, CXO_BUFFERS, 1),
MSM_RPM_STATUS_ID_MAP(8660, CXO_CLK),
MSM_RPM_STATUS_ID_MAP(8660, PXO_CLK),
MSM_RPM_STATUS_ID_MAP(8660, PLL_4),
MSM_RPM_STATUS_ID_MAP(8660, APPS_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8660, SYSTEM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8660, MM_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8660, DAYTONA_FABRIC_CLK),
MSM_RPM_STATUS_ID_MAP(8660, SFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8660, CFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8660, MMFPB_CLK),
MSM_RPM_STATUS_ID_MAP(8660, SMI_CLK),
MSM_RPM_STATUS_ID_MAP(8660, EBI1_CLK),
MSM_RPM_STATUS_ID_MAP(8660, APPS_L2_CACHE_CTL),
MSM_RPM_STATUS_ID_MAP(8660, APPS_FABRIC_HALT),
MSM_RPM_STATUS_ID_MAP(8660, APPS_FABRIC_CLOCK_MODE),
MSM_RPM_STATUS_ID_MAP(8660, APPS_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8660, SYSTEM_FABRIC_HALT),
MSM_RPM_STATUS_ID_MAP(8660, SYSTEM_FABRIC_CLOCK_MODE),
MSM_RPM_STATUS_ID_MAP(8660, SYSTEM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8660, MM_FABRIC_HALT),
MSM_RPM_STATUS_ID_MAP(8660, MM_FABRIC_CLOCK_MODE),
MSM_RPM_STATUS_ID_MAP(8660, MM_FABRIC_ARB),
MSM_RPM_STATUS_ID_MAP(8660, SMPS0B_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS0B_1),
MSM_RPM_STATUS_ID_MAP(8660, SMPS1B_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS1B_1),
MSM_RPM_STATUS_ID_MAP(8660, SMPS2B_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS2B_1),
MSM_RPM_STATUS_ID_MAP(8660, SMPS3B_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS3B_1),
MSM_RPM_STATUS_ID_MAP(8660, SMPS4B_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS4B_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO0B_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO0B_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO1B_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO1B_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO2B_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO2B_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO3B_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO3B_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO4B_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO4B_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO5B_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO5B_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO6B_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO6B_1),
MSM_RPM_STATUS_ID_MAP(8660, LVS0B),
MSM_RPM_STATUS_ID_MAP(8660, LVS1B),
MSM_RPM_STATUS_ID_MAP(8660, LVS2B),
MSM_RPM_STATUS_ID_MAP(8660, LVS3B),
MSM_RPM_STATUS_ID_MAP(8660, MVS),
MSM_RPM_STATUS_ID_MAP(8660, SMPS0_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS0_1),
MSM_RPM_STATUS_ID_MAP(8660, SMPS1_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS1_1),
MSM_RPM_STATUS_ID_MAP(8660, SMPS2_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS2_1),
MSM_RPM_STATUS_ID_MAP(8660, SMPS3_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS3_1),
MSM_RPM_STATUS_ID_MAP(8660, SMPS4_0),
MSM_RPM_STATUS_ID_MAP(8660, SMPS4_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO0_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO0_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO1_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO1_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO2_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO2_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO3_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO3_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO4_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO4_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO5_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO5_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO6_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO6_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO7_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO7_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO8_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO8_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO9_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO9_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO10_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO10_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO11_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO11_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO12_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO12_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO13_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO13_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO14_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO14_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO15_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO15_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO16_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO16_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO17_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO17_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO18_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO18_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO19_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO19_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO20_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO20_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO21_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO21_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO22_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO22_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO23_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO23_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO24_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO24_1),
MSM_RPM_STATUS_ID_MAP(8660, LDO25_0),
MSM_RPM_STATUS_ID_MAP(8660, LDO25_1),
MSM_RPM_STATUS_ID_MAP(8660, LVS0),
MSM_RPM_STATUS_ID_MAP(8660, LVS1),
MSM_RPM_STATUS_ID_MAP(8660, NCP_0),
MSM_RPM_STATUS_ID_MAP(8660, NCP_1),
MSM_RPM_STATUS_ID_MAP(8660, CXO_BUFFERS),
},
.target_ctrl_id = {
MSM_RPM_CTRL_MAP(8660, VERSION_MAJOR),
MSM_RPM_CTRL_MAP(8660, VERSION_MINOR),
MSM_RPM_CTRL_MAP(8660, VERSION_BUILD),
MSM_RPM_CTRL_MAP(8660, REQ_CTX_0),
MSM_RPM_CTRL_MAP(8660, REQ_SEL_0),
MSM_RPM_CTRL_MAP(8660, ACK_CTX_0),
MSM_RPM_CTRL_MAP(8660, ACK_SEL_0),
},
.sel_invalidate = MSM_RPM_8660_SEL_INVALIDATE,
.sel_notification = MSM_RPM_8660_SEL_NOTIFICATION,
.sel_last = MSM_RPM_8660_SEL_LAST,
.ver = {2, 0, 0},
};
unsigned int rpm_map_data_size = ARRAY_SIZE(rpm_map_data);
struct platform_device msm_rpm_device = {
struct platform_device msm8660_rpm_device = {
.name = "msm_rpm",
.id = -1,
};
#endif

22
arch/arm/mach-msm/devices.h
View File

@@ -240,8 +240,26 @@ extern struct platform_device msm_device_touchscreen;
extern struct platform_device led_pdev;
extern struct platform_device msm_rpm_device;
extern struct platform_device msm_rpm_stat_device;
extern struct platform_device msm8960_rpm_device;
extern struct platform_device msm8960_rpm_stat_device;
extern struct platform_device msm8960_rpm_log_device;
extern struct platform_device msm8930_rpm_device;
extern struct platform_device msm8930_rpm_stat_device;
extern struct platform_device msm8930_rpm_log_device;
extern struct platform_device msm8660_rpm_device;
extern struct platform_device msm8660_rpm_stat_device;
extern struct platform_device msm8660_rpm_log_device;
extern struct platform_device msm9615_rpm_device;
extern struct platform_device msm9615_rpm_stat_device;
extern struct platform_device msm9615_rpm_log_device;
extern struct platform_device apq8064_rpm_device;
extern struct platform_device apq8064_rpm_stat_device;
extern struct platform_device apq8064_rpm_log_device;
extern struct platform_device msm_device_rng;
extern struct platform_device apq8064_device_rng;

432
arch/arm/mach-msm/include/mach/rpm-8064.h Normal file
View File

@@ -0,0 +1,432 @@
/* Copyright (c) 2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_MSM_RPM_8064_H
#define __ARCH_ARM_MACH_MSM_RPM_8064_H
/* RPM control message RAM enums */
enum {
MSM_RPM_8064_CTRL_VERSION_MAJOR,
MSM_RPM_8064_CTRL_VERSION_MINOR,
MSM_RPM_8064_CTRL_VERSION_BUILD,
MSM_RPM_8064_CTRL_REQ_CTX_0,
MSM_RPM_8064_CTRL_REQ_CTX_7 = MSM_RPM_8064_CTRL_REQ_CTX_0 + 7,
MSM_RPM_8064_CTRL_REQ_SEL_0,
MSM_RPM_8064_CTRL_REQ_SEL_3 = MSM_RPM_8064_CTRL_REQ_SEL_0 + 3,
MSM_RPM_8064_CTRL_ACK_CTX_0,
MSM_RPM_8064_CTRL_ACK_CTX_7 = MSM_RPM_8064_CTRL_ACK_CTX_0 + 7,
MSM_RPM_8064_CTRL_ACK_SEL_0,
MSM_RPM_8064_CTRL_ACK_SEL_7 = MSM_RPM_8064_CTRL_ACK_SEL_0 + 7,
};
/* RPM resource select enums defined for RPM core
NOT IN SEQUENTIAL ORDER */
enum {
MSM_RPM_8064_SEL_NOTIFICATION = 0,
MSM_RPM_8064_SEL_INVALIDATE = 1,
MSM_RPM_8064_SEL_TRIGGER_TIMED = 2,
MSM_RPM_8064_SEL_RPM_CTL = 3,
MSM_RPM_8064_SEL_CXO_CLK = 5,
MSM_RPM_8064_SEL_PXO_CLK = 6,
MSM_RPM_8064_SEL_QDSS_CLK = 7,
MSM_RPM_8064_SEL_APPS_FABRIC_CLK = 8,
MSM_RPM_8064_SEL_SYSTEM_FABRIC_CLK = 9,
MSM_RPM_8064_SEL_MM_FABRIC_CLK = 10,
MSM_RPM_8064_SEL_DAYTONA_FABRIC_CLK = 11,
MSM_RPM_8064_SEL_SFPB_CLK = 12,
MSM_RPM_8064_SEL_CFPB_CLK = 13,
MSM_RPM_8064_SEL_MMFPB_CLK = 14,
MSM_RPM_8064_SEL_EBI1_CLK = 16,
MSM_RPM_8064_SEL_APPS_FABRIC_CFG_HALT = 18,
MSM_RPM_8064_SEL_APPS_FABRIC_CFG_CLKMOD = 19,
MSM_RPM_8064_SEL_APPS_FABRIC_CFG_IOCTL = 20,
MSM_RPM_8064_SEL_APPS_FABRIC_ARB = 21,
MSM_RPM_8064_SEL_SYS_FABRIC_CFG_HALT = 22,
MSM_RPM_8064_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
MSM_RPM_8064_SEL_SYS_FABRIC_CFG_IOCTL = 24,
MSM_RPM_8064_SEL_SYSTEM_FABRIC_ARB = 25,
MSM_RPM_8064_SEL_MMSS_FABRIC_CFG_HALT = 26,
MSM_RPM_8064_SEL_MMSS_FABRIC_CFG_CLKMOD = 27,
MSM_RPM_8064_SEL_MMSS_FABRIC_CFG_IOCTL = 28,
MSM_RPM_8064_SEL_MM_FABRIC_ARB = 29,
MSM_RPM_8064_SEL_PM8921_S1 = 30,
MSM_RPM_8064_SEL_PM8921_S2 = 31,
MSM_RPM_8064_SEL_PM8921_S3 = 32,
MSM_RPM_8064_SEL_PM8921_S4 = 33,
MSM_RPM_8064_SEL_PM8921_S5 = 34,
MSM_RPM_8064_SEL_PM8921_S6 = 35,
MSM_RPM_8064_SEL_PM8921_S7 = 36,
MSM_RPM_8064_SEL_PM8921_S8 = 37,
MSM_RPM_8064_SEL_PM8921_L1 = 38,
MSM_RPM_8064_SEL_PM8921_L2 = 39,
MSM_RPM_8064_SEL_PM8921_L3 = 40,
MSM_RPM_8064_SEL_PM8921_L4 = 41,
MSM_RPM_8064_SEL_PM8921_L5 = 42,
MSM_RPM_8064_SEL_PM8921_L6 = 43,
MSM_RPM_8064_SEL_PM8921_L7 = 44,
MSM_RPM_8064_SEL_PM8921_L8 = 45,
MSM_RPM_8064_SEL_PM8921_L9 = 46,
MSM_RPM_8064_SEL_PM8921_L10 = 47,
MSM_RPM_8064_SEL_PM8921_L11 = 48,
MSM_RPM_8064_SEL_PM8921_L12 = 49,
MSM_RPM_8064_SEL_PM8921_L13 = 50,
MSM_RPM_8064_SEL_PM8921_L14 = 51,
MSM_RPM_8064_SEL_PM8921_L15 = 52,
MSM_RPM_8064_SEL_PM8921_L16 = 53,
MSM_RPM_8064_SEL_PM8921_L17 = 54,
MSM_RPM_8064_SEL_PM8921_L18 = 55,
MSM_RPM_8064_SEL_PM8921_L19 = 56,
MSM_RPM_8064_SEL_PM8921_L20 = 57,
MSM_RPM_8064_SEL_PM8921_L21 = 58,
MSM_RPM_8064_SEL_PM8921_L22 = 59,
MSM_RPM_8064_SEL_PM8921_L23 = 60,
MSM_RPM_8064_SEL_PM8921_L24 = 61,
MSM_RPM_8064_SEL_PM8921_L25 = 62,
MSM_RPM_8064_SEL_PM8921_L26 = 63,
MSM_RPM_8064_SEL_PM8921_L27 = 64,
MSM_RPM_8064_SEL_PM8921_L28 = 65,
MSM_RPM_8064_SEL_PM8921_L29 = 66,
MSM_RPM_8064_SEL_PM8921_CLK1 = 67,
MSM_RPM_8064_SEL_PM8921_CLK2 = 68,
MSM_RPM_8064_SEL_PM8921_LVS1 = 69,
MSM_RPM_8064_SEL_PM8921_LVS2 = 70,
MSM_RPM_8064_SEL_PM8921_LVS3 = 71,
MSM_RPM_8064_SEL_PM8921_LVS4 = 72,
MSM_RPM_8064_SEL_PM8921_LVS5 = 73,
MSM_RPM_8064_SEL_PM8921_LVS6 = 74,
MSM_RPM_8064_SEL_PM8921_LVS7 = 75,
MSM_RPM_8064_SEL_PM8821_S1 = 76,
MSM_RPM_8064_SEL_PM8821_S2 = 77,
MSM_RPM_8064_SEL_PM8821_L1 = 78,
MSM_RPM_8064_SEL_NCP = 80,
MSM_RPM_8064_SEL_CXO_BUFFERS = 81,
MSM_RPM_8064_SEL_USB_OTG_SWITCH = 82,
MSM_RPM_8064_SEL_HDMI_SWITCH = 83,
MSM_RPM_8064_SEL_DDR_DMM = 84,
MSM_RPM_8064_SEL_LAST = MSM_RPM_8064_SEL_DDR_DMM,
};
/* RPM resource (4 byte) word ID enum */
enum {
MSM_RPM_8064_ID_NOTIFICATION_CONFIGURED_0 = 0,
MSM_RPM_8064_ID_NOTIFICATION_CONFIGURED_3 =
MSM_RPM_8064_ID_NOTIFICATION_CONFIGURED_0 + 3,
MSM_RPM_8064_ID_NOTIFICATION_REGISTERED_0 = 4,
MSM_RPM_8064_ID_NOTIFICATION_REGISTERED_3 =
MSM_RPM_8064_ID_NOTIFICATION_REGISTERED_0 + 3,
MSM_RPM_8064_ID_INVALIDATE_0 = 8,
MSM_RPM_8064_ID_INVALIDATE_7 =
MSM_RPM_8064_ID_INVALIDATE_0 + 7,
MSM_RPM_8064_ID_TRIGGER_TIMED_TO = 16,
MSM_RPM_8064_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
MSM_RPM_8064_ID_RPM_CTL = 18,
/* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
MSM_RPM_8064_ID_RESERVED_0 = 19,
MSM_RPM_8064_ID_RESERVED_5 =
MSM_RPM_8064_ID_RESERVED_0 + 5,
MSM_RPM_8064_ID_CXO_CLK = 25,
MSM_RPM_8064_ID_PXO_CLK = 26,
MSM_RPM_8064_ID_APPS_FABRIC_CLK = 27,
MSM_RPM_8064_ID_SYSTEM_FABRIC_CLK = 28,
MSM_RPM_8064_ID_MM_FABRIC_CLK = 29,
MSM_RPM_8064_ID_DAYTONA_FABRIC_CLK = 30,
MSM_RPM_8064_ID_SFPB_CLK = 31,
MSM_RPM_8064_ID_CFPB_CLK = 32,
MSM_RPM_8064_ID_MMFPB_CLK = 33,
MSM_RPM_8064_ID_EBI1_CLK = 34,
MSM_RPM_8064_ID_APPS_FABRIC_CFG_HALT_0 = 35,
MSM_RPM_8064_ID_APPS_FABRIC_CFG_HALT_1 = 36,
MSM_RPM_8064_ID_APPS_FABRIC_CFG_CLKMOD_0 = 37,
MSM_RPM_8064_ID_APPS_FABRIC_CFG_CLKMOD_1 = 38,
MSM_RPM_8064_ID_APPS_FABRIC_CFG_CLKMOD_2 = 39,
MSM_RPM_8064_ID_APPS_FABRIC_CFG_IOCTL = 40,
MSM_RPM_8064_ID_APPS_FABRIC_ARB_0 = 41,
MSM_RPM_8064_ID_APPS_FABRIC_ARB_11 =
MSM_RPM_8064_ID_APPS_FABRIC_ARB_0 + 11,
MSM_RPM_8064_ID_SYS_FABRIC_CFG_HALT_0 = 53,
MSM_RPM_8064_ID_SYS_FABRIC_CFG_HALT_1 = 54,
MSM_RPM_8064_ID_SYS_FABRIC_CFG_CLKMOD_0 = 55,
MSM_RPM_8064_ID_SYS_FABRIC_CFG_CLKMOD_1 = 56,
MSM_RPM_8064_ID_SYS_FABRIC_CFG_CLKMOD_2 = 57,
MSM_RPM_8064_ID_SYS_FABRIC_CFG_IOCTL = 58,
MSM_RPM_8064_ID_SYSTEM_FABRIC_ARB_0 = 59,
MSM_RPM_8064_ID_SYSTEM_FABRIC_ARB_29 =
MSM_RPM_8064_ID_SYSTEM_FABRIC_ARB_0 + 29,
MSM_RPM_8064_ID_MMSS_FABRIC_CFG_HALT_0 = 89,
MSM_RPM_8064_ID_MMSS_FABRIC_CFG_HALT_1 = 90,
MSM_RPM_8064_ID_MMSS_FABRIC_CFG_CLKMOD_0 = 91,
MSM_RPM_8064_ID_MMSS_FABRIC_CFG_CLKMOD_1 = 92,
MSM_RPM_8064_ID_MMSS_FABRIC_CFG_CLKMOD_2 = 93,
MSM_RPM_8064_ID_MMSS_FABRIC_CFG_IOCTL = 94,
MSM_RPM_8064_ID_MM_FABRIC_ARB_0 = 95,
MSM_RPM_8064_ID_MM_FABRIC_ARB_20 =
MSM_RPM_8064_ID_MM_FABRIC_ARB_0 + 20,
MSM_RPM_8064_ID_PM8921_S1_0 = 116,
MSM_RPM_8064_ID_PM8921_S1_1 = 117,
MSM_RPM_8064_ID_PM8921_S2_0 = 118,
MSM_RPM_8064_ID_PM8921_S2_1 = 119,
MSM_RPM_8064_ID_PM8921_S3_0 = 120,
MSM_RPM_8064_ID_PM8921_S3_1 = 121,
MSM_RPM_8064_ID_PM8921_S4_0 = 122,
MSM_RPM_8064_ID_PM8921_S4_1 = 123,
MSM_RPM_8064_ID_PM8921_S5_0 = 124,
MSM_RPM_8064_ID_PM8921_S5_1 = 125,
MSM_RPM_8064_ID_PM8921_S6_0 = 126,
MSM_RPM_8064_ID_PM8921_S6_1 = 127,
MSM_RPM_8064_ID_PM8921_S7_0 = 128,
MSM_RPM_8064_ID_PM8921_S7_1 = 129,
MSM_RPM_8064_ID_PM8921_S8_0 = 130,
MSM_RPM_8064_ID_PM8921_S8_1 = 131,
MSM_RPM_8064_ID_PM8921_L1_0 = 132,
MSM_RPM_8064_ID_PM8921_L1_1 = 133,
MSM_RPM_8064_ID_PM8921_L2_0 = 134,
MSM_RPM_8064_ID_PM8921_L2_1 = 135,
MSM_RPM_8064_ID_PM8921_L3_0 = 136,
MSM_RPM_8064_ID_PM8921_L3_1 = 137,
MSM_RPM_8064_ID_PM8921_L4_0 = 138,
MSM_RPM_8064_ID_PM8921_L4_1 = 139,
MSM_RPM_8064_ID_PM8921_L5_0 = 140,
MSM_RPM_8064_ID_PM8921_L5_1 = 141,
MSM_RPM_8064_ID_PM8921_L6_0 = 142,
MSM_RPM_8064_ID_PM8921_L6_1 = 143,
MSM_RPM_8064_ID_PM8921_L7_0 = 144,
MSM_RPM_8064_ID_PM8921_L7_1 = 145,
MSM_RPM_8064_ID_PM8921_L8_0 = 146,
MSM_RPM_8064_ID_PM8921_L8_1 = 147,
MSM_RPM_8064_ID_PM8921_L9_0 = 148,
MSM_RPM_8064_ID_PM8921_L9_1 = 149,
MSM_RPM_8064_ID_PM8921_L10_0 = 150,
MSM_RPM_8064_ID_PM8921_L10_1 = 151,
MSM_RPM_8064_ID_PM8921_L11_0 = 152,
MSM_RPM_8064_ID_PM8921_L11_1 = 153,
MSM_RPM_8064_ID_PM8921_L12_0 = 154,
MSM_RPM_8064_ID_PM8921_L12_1 = 155,
MSM_RPM_8064_ID_PM8921_L13_0 = 156,
MSM_RPM_8064_ID_PM8921_L13_1 = 157,
MSM_RPM_8064_ID_PM8921_L14_0 = 158,
MSM_RPM_8064_ID_PM8921_L14_1 = 159,
MSM_RPM_8064_ID_PM8921_L15_0 = 160,
MSM_RPM_8064_ID_PM8921_L15_1 = 161,
MSM_RPM_8064_ID_PM8921_L16_0 = 162,
MSM_RPM_8064_ID_PM8921_L16_1 = 163,
MSM_RPM_8064_ID_PM8921_L17_0 = 164,
MSM_RPM_8064_ID_PM8921_L17_1 = 165,
MSM_RPM_8064_ID_PM8921_L18_0 = 166,
MSM_RPM_8064_ID_PM8921_L18_1 = 167,
MSM_RPM_8064_ID_PM8921_L19_0 = 168,
MSM_RPM_8064_ID_PM8921_L19_1 = 169,
MSM_RPM_8064_ID_PM8921_L20_0 = 170,
MSM_RPM_8064_ID_PM8921_L20_1 = 171,
MSM_RPM_8064_ID_PM8921_L21_0 = 172,
MSM_RPM_8064_ID_PM8921_L21_1 = 173,
MSM_RPM_8064_ID_PM8921_L22_0 = 174,
MSM_RPM_8064_ID_PM8921_L22_1 = 175,
MSM_RPM_8064_ID_PM8921_L23_0 = 176,
MSM_RPM_8064_ID_PM8921_L23_1 = 177,
MSM_RPM_8064_ID_PM8921_L24_0 = 178,
MSM_RPM_8064_ID_PM8921_L24_1 = 179,
MSM_RPM_8064_ID_PM8921_L25_0 = 180,
MSM_RPM_8064_ID_PM8921_L25_1 = 181,
MSM_RPM_8064_ID_PM8921_L26_0 = 182,
MSM_RPM_8064_ID_PM8921_L26_1 = 183,
MSM_RPM_8064_ID_PM8921_L27_0 = 184,
MSM_RPM_8064_ID_PM8921_L27_1 = 185,
MSM_RPM_8064_ID_PM8921_L28_0 = 186,
MSM_RPM_8064_ID_PM8921_L28_1 = 187,
MSM_RPM_8064_ID_PM8921_L29_0 = 188,
MSM_RPM_8064_ID_PM8921_L29_1 = 189,
MSM_RPM_8064_ID_PM8921_CLK1_0 = 190,
MSM_RPM_8064_ID_PM8921_CLK1_1 = 191,
MSM_RPM_8064_ID_PM8921_CLK2_0 = 192,
MSM_RPM_8064_ID_PM8921_CLK2_1 = 193,
MSM_RPM_8064_ID_PM8921_LVS1 = 194,
MSM_RPM_8064_ID_PM8921_LVS2 = 195,
MSM_RPM_8064_ID_PM8921_LVS3 = 196,
MSM_RPM_8064_ID_PM8921_LVS4 = 197,
MSM_RPM_8064_ID_PM8921_LVS5 = 198,
MSM_RPM_8064_ID_PM8921_LVS6 = 199,
MSM_RPM_8064_ID_PM8921_LVS7 = 200,
MSM_RPM_8064_ID_PM8821_S1_0 = 201,
MSM_RPM_8064_ID_PM8821_S1_1 = 202,
MSM_RPM_8064_ID_PM8821_S2_0 = 203,
MSM_RPM_8064_ID_PM8821_S2_1 = 204,
MSM_RPM_8064_ID_PM8821_L1_0 = 205,
MSM_RPM_8064_ID_PM8821_L1_1 = 206,
MSM_RPM_8064_ID_NCP_0 = 207,
MSM_RPM_8064_ID_NCP_1 = 208,
MSM_RPM_8064_ID_CXO_BUFFERS = 209,
MSM_RPM_8064_ID_USB_OTG_SWITCH = 210,
MSM_RPM_8064_ID_HDMI_SWITCH = 211,
MSM_RPM_8064_ID_DDR_DMM_0 = 212,
MSM_RPM_8064_ID_DDR_DMM_1 = 213,
MSM_RPM_8064_ID_QDSS_CLK = 214,
MSM_RPM_8064_ID_LAST = MSM_RPM_8064_ID_QDSS_CLK,
};
/* RPM status ID enum */
enum {
MSM_RPM_8064_STATUS_ID_VERSION_MAJOR = 0,
MSM_RPM_8064_STATUS_ID_VERSION_MINOR = 1,
MSM_RPM_8064_STATUS_ID_VERSION_BUILD = 2,
MSM_RPM_8064_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
MSM_RPM_8064_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
MSM_RPM_8064_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
MSM_RPM_8064_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
MSM_RPM_8064_STATUS_ID_SEQUENCE = 7,
MSM_RPM_8064_STATUS_ID_RPM_CTL = 8,
MSM_RPM_8064_STATUS_ID_CXO_CLK = 9,
MSM_RPM_8064_STATUS_ID_PXO_CLK = 10,
MSM_RPM_8064_STATUS_ID_APPS_FABRIC_CLK = 11,
MSM_RPM_8064_STATUS_ID_SYSTEM_FABRIC_CLK = 12,
MSM_RPM_8064_STATUS_ID_MM_FABRIC_CLK = 13,
MSM_RPM_8064_STATUS_ID_DAYTONA_FABRIC_CLK = 14,
MSM_RPM_8064_STATUS_ID_SFPB_CLK = 15,
MSM_RPM_8064_STATUS_ID_CFPB_CLK = 16,
MSM_RPM_8064_STATUS_ID_MMFPB_CLK = 17,
MSM_RPM_8064_STATUS_ID_EBI1_CLK = 18,
MSM_RPM_8064_STATUS_ID_APPS_FABRIC_CFG_HALT = 19,
MSM_RPM_8064_STATUS_ID_APPS_FABRIC_CFG_CLKMOD = 20,
MSM_RPM_8064_STATUS_ID_APPS_FABRIC_CFG_IOCTL = 21,
MSM_RPM_8064_STATUS_ID_APPS_FABRIC_ARB = 22,
MSM_RPM_8064_STATUS_ID_SYS_FABRIC_CFG_HALT = 23,
MSM_RPM_8064_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 24,
MSM_RPM_8064_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 25,
MSM_RPM_8064_STATUS_ID_SYSTEM_FABRIC_ARB = 26,
MSM_RPM_8064_STATUS_ID_MMSS_FABRIC_CFG_HALT = 27,
MSM_RPM_8064_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD = 28,
MSM_RPM_8064_STATUS_ID_MMSS_FABRIC_CFG_IOCTL = 29,
MSM_RPM_8064_STATUS_ID_MM_FABRIC_ARB = 30,
MSM_RPM_8064_STATUS_ID_PM8921_S1_0 = 31,
MSM_RPM_8064_STATUS_ID_PM8921_S1_1 = 32,
MSM_RPM_8064_STATUS_ID_PM8921_S2_0 = 33,
MSM_RPM_8064_STATUS_ID_PM8921_S2_1 = 34,
MSM_RPM_8064_STATUS_ID_PM8921_S3_0 = 35,
MSM_RPM_8064_STATUS_ID_PM8921_S3_1 = 36,
MSM_RPM_8064_STATUS_ID_PM8921_S4_0 = 37,
MSM_RPM_8064_STATUS_ID_PM8921_S4_1 = 38,
MSM_RPM_8064_STATUS_ID_PM8921_S5_0 = 39,
MSM_RPM_8064_STATUS_ID_PM8921_S5_1 = 40,
MSM_RPM_8064_STATUS_ID_PM8921_S6_0 = 41,
MSM_RPM_8064_STATUS_ID_PM8921_S6_1 = 42,
MSM_RPM_8064_STATUS_ID_PM8921_S7_0 = 43,
MSM_RPM_8064_STATUS_ID_PM8921_S7_1 = 44,
MSM_RPM_8064_STATUS_ID_PM8921_S8_0 = 45,
MSM_RPM_8064_STATUS_ID_PM8921_S8_1 = 46,
MSM_RPM_8064_STATUS_ID_PM8921_L1_0 = 47,
MSM_RPM_8064_STATUS_ID_PM8921_L1_1 = 48,
MSM_RPM_8064_STATUS_ID_PM8921_L2_0 = 49,
MSM_RPM_8064_STATUS_ID_PM8921_L2_1 = 50,
MSM_RPM_8064_STATUS_ID_PM8921_L3_0 = 51,
MSM_RPM_8064_STATUS_ID_PM8921_L3_1 = 52,
MSM_RPM_8064_STATUS_ID_PM8921_L4_0 = 53,
MSM_RPM_8064_STATUS_ID_PM8921_L4_1 = 54,
MSM_RPM_8064_STATUS_ID_PM8921_L5_0 = 55,
MSM_RPM_8064_STATUS_ID_PM8921_L5_1 = 56,
MSM_RPM_8064_STATUS_ID_PM8921_L6_0 = 57,
MSM_RPM_8064_STATUS_ID_PM8921_L6_1 = 58,
MSM_RPM_8064_STATUS_ID_PM8921_L7_0 = 59,
MSM_RPM_8064_STATUS_ID_PM8921_L7_1 = 60,
MSM_RPM_8064_STATUS_ID_PM8921_L8_0 = 61,
MSM_RPM_8064_STATUS_ID_PM8921_L8_1 = 62,
MSM_RPM_8064_STATUS_ID_PM8921_L9_0 = 63,
MSM_RPM_8064_STATUS_ID_PM8921_L9_1 = 64,
MSM_RPM_8064_STATUS_ID_PM8921_L10_0 = 65,
MSM_RPM_8064_STATUS_ID_PM8921_L10_1 = 66,
MSM_RPM_8064_STATUS_ID_PM8921_L11_0 = 67,
MSM_RPM_8064_STATUS_ID_PM8921_L11_1 = 68,
MSM_RPM_8064_STATUS_ID_PM8921_L12_0 = 69,
MSM_RPM_8064_STATUS_ID_PM8921_L12_1 = 70,
MSM_RPM_8064_STATUS_ID_PM8921_L13_0 = 71,
MSM_RPM_8064_STATUS_ID_PM8921_L13_1 = 72,
MSM_RPM_8064_STATUS_ID_PM8921_L14_0 = 73,
MSM_RPM_8064_STATUS_ID_PM8921_L14_1 = 74,
MSM_RPM_8064_STATUS_ID_PM8921_L15_0 = 75,
MSM_RPM_8064_STATUS_ID_PM8921_L15_1 = 76,
MSM_RPM_8064_STATUS_ID_PM8921_L16_0 = 77,
MSM_RPM_8064_STATUS_ID_PM8921_L16_1 = 78,
MSM_RPM_8064_STATUS_ID_PM8921_L17_0 = 79,
MSM_RPM_8064_STATUS_ID_PM8921_L17_1 = 80,
MSM_RPM_8064_STATUS_ID_PM8921_L18_0 = 81,
MSM_RPM_8064_STATUS_ID_PM8921_L18_1 = 82,
MSM_RPM_8064_STATUS_ID_PM8921_L19_0 = 83,
MSM_RPM_8064_STATUS_ID_PM8921_L19_1 = 84,
MSM_RPM_8064_STATUS_ID_PM8921_L20_0 = 85,
MSM_RPM_8064_STATUS_ID_PM8921_L20_1 = 86,
MSM_RPM_8064_STATUS_ID_PM8921_L21_0 = 87,
MSM_RPM_8064_STATUS_ID_PM8921_L21_1 = 88,
MSM_RPM_8064_STATUS_ID_PM8921_L22_0 = 89,
MSM_RPM_8064_STATUS_ID_PM8921_L22_1 = 90,
MSM_RPM_8064_STATUS_ID_PM8921_L23_0 = 91,
MSM_RPM_8064_STATUS_ID_PM8921_L23_1 = 92,
MSM_RPM_8064_STATUS_ID_PM8921_L24_0 = 93,
MSM_RPM_8064_STATUS_ID_PM8921_L24_1 = 94,
MSM_RPM_8064_STATUS_ID_PM8921_L25_0 = 95,
MSM_RPM_8064_STATUS_ID_PM8921_L25_1 = 96,
MSM_RPM_8064_STATUS_ID_PM8921_L26_0 = 97,
MSM_RPM_8064_STATUS_ID_PM8921_L26_1 = 98,
MSM_RPM_8064_STATUS_ID_PM8921_L27_0 = 99,
MSM_RPM_8064_STATUS_ID_PM8921_L27_1 = 100,
MSM_RPM_8064_STATUS_ID_PM8921_L28_0 = 101,
MSM_RPM_8064_STATUS_ID_PM8921_L28_1 = 102,
MSM_RPM_8064_STATUS_ID_PM8921_L29_0 = 103,
MSM_RPM_8064_STATUS_ID_PM8921_L29_1 = 104,
MSM_RPM_8064_STATUS_ID_PM8921_CLK1_0 = 105,
MSM_RPM_8064_STATUS_ID_PM8921_CLK1_1 = 106,
MSM_RPM_8064_STATUS_ID_PM8921_CLK2_0 = 107,
MSM_RPM_8064_STATUS_ID_PM8921_CLK2_1 = 108,
MSM_RPM_8064_STATUS_ID_PM8921_LVS1 = 109,
MSM_RPM_8064_STATUS_ID_PM8921_LVS2 = 110,
MSM_RPM_8064_STATUS_ID_PM8921_LVS3 = 111,
MSM_RPM_8064_STATUS_ID_PM8921_LVS4 = 112,
MSM_RPM_8064_STATUS_ID_PM8921_LVS5 = 113,
MSM_RPM_8064_STATUS_ID_PM8921_LVS6 = 114,
MSM_RPM_8064_STATUS_ID_PM8921_LVS7 = 115,
MSM_RPM_8064_STATUS_ID_PM8821_S1_0 = 116,
MSM_RPM_8064_STATUS_ID_PM8821_S1_1 = 117,
MSM_RPM_8064_STATUS_ID_PM8821_S2_0 = 118,
MSM_RPM_8064_STATUS_ID_PM8821_S2_1 = 119,
MSM_RPM_8064_STATUS_ID_PM8821_L1_0 = 120,
MSM_RPM_8064_STATUS_ID_PM8821_L1_1 = 121,
MSM_RPM_8064_STATUS_ID_NCP_0 = 122,
MSM_RPM_8064_STATUS_ID_NCP_1 = 123,
MSM_RPM_8064_STATUS_ID_CXO_BUFFERS = 124,
MSM_RPM_8064_STATUS_ID_USB_OTG_SWITCH = 125,
MSM_RPM_8064_STATUS_ID_HDMI_SWITCH = 126,
MSM_RPM_8064_STATUS_ID_DDR_DMM_0 = 127,
MSM_RPM_8064_STATUS_ID_DDR_DMM_1 = 128,
MSM_RPM_8064_STATUS_ID_EBI1_CH0_RANGE = 129,
MSM_RPM_8064_STATUS_ID_EBI1_CH1_RANGE = 130,
MSM_RPM_8064_STATUS_ID_LAST = MSM_RPM_8064_STATUS_ID_EBI1_CH1_RANGE,
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_8064_H */

802
arch/arm/mach-msm/include/mach/rpm-8660.h
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -13,469 +13,443 @@
#ifndef __ARCH_ARM_MACH_MSM_RPM_8660_H
#define __ARCH_ARM_MACH_MSM_RPM_8660_H
#define RPM_MAJOR_VER 2
#define RPM_MINOR_VER 0
#define RPM_BUILD_VER 0
/* RPM control message RAM enums */
enum {
MSM_RPM_CTRL_VERSION_MAJOR,
MSM_RPM_CTRL_VERSION_MINOR,
MSM_RPM_CTRL_VERSION_BUILD,
MSM_RPM_8660_CTRL_VERSION_MAJOR,
MSM_RPM_8660_CTRL_VERSION_MINOR,
MSM_RPM_8660_CTRL_VERSION_BUILD,
MSM_RPM_CTRL_REQ_CTX_0,
MSM_RPM_CTRL_REQ_CTX_7 = MSM_RPM_CTRL_REQ_CTX_0 + 7,
MSM_RPM_CTRL_REQ_SEL_0,
MSM_RPM_CTRL_REQ_SEL_7 = MSM_RPM_CTRL_REQ_SEL_0 + 7,
MSM_RPM_CTRL_ACK_CTX_0,
MSM_RPM_CTRL_ACK_CTX_7 = MSM_RPM_CTRL_ACK_CTX_0 + 7,
MSM_RPM_CTRL_ACK_SEL_0,
MSM_RPM_CTRL_ACK_SEL_7 = MSM_RPM_CTRL_ACK_SEL_0 + 7,
MSM_RPM_8660_CTRL_REQ_CTX_0,
MSM_RPM_8660_CTRL_REQ_CTX_7 = MSM_RPM_8660_CTRL_REQ_CTX_0 + 7,
MSM_RPM_8660_CTRL_REQ_SEL_0,
MSM_RPM_8660_CTRL_REQ_SEL_7 = MSM_RPM_8660_CTRL_REQ_SEL_0 + 7,
MSM_RPM_8660_CTRL_ACK_CTX_0,
MSM_RPM_8660_CTRL_ACK_CTX_7 = MSM_RPM_8660_CTRL_ACK_CTX_0 + 7,
MSM_RPM_8660_CTRL_ACK_SEL_0,
MSM_RPM_8660_CTRL_ACK_SEL_7 = MSM_RPM_8660_CTRL_ACK_SEL_0 + 7,
};
enum {
MSM_RPM_SEL_NOTIFICATION,
MSM_RPM_SEL_INVALIDATE,
MSM_RPM_SEL_TRIGGER_TIMED,
MSM_RPM_SEL_TRIGGER_SET,
MSM_RPM_SEL_TRIGGER_CLEAR,
MSM_RPM_8660_SEL_NOTIFICATION,
MSM_RPM_8660_SEL_INVALIDATE,
MSM_RPM_8660_SEL_TRIGGER_TIMED,
MSM_RPM_8660_SEL_TRIGGER_SET,
MSM_RPM_8660_SEL_TRIGGER_CLEAR,
MSM_RPM_SEL_CXO_CLK,
MSM_RPM_SEL_PXO_CLK,
MSM_RPM_SEL_PLL_4,
MSM_RPM_SEL_APPS_FABRIC_CLK,
MSM_RPM_SEL_SYSTEM_FABRIC_CLK,
MSM_RPM_SEL_MM_FABRIC_CLK,
MSM_RPM_SEL_DAYTONA_FABRIC_CLK,
MSM_RPM_SEL_SFPB_CLK,
MSM_RPM_SEL_CFPB_CLK,
MSM_RPM_SEL_MMFPB_CLK,
MSM_RPM_SEL_SMI_CLK,
MSM_RPM_SEL_EBI1_CLK,
MSM_RPM_8660_SEL_CXO_CLK,
MSM_RPM_8660_SEL_PXO_CLK,
MSM_RPM_8660_SEL_PLL_4,
MSM_RPM_8660_SEL_APPS_FABRIC_CLK,
MSM_RPM_8660_SEL_SYSTEM_FABRIC_CLK,
MSM_RPM_8660_SEL_MM_FABRIC_CLK,
MSM_RPM_8660_SEL_DAYTONA_FABRIC_CLK,
MSM_RPM_8660_SEL_SFPB_CLK,
MSM_RPM_8660_SEL_CFPB_CLK,
MSM_RPM_8660_SEL_MMFPB_CLK,
MSM_RPM_8660_SEL_SMI_CLK,
MSM_RPM_8660_SEL_EBI1_CLK,
MSM_RPM_SEL_APPS_L2_CACHE_CTL,
MSM_RPM_8660_SEL_APPS_L2_CACHE_CTL,
MSM_RPM_SEL_APPS_FABRIC_HALT,
MSM_RPM_SEL_APPS_FABRIC_CLOCK_MODE,
MSM_RPM_SEL_APPS_FABRIC_IOCTL,
MSM_RPM_SEL_APPS_FABRIC_ARB,
MSM_RPM_8660_SEL_APPS_FABRIC_HALT,
MSM_RPM_8660_SEL_APPS_FABRIC_CLOCK_MODE,
MSM_RPM_8660_SEL_APPS_FABRIC_IOCTL,
MSM_RPM_8660_SEL_APPS_FABRIC_ARB,
MSM_RPM_SEL_SYSTEM_FABRIC_HALT,
MSM_RPM_SEL_SYSTEM_FABRIC_CLOCK_MODE,
MSM_RPM_SEL_SYSTEM_FABRIC_IOCTL,
MSM_RPM_SEL_SYSTEM_FABRIC_ARB,
MSM_RPM_8660_SEL_SYSTEM_FABRIC_HALT,
MSM_RPM_8660_SEL_SYSTEM_FABRIC_CLOCK_MODE,
MSM_RPM_8660_SEL_SYSTEM_FABRIC_IOCTL,
MSM_RPM_8660_SEL_SYSTEM_FABRIC_ARB,
MSM_RPM_SEL_MM_FABRIC_HALT,
MSM_RPM_SEL_MM_FABRIC_CLOCK_MODE,
MSM_RPM_SEL_MM_FABRIC_IOCTL,
MSM_RPM_SEL_MM_FABRIC_ARB,
MSM_RPM_8660_SEL_MM_FABRIC_HALT,
MSM_RPM_8660_SEL_MM_FABRIC_CLOCK_MODE,
MSM_RPM_8660_SEL_MM_FABRIC_IOCTL,
MSM_RPM_8660_SEL_MM_FABRIC_ARB,
MSM_RPM_SEL_SMPS0B,
MSM_RPM_SEL_SMPS1B,
MSM_RPM_SEL_SMPS2B,
MSM_RPM_SEL_SMPS3B,
MSM_RPM_SEL_SMPS4B,
MSM_RPM_SEL_LDO0B,
MSM_RPM_SEL_LDO1B,
MSM_RPM_SEL_LDO2B,
MSM_RPM_SEL_LDO3B,
MSM_RPM_SEL_LDO4B,
MSM_RPM_SEL_LDO5B,
MSM_RPM_SEL_LDO6B,
MSM_RPM_SEL_LVS0B,
MSM_RPM_SEL_LVS1B,
MSM_RPM_SEL_LVS2B,
MSM_RPM_SEL_LVS3B,
MSM_RPM_SEL_MVS,
MSM_RPM_8660_SEL_SMPS0B,
MSM_RPM_8660_SEL_SMPS1B,
MSM_RPM_8660_SEL_SMPS2B,
MSM_RPM_8660_SEL_SMPS3B,
MSM_RPM_8660_SEL_SMPS4B,
MSM_RPM_8660_SEL_LDO0B,
MSM_RPM_8660_SEL_LDO1B,
MSM_RPM_8660_SEL_LDO2B,
MSM_RPM_8660_SEL_LDO3B,
MSM_RPM_8660_SEL_LDO4B,
MSM_RPM_8660_SEL_LDO5B,
MSM_RPM_8660_SEL_LDO6B,
MSM_RPM_8660_SEL_LVS0B,
MSM_RPM_8660_SEL_LVS1B,
MSM_RPM_8660_SEL_LVS2B,
MSM_RPM_8660_SEL_LVS3B,
MSM_RPM_8660_SEL_MVS,
MSM_RPM_SEL_SMPS0,
MSM_RPM_SEL_SMPS1,
MSM_RPM_SEL_SMPS2,
MSM_RPM_SEL_SMPS3,
MSM_RPM_SEL_SMPS4,
MSM_RPM_8660_SEL_SMPS0,
MSM_RPM_8660_SEL_SMPS1,
MSM_RPM_8660_SEL_SMPS2,
MSM_RPM_8660_SEL_SMPS3,
MSM_RPM_8660_SEL_SMPS4,
MSM_RPM_SEL_LDO0,
MSM_RPM_SEL_LDO1,
MSM_RPM_SEL_LDO2,
MSM_RPM_SEL_LDO3,
MSM_RPM_SEL_LDO4,
MSM_RPM_SEL_LDO5,
MSM_RPM_SEL_LDO6,
MSM_RPM_SEL_LDO7,
MSM_RPM_SEL_LDO8,
MSM_RPM_SEL_LDO9,
MSM_RPM_SEL_LDO10,
MSM_RPM_SEL_LDO11,
MSM_RPM_SEL_LDO12,
MSM_RPM_SEL_LDO13,
MSM_RPM_SEL_LDO14,
MSM_RPM_SEL_LDO15,
MSM_RPM_SEL_LDO16,
MSM_RPM_SEL_LDO17,
MSM_RPM_SEL_LDO18,
MSM_RPM_SEL_LDO19,
MSM_RPM_SEL_LDO20,
MSM_RPM_SEL_LDO21,
MSM_RPM_SEL_LDO22,
MSM_RPM_SEL_LDO23,
MSM_RPM_SEL_LDO24,
MSM_RPM_SEL_LDO25,
MSM_RPM_SEL_LVS0,
MSM_RPM_SEL_LVS1,
MSM_RPM_SEL_NCP,
MSM_RPM_8660_SEL_LDO0,
MSM_RPM_8660_SEL_LDO1,
MSM_RPM_8660_SEL_LDO2,
MSM_RPM_8660_SEL_LDO3,
MSM_RPM_8660_SEL_LDO4,
MSM_RPM_8660_SEL_LDO5,
MSM_RPM_8660_SEL_LDO6,
MSM_RPM_8660_SEL_LDO7,
MSM_RPM_8660_SEL_LDO8,
MSM_RPM_8660_SEL_LDO9,
MSM_RPM_8660_SEL_LDO10,
MSM_RPM_8660_SEL_LDO11,
MSM_RPM_8660_SEL_LDO12,
MSM_RPM_8660_SEL_LDO13,
MSM_RPM_8660_SEL_LDO14,
MSM_RPM_8660_SEL_LDO15,
MSM_RPM_8660_SEL_LDO16,
MSM_RPM_8660_SEL_LDO17,
MSM_RPM_8660_SEL_LDO18,
MSM_RPM_8660_SEL_LDO19,
MSM_RPM_8660_SEL_LDO20,
MSM_RPM_8660_SEL_LDO21,
MSM_RPM_8660_SEL_LDO22,
MSM_RPM_8660_SEL_LDO23,
MSM_RPM_8660_SEL_LDO24,
MSM_RPM_8660_SEL_LDO25,
MSM_RPM_8660_SEL_LVS0,
MSM_RPM_8660_SEL_LVS1,
MSM_RPM_8660_SEL_NCP,
MSM_RPM_SEL_CXO_BUFFERS,
MSM_RPM_8660_SEL_CXO_BUFFERS,
MSM_RPM_SEL_LAST = MSM_RPM_SEL_CXO_BUFFERS,
MSM_RPM_8660_SEL_LAST = MSM_RPM_8660_SEL_CXO_BUFFERS,
};
enum {
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0,
MSM_RPM_ID_NOTIFICATION_CONFIGURED_7 =
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 7,
MSM_RPM_8660_ID_NOTIFICATION_CONFIGURED_0,
MSM_RPM_8660_ID_NOTIFICATION_CONFIGURED_7 =
MSM_RPM_8660_ID_NOTIFICATION_CONFIGURED_0 + 7,
MSM_RPM_ID_NOTIFICATION_REGISTERED_0,
MSM_RPM_ID_NOTIFICATION_REGISTERED_7 =
MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 7,
MSM_RPM_8660_ID_NOTIFICATION_REGISTERED_0,
MSM_RPM_8660_ID_NOTIFICATION_REGISTERED_7 =
MSM_RPM_8660_ID_NOTIFICATION_REGISTERED_0 + 7,
MSM_RPM_ID_INVALIDATE_0,
MSM_RPM_ID_INVALIDATE_7 = MSM_RPM_ID_INVALIDATE_0 + 7,
MSM_RPM_8660_ID_INVALIDATE_0,
MSM_RPM_8660_ID_INVALIDATE_7 =
MSM_RPM_8660_ID_INVALIDATE_0 + 7,
MSM_RPM_ID_TRIGGER_TIMED_TO,
MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT,
MSM_RPM_8660_ID_TRIGGER_TIMED_TO,
MSM_RPM_8660_ID_TRIGGER_TIMED_SCLK_COUNT,
MSM_RPM_ID_TRIGGER_SET_FROM,
MSM_RPM_ID_TRIGGER_SET_TO,
MSM_RPM_ID_TRIGGER_SET_TRIGGER,
MSM_RPM_8660_ID_TRIGGER_SET_FROM,
MSM_RPM_8660_ID_TRIGGER_SET_TO,
MSM_RPM_8660_ID_TRIGGER_SET_TRIGGER,
MSM_RPM_ID_TRIGGER_CLEAR_FROM,
MSM_RPM_ID_TRIGGER_CLEAR_TO,
MSM_RPM_ID_TRIGGER_CLEAR_TRIGGER,
MSM_RPM_8660_ID_TRIGGER_CLEAR_FROM,
MSM_RPM_8660_ID_TRIGGER_CLEAR_TO,
MSM_RPM_8660_ID_TRIGGER_CLEAR_TRIGGER,
MSM_RPM_ID_CXO_CLK,
MSM_RPM_ID_PXO_CLK,
MSM_RPM_ID_PLL_4,
MSM_RPM_ID_APPS_FABRIC_CLK,
MSM_RPM_ID_SYSTEM_FABRIC_CLK,
MSM_RPM_ID_MM_FABRIC_CLK,
MSM_RPM_ID_DAYTONA_FABRIC_CLK,
MSM_RPM_ID_SFPB_CLK,
MSM_RPM_ID_CFPB_CLK,
MSM_RPM_ID_MMFPB_CLK,
MSM_RPM_ID_SMI_CLK,
MSM_RPM_ID_EBI1_CLK,
MSM_RPM_8660_ID_CXO_CLK,
MSM_RPM_8660_ID_PXO_CLK,
MSM_RPM_8660_ID_PLL_4,
MSM_RPM_8660_ID_APPS_FABRIC_CLK,
MSM_RPM_8660_ID_SYSTEM_FABRIC_CLK,
MSM_RPM_8660_ID_MM_FABRIC_CLK,
MSM_RPM_8660_ID_DAYTONA_FABRIC_CLK,
MSM_RPM_8660_ID_SFPB_CLK,
MSM_RPM_8660_ID_CFPB_CLK,
MSM_RPM_8660_ID_MMFPB_CLK,
MSM_RPM_8660_ID_SMI_CLK,
MSM_RPM_8660_ID_EBI1_CLK,
MSM_RPM_ID_APPS_L2_CACHE_CTL,
MSM_RPM_8660_ID_APPS_L2_CACHE_CTL,
MSM_RPM_ID_APPS_FABRIC_HALT_0,
MSM_RPM_ID_APPS_FABRIC_HALT_1,
MSM_RPM_ID_APPS_FABRIC_CLOCK_MODE_0,
MSM_RPM_ID_APPS_FABRIC_CLOCK_MODE_1,
MSM_RPM_ID_APPS_FABRIC_CLOCK_MODE_2,
MSM_RPM_ID_APPS_FABRIC_RESERVED_A,
MSM_RPM_ID_APPS_FABRIC_ARB_0,
MSM_RPM_ID_APPS_FABRIC_ARB_5 = MSM_RPM_ID_APPS_FABRIC_ARB_0 + 5,
MSM_RPM_ID_APPS_FABRIC_RESERVED_B_0,
MSM_RPM_ID_APPS_FABRIC_RESERVED_B_5 =
MSM_RPM_ID_APPS_FABRIC_RESERVED_B_0 + 5,
MSM_RPM_8660_ID_APPS_FABRIC_HALT_0,
MSM_RPM_8660_ID_APPS_FABRIC_HALT_1,
MSM_RPM_8660_ID_APPS_FABRIC_CLOCK_MODE_0,
MSM_RPM_8660_ID_APPS_FABRIC_CLOCK_MODE_1,
MSM_RPM_8660_ID_APPS_FABRIC_CLOCK_MODE_2,
MSM_RPM_8660_ID_APPS_FABRIC_RESERVED_A,
MSM_RPM_8660_ID_APPS_FABRIC_ARB_0,
MSM_RPM_8660_ID_APPS_FABRIC_ARB_5 =
MSM_RPM_8660_ID_APPS_FABRIC_ARB_0 + 5,
MSM_RPM_8660_ID_APPS_FABRIC_RESERVED_B_0,
MSM_RPM_8660_ID_APPS_FABRIC_RESERVED_B_5 =
MSM_RPM_8660_ID_APPS_FABRIC_RESERVED_B_0 + 5,
MSM_RPM_ID_SYSTEM_FABRIC_HALT_0,
MSM_RPM_ID_SYSTEM_FABRIC_HALT_1,
MSM_RPM_ID_SYSTEM_FABRIC_CLOCK_MODE_0,
MSM_RPM_ID_SYSTEM_FABRIC_CLOCK_MODE_1,
MSM_RPM_ID_SYSTEM_FABRIC_CLOCK_MODE_2,
MSM_RPM_ID_SYSTEM_FABRIC_RESERVED_A,
MSM_RPM_ID_SYSTEM_FABRIC_ARB_0,
MSM_RPM_ID_SYSTEM_FABRIC_ARB_21 = MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 21,
MSM_RPM_ID_SYSTEM_FABRIC_RESERVED_B_0,
MSM_RPM_ID_SYSTEM_FABRIC_RESERVED_B_13 =
MSM_RPM_ID_SYSTEM_FABRIC_RESERVED_B_0 + 13,
MSM_RPM_8660_ID_SYSTEM_FABRIC_HALT_0,
MSM_RPM_8660_ID_SYSTEM_FABRIC_HALT_1,
MSM_RPM_8660_ID_SYSTEM_FABRIC_CLOCK_MODE_0,
MSM_RPM_8660_ID_SYSTEM_FABRIC_CLOCK_MODE_1,
MSM_RPM_8660_ID_SYSTEM_FABRIC_CLOCK_MODE_2,
MSM_RPM_8660_ID_SYSTEM_FABRIC_RESERVED_A,
MSM_RPM_8660_ID_SYSTEM_FABRIC_ARB_0,
MSM_RPM_8660_ID_SYSTEM_FABRIC_ARB_21 =
MSM_RPM_8660_ID_SYSTEM_FABRIC_ARB_0 + 21,
MSM_RPM_8660_ID_SYSTEM_FABRIC_RESERVED_B_0,
MSM_RPM_8660_ID_SYSTEM_FABRIC_RESERVED_B_13 =
MSM_RPM_8660_ID_SYSTEM_FABRIC_RESERVED_B_0 + 13,
MSM_RPM_ID_MM_FABRIC_HALT_0,
MSM_RPM_ID_MM_FABRIC_HALT_1,
MSM_RPM_ID_MM_FABRIC_CLOCK_MODE_0,
MSM_RPM_ID_MM_FABRIC_CLOCK_MODE_1,
MSM_RPM_ID_MM_FABRIC_CLOCK_MODE_2,
MSM_RPM_ID_MM_FABRIC_RESERVED_A,
MSM_RPM_ID_MM_FABRIC_ARB_0,
MSM_RPM_ID_MM_FABRIC_ARB_22 = MSM_RPM_ID_MM_FABRIC_ARB_0 + 22,
MSM_RPM_8660_ID_MM_FABRIC_HALT_0,
MSM_RPM_8660_ID_MM_FABRIC_HALT_1,
MSM_RPM_8660_ID_MM_FABRIC_CLOCK_MODE_0,
MSM_RPM_8660_ID_MM_FABRIC_CLOCK_MODE_1,
MSM_RPM_8660_ID_MM_FABRIC_CLOCK_MODE_2,
MSM_RPM_8660_ID_MM_FABRIC_RESERVED_A,
MSM_RPM_8660_ID_MM_FABRIC_ARB_0,
MSM_RPM_8660_ID_MM_FABRIC_ARB_22 =
MSM_RPM_8660_ID_MM_FABRIC_ARB_0 + 22,
/* pmic 8901 */
MSM_RPM_ID_SMPS0B_0,
MSM_RPM_ID_SMPS0B_1,
MSM_RPM_ID_SMPS1B_0,
MSM_RPM_ID_SMPS1B_1,
MSM_RPM_ID_SMPS2B_0,
MSM_RPM_ID_SMPS2B_1,
MSM_RPM_ID_SMPS3B_0,
MSM_RPM_ID_SMPS3B_1,
MSM_RPM_ID_SMPS4B_0,
MSM_RPM_ID_SMPS4B_1,
MSM_RPM_ID_LDO0B_0,
MSM_RPM_ID_LDO0B_1,
MSM_RPM_ID_LDO1B_0,
MSM_RPM_ID_LDO1B_1,
MSM_RPM_ID_LDO2B_0,
MSM_RPM_ID_LDO2B_1,
MSM_RPM_ID_LDO3B_0,
MSM_RPM_ID_LDO3B_1,
MSM_RPM_ID_LDO4B_0,
MSM_RPM_ID_LDO4B_1,
MSM_RPM_ID_LDO5B_0,
MSM_RPM_ID_LDO5B_1,
MSM_RPM_ID_LDO6B_0,
MSM_RPM_ID_LDO6B_1,
MSM_RPM_ID_LVS0B,
MSM_RPM_ID_LVS1B,
MSM_RPM_ID_LVS2B,
MSM_RPM_ID_LVS3B,
MSM_RPM_ID_MVS,
MSM_RPM_8660_ID_SMPS0B_0,
MSM_RPM_8660_ID_SMPS0B_1,
MSM_RPM_8660_ID_SMPS1B_0,
MSM_RPM_8660_ID_SMPS1B_1,
MSM_RPM_8660_ID_SMPS2B_0,
MSM_RPM_8660_ID_SMPS2B_1,
MSM_RPM_8660_ID_SMPS3B_0,
MSM_RPM_8660_ID_SMPS3B_1,
MSM_RPM_8660_ID_SMPS4B_0,
MSM_RPM_8660_ID_SMPS4B_1,
MSM_RPM_8660_ID_LDO0B_0,
MSM_RPM_8660_ID_LDO0B_1,
MSM_RPM_8660_ID_LDO1B_0,
MSM_RPM_8660_ID_LDO1B_1,
MSM_RPM_8660_ID_LDO2B_0,
MSM_RPM_8660_ID_LDO2B_1,
MSM_RPM_8660_ID_LDO3B_0,
MSM_RPM_8660_ID_LDO3B_1,
MSM_RPM_8660_ID_LDO4B_0,
MSM_RPM_8660_ID_LDO4B_1,
MSM_RPM_8660_ID_LDO5B_0,
MSM_RPM_8660_ID_LDO5B_1,
MSM_RPM_8660_ID_LDO6B_0,
MSM_RPM_8660_ID_LDO6B_1,
MSM_RPM_8660_ID_LVS0B,
MSM_RPM_8660_ID_LVS1B,
MSM_RPM_8660_ID_LVS2B,
MSM_RPM_8660_ID_LVS3B,
MSM_RPM_8660_ID_MVS,
/* pmic 8058 */
MSM_RPM_ID_SMPS0_0,
MSM_RPM_ID_SMPS0_1,
MSM_RPM_ID_SMPS1_0,
MSM_RPM_ID_SMPS1_1,
MSM_RPM_ID_SMPS2_0,
MSM_RPM_ID_SMPS2_1,
MSM_RPM_ID_SMPS3_0,
MSM_RPM_ID_SMPS3_1,
MSM_RPM_ID_SMPS4_0,
MSM_RPM_ID_SMPS4_1,
MSM_RPM_ID_LDO0_0,
MSM_RPM_ID_LDO0_1,
MSM_RPM_ID_LDO1_0,
MSM_RPM_ID_LDO1_1,
MSM_RPM_ID_LDO2_0,
MSM_RPM_ID_LDO2_1,
MSM_RPM_ID_LDO3_0,
MSM_RPM_ID_LDO3_1,
MSM_RPM_ID_LDO4_0,
MSM_RPM_ID_LDO4_1,
MSM_RPM_ID_LDO5_0,
MSM_RPM_ID_LDO5_1,
MSM_RPM_ID_LDO6_0,
MSM_RPM_ID_LDO6_1,
MSM_RPM_ID_LDO7_0,
MSM_RPM_ID_LDO7_1,
MSM_RPM_ID_LDO8_0,
MSM_RPM_ID_LDO8_1,
MSM_RPM_ID_LDO9_0,
MSM_RPM_ID_LDO9_1,
MSM_RPM_ID_LDO10_0,
MSM_RPM_ID_LDO10_1,
MSM_RPM_ID_LDO11_0,
MSM_RPM_ID_LDO11_1,
MSM_RPM_ID_LDO12_0,
MSM_RPM_ID_LDO12_1,
MSM_RPM_ID_LDO13_0,
MSM_RPM_ID_LDO13_1,
MSM_RPM_ID_LDO14_0,
MSM_RPM_ID_LDO14_1,
MSM_RPM_ID_LDO15_0,
MSM_RPM_ID_LDO15_1,
MSM_RPM_ID_LDO16_0,
MSM_RPM_ID_LDO16_1,
MSM_RPM_ID_LDO17_0,
MSM_RPM_ID_LDO17_1,
MSM_RPM_ID_LDO18_0,
MSM_RPM_ID_LDO18_1,
MSM_RPM_ID_LDO19_0,
MSM_RPM_ID_LDO19_1,
MSM_RPM_ID_LDO20_0,
MSM_RPM_ID_LDO20_1,
MSM_RPM_ID_LDO21_0,
MSM_RPM_ID_LDO21_1,
MSM_RPM_ID_LDO22_0,
MSM_RPM_ID_LDO22_1,
MSM_RPM_ID_LDO23_0,
MSM_RPM_ID_LDO23_1,
MSM_RPM_ID_LDO24_0,
MSM_RPM_ID_LDO24_1,
MSM_RPM_ID_LDO25_0,
MSM_RPM_ID_LDO25_1,
MSM_RPM_ID_LVS0,
MSM_RPM_ID_LVS1,
MSM_RPM_ID_NCP_0,
MSM_RPM_ID_NCP_1,
MSM_RPM_8660_ID_SMPS0_0,
MSM_RPM_8660_ID_SMPS0_1,
MSM_RPM_8660_ID_SMPS1_0,
MSM_RPM_8660_ID_SMPS1_1,
MSM_RPM_8660_ID_SMPS2_0,
MSM_RPM_8660_ID_SMPS2_1,
MSM_RPM_8660_ID_SMPS3_0,
MSM_RPM_8660_ID_SMPS3_1,
MSM_RPM_8660_ID_SMPS4_0,
MSM_RPM_8660_ID_SMPS4_1,
MSM_RPM_8660_ID_LDO0_0,
MSM_RPM_8660_ID_LDO0_1,
MSM_RPM_8660_ID_LDO1_0,
MSM_RPM_8660_ID_LDO1_1,
MSM_RPM_8660_ID_LDO2_0,
MSM_RPM_8660_ID_LDO2_1,
MSM_RPM_8660_ID_LDO3_0,
MSM_RPM_8660_ID_LDO3_1,
MSM_RPM_8660_ID_LDO4_0,
MSM_RPM_8660_ID_LDO4_1,
MSM_RPM_8660_ID_LDO5_0,
MSM_RPM_8660_ID_LDO5_1,
MSM_RPM_8660_ID_LDO6_0,
MSM_RPM_8660_ID_LDO6_1,
MSM_RPM_8660_ID_LDO7_0,
MSM_RPM_8660_ID_LDO7_1,
MSM_RPM_8660_ID_LDO8_0,
MSM_RPM_8660_ID_LDO8_1,
MSM_RPM_8660_ID_LDO9_0,
MSM_RPM_8660_ID_LDO9_1,
MSM_RPM_8660_ID_LDO10_0,
MSM_RPM_8660_ID_LDO10_1,
MSM_RPM_8660_ID_LDO11_0,
MSM_RPM_8660_ID_LDO11_1,
MSM_RPM_8660_ID_LDO12_0,
MSM_RPM_8660_ID_LDO12_1,
MSM_RPM_8660_ID_LDO13_0,
MSM_RPM_8660_ID_LDO13_1,
MSM_RPM_8660_ID_LDO14_0,
MSM_RPM_8660_ID_LDO14_1,
MSM_RPM_8660_ID_LDO15_0,
MSM_RPM_8660_ID_LDO15_1,
MSM_RPM_8660_ID_LDO16_0,
MSM_RPM_8660_ID_LDO16_1,
MSM_RPM_8660_ID_LDO17_0,
MSM_RPM_8660_ID_LDO17_1,
MSM_RPM_8660_ID_LDO18_0,
MSM_RPM_8660_ID_LDO18_1,
MSM_RPM_8660_ID_LDO19_0,
MSM_RPM_8660_ID_LDO19_1,
MSM_RPM_8660_ID_LDO20_0,
MSM_RPM_8660_ID_LDO20_1,
MSM_RPM_8660_ID_LDO21_0,
MSM_RPM_8660_ID_LDO21_1,
MSM_RPM_8660_ID_LDO22_0,
MSM_RPM_8660_ID_LDO22_1,
MSM_RPM_8660_ID_LDO23_0,
MSM_RPM_8660_ID_LDO23_1,
MSM_RPM_8660_ID_LDO24_0,
MSM_RPM_8660_ID_LDO24_1,
MSM_RPM_8660_ID_LDO25_0,
MSM_RPM_8660_ID_LDO25_1,
MSM_RPM_8660_ID_LVS0,
MSM_RPM_8660_ID_LVS1,
MSM_RPM_8660_ID_NCP_0,
MSM_RPM_8660_ID_NCP_1,
MSM_RPM_ID_CXO_BUFFERS,
MSM_RPM_8660_ID_CXO_BUFFERS,
MSM_RPM_ID_LAST = MSM_RPM_ID_CXO_BUFFERS
};
/* RPM resources RPM_ID aliases */
enum {
MSM_RPMRS_ID_RPM_CTL = MSM_RPM_ID_TRIGGER_SET_FROM,
MSM_RPMRS_ID_PXO_CLK = MSM_RPM_ID_PXO_CLK,
MSM_RPMRS_ID_APPS_L2_CACHE_CTL = MSM_RPM_ID_APPS_L2_CACHE_CTL,
MSM_RPMRS_ID_VDD_MEM_0 = MSM_RPM_ID_SMPS0_0,
MSM_RPMRS_ID_VDD_MEM_1 = MSM_RPM_ID_SMPS0_1,
MSM_RPMRS_ID_VDD_DIG_0 = MSM_RPM_ID_SMPS1_0,
MSM_RPMRS_ID_VDD_DIG_1 = MSM_RPM_ID_SMPS1_1
};
/* VDD values are in millivolts */
#define MSM_RPMRS_VDD_MASK 0xfff
enum {
MSM_RPMRS_VDD_MEM_RET_LOW = 500,
MSM_RPMRS_VDD_MEM_RET_HIGH = 750,
MSM_RPMRS_VDD_MEM_ACTIVE = 1000,
MSM_RPMRS_VDD_MEM_MAX = 1250,
MSM_RPM_8660_ID_LAST = MSM_RPM_8660_ID_CXO_BUFFERS
};
enum {
MSM_RPMRS_VDD_DIG_RET_LOW = 500,
MSM_RPMRS_VDD_DIG_RET_HIGH = 750,
MSM_RPMRS_VDD_DIG_ACTIVE = 1000,
MSM_RPMRS_VDD_DIG_MAX = 1250,
};
MSM_RPM_8660_STATUS_ID_VERSION_MAJOR,
MSM_RPM_8660_STATUS_ID_VERSION_MINOR,
MSM_RPM_8660_STATUS_ID_VERSION_BUILD,
MSM_RPM_8660_STATUS_ID_SUPPORTED_RESOURCES_0,
MSM_RPM_8660_STATUS_ID_SUPPORTED_RESOURCES_1,
MSM_RPM_8660_STATUS_ID_SUPPORTED_RESOURCES_2,
MSM_RPM_8660_STATUS_ID_RESERVED_0,
MSM_RPM_8660_STATUS_ID_RESERVED_4 =
MSM_RPM_8660_STATUS_ID_RESERVED_0 + 4,
MSM_RPM_8660_STATUS_ID_SEQUENCE,
enum {
MSM_RPM_STATUS_ID_VERSION_MAJOR,
MSM_RPM_STATUS_ID_VERSION_MINOR,
MSM_RPM_STATUS_ID_VERSION_BUILD,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2,
MSM_RPM_STATUS_ID_RESERVED_0,
MSM_RPM_STATUS_ID_RESERVED_4 = MSM_RPM_STATUS_ID_RESERVED_0 + 4,
MSM_RPM_STATUS_ID_SEQUENCE,
MSM_RPM_8660_STATUS_ID_CXO_CLK,
MSM_RPM_8660_STATUS_ID_PXO_CLK,
MSM_RPM_8660_STATUS_ID_PLL_4,
MSM_RPM_8660_STATUS_ID_APPS_FABRIC_CLK,
MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_CLK,
MSM_RPM_8660_STATUS_ID_MM_FABRIC_CLK,
MSM_RPM_8660_STATUS_ID_DAYTONA_FABRIC_CLK,
MSM_RPM_8660_STATUS_ID_SFPB_CLK,
MSM_RPM_8660_STATUS_ID_CFPB_CLK,
MSM_RPM_8660_STATUS_ID_MMFPB_CLK,
MSM_RPM_8660_STATUS_ID_SMI_CLK,
MSM_RPM_8660_STATUS_ID_EBI1_CLK,
MSM_RPM_STATUS_ID_CXO_CLK,
MSM_RPM_STATUS_ID_PXO_CLK,
MSM_RPM_STATUS_ID_PLL_4,
MSM_RPM_STATUS_ID_APPS_FABRIC_CLK,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK,
MSM_RPM_STATUS_ID_MM_FABRIC_CLK,
MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK,
MSM_RPM_STATUS_ID_SFPB_CLK,
MSM_RPM_STATUS_ID_CFPB_CLK,
MSM_RPM_STATUS_ID_MMFPB_CLK,
MSM_RPM_STATUS_ID_SMI_CLK,
MSM_RPM_STATUS_ID_EBI1_CLK,
MSM_RPM_8660_STATUS_ID_APPS_L2_CACHE_CTL,
MSM_RPM_STATUS_ID_APPS_L2_CACHE_CTL,
MSM_RPM_8660_STATUS_ID_APPS_FABRIC_HALT,
MSM_RPM_8660_STATUS_ID_APPS_FABRIC_CLOCK_MODE,
MSM_RPM_8660_STATUS_ID_APPS_FABRIC_RESERVED,
MSM_RPM_8660_STATUS_ID_APPS_FABRIC_ARB,
MSM_RPM_STATUS_ID_APPS_FABRIC_HALT,
MSM_RPM_STATUS_ID_APPS_FABRIC_CLOCK_MODE,
MSM_RPM_STATUS_ID_APPS_FABRIC_RESERVED,
MSM_RPM_STATUS_ID_APPS_FABRIC_ARB,
MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_HALT,
MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_CLOCK_MODE,
MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_RESERVED,
MSM_RPM_8660_STATUS_ID_SYSTEM_FABRIC_ARB,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_HALT,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLOCK_MODE,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_RESERVED,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB,
MSM_RPM_STATUS_ID_MM_FABRIC_HALT,
MSM_RPM_STATUS_ID_MM_FABRIC_CLOCK_MODE,
MSM_RPM_STATUS_ID_MM_FABRIC_RESERVED,
MSM_RPM_STATUS_ID_MM_FABRIC_ARB,
MSM_RPM_8660_STATUS_ID_MM_FABRIC_HALT,
MSM_RPM_8660_STATUS_ID_MM_FABRIC_CLOCK_MODE,
MSM_RPM_8660_STATUS_ID_MM_FABRIC_RESERVED,
MSM_RPM_8660_STATUS_ID_MM_FABRIC_ARB,
/* pmic 8901 */
MSM_RPM_STATUS_ID_SMPS0B_0,
MSM_RPM_STATUS_ID_SMPS0B_1,
MSM_RPM_STATUS_ID_SMPS1B_0,
MSM_RPM_STATUS_ID_SMPS1B_1,
MSM_RPM_STATUS_ID_SMPS2B_0,
MSM_RPM_STATUS_ID_SMPS2B_1,
MSM_RPM_STATUS_ID_SMPS3B_0,
MSM_RPM_STATUS_ID_SMPS3B_1,
MSM_RPM_STATUS_ID_SMPS4B_0,
MSM_RPM_STATUS_ID_SMPS4B_1,
MSM_RPM_STATUS_ID_LDO0B_0,
MSM_RPM_STATUS_ID_LDO0B_1,
MSM_RPM_STATUS_ID_LDO1B_0,
MSM_RPM_STATUS_ID_LDO1B_1,
MSM_RPM_STATUS_ID_LDO2B_0,
MSM_RPM_STATUS_ID_LDO2B_1,
MSM_RPM_STATUS_ID_LDO3B_0,
MSM_RPM_STATUS_ID_LDO3B_1,
MSM_RPM_STATUS_ID_LDO4B_0,
MSM_RPM_STATUS_ID_LDO4B_1,
MSM_RPM_STATUS_ID_LDO5B_0,
MSM_RPM_STATUS_ID_LDO5B_1,
MSM_RPM_STATUS_ID_LDO6B_0,
MSM_RPM_STATUS_ID_LDO6B_1,
MSM_RPM_STATUS_ID_LVS0B,
MSM_RPM_STATUS_ID_LVS1B,
MSM_RPM_STATUS_ID_LVS2B,
MSM_RPM_STATUS_ID_LVS3B,
MSM_RPM_STATUS_ID_MVS,
MSM_RPM_8660_STATUS_ID_SMPS0B_0,
MSM_RPM_8660_STATUS_ID_SMPS0B_1,
MSM_RPM_8660_STATUS_ID_SMPS1B_0,
MSM_RPM_8660_STATUS_ID_SMPS1B_1,
MSM_RPM_8660_STATUS_ID_SMPS2B_0,
MSM_RPM_8660_STATUS_ID_SMPS2B_1,
MSM_RPM_8660_STATUS_ID_SMPS3B_0,
MSM_RPM_8660_STATUS_ID_SMPS3B_1,
MSM_RPM_8660_STATUS_ID_SMPS4B_0,
MSM_RPM_8660_STATUS_ID_SMPS4B_1,
MSM_RPM_8660_STATUS_ID_LDO0B_0,
MSM_RPM_8660_STATUS_ID_LDO0B_1,
MSM_RPM_8660_STATUS_ID_LDO1B_0,
MSM_RPM_8660_STATUS_ID_LDO1B_1,
MSM_RPM_8660_STATUS_ID_LDO2B_0,
MSM_RPM_8660_STATUS_ID_LDO2B_1,
MSM_RPM_8660_STATUS_ID_LDO3B_0,
MSM_RPM_8660_STATUS_ID_LDO3B_1,
MSM_RPM_8660_STATUS_ID_LDO4B_0,
MSM_RPM_8660_STATUS_ID_LDO4B_1,
MSM_RPM_8660_STATUS_ID_LDO5B_0,
MSM_RPM_8660_STATUS_ID_LDO5B_1,
MSM_RPM_8660_STATUS_ID_LDO6B_0,
MSM_RPM_8660_STATUS_ID_LDO6B_1,
MSM_RPM_8660_STATUS_ID_LVS0B,
MSM_RPM_8660_STATUS_ID_LVS1B,
MSM_RPM_8660_STATUS_ID_LVS2B,
MSM_RPM_8660_STATUS_ID_LVS3B,
MSM_RPM_8660_STATUS_ID_MVS,
/* pmic 8058 */
MSM_RPM_STATUS_ID_SMPS0_0,
MSM_RPM_STATUS_ID_SMPS0_1,
MSM_RPM_STATUS_ID_SMPS1_0,
MSM_RPM_STATUS_ID_SMPS1_1,
MSM_RPM_STATUS_ID_SMPS2_0,
MSM_RPM_STATUS_ID_SMPS2_1,
MSM_RPM_STATUS_ID_SMPS3_0,
MSM_RPM_STATUS_ID_SMPS3_1,
MSM_RPM_STATUS_ID_SMPS4_0,
MSM_RPM_STATUS_ID_SMPS4_1,
MSM_RPM_STATUS_ID_LDO0_0,
MSM_RPM_STATUS_ID_LDO0_1,
MSM_RPM_STATUS_ID_LDO1_0,
MSM_RPM_STATUS_ID_LDO1_1,
MSM_RPM_STATUS_ID_LDO2_0,
MSM_RPM_STATUS_ID_LDO2_1,
MSM_RPM_STATUS_ID_LDO3_0,
MSM_RPM_STATUS_ID_LDO3_1,
MSM_RPM_STATUS_ID_LDO4_0,
MSM_RPM_STATUS_ID_LDO4_1,
MSM_RPM_STATUS_ID_LDO5_0,
MSM_RPM_STATUS_ID_LDO5_1,
MSM_RPM_STATUS_ID_LDO6_0,
MSM_RPM_STATUS_ID_LDO6_1,
MSM_RPM_STATUS_ID_LDO7_0,
MSM_RPM_STATUS_ID_LDO7_1,
MSM_RPM_STATUS_ID_LDO8_0,
MSM_RPM_STATUS_ID_LDO8_1,
MSM_RPM_STATUS_ID_LDO9_0,
MSM_RPM_STATUS_ID_LDO9_1,
MSM_RPM_STATUS_ID_LDO10_0,
MSM_RPM_STATUS_ID_LDO10_1,
MSM_RPM_STATUS_ID_LDO11_0,
MSM_RPM_STATUS_ID_LDO11_1,
MSM_RPM_STATUS_ID_LDO12_0,
MSM_RPM_STATUS_ID_LDO12_1,
MSM_RPM_STATUS_ID_LDO13_0,
MSM_RPM_STATUS_ID_LDO13_1,
MSM_RPM_STATUS_ID_LDO14_0,
MSM_RPM_STATUS_ID_LDO14_1,
MSM_RPM_STATUS_ID_LDO15_0,
MSM_RPM_STATUS_ID_LDO15_1,
MSM_RPM_STATUS_ID_LDO16_0,
MSM_RPM_STATUS_ID_LDO16_1,
MSM_RPM_STATUS_ID_LDO17_0,
MSM_RPM_STATUS_ID_LDO17_1,
MSM_RPM_STATUS_ID_LDO18_0,
MSM_RPM_STATUS_ID_LDO18_1,
MSM_RPM_STATUS_ID_LDO19_0,
MSM_RPM_STATUS_ID_LDO19_1,
MSM_RPM_STATUS_ID_LDO20_0,
MSM_RPM_STATUS_ID_LDO20_1,
MSM_RPM_STATUS_ID_LDO21_0,
MSM_RPM_STATUS_ID_LDO21_1,
MSM_RPM_STATUS_ID_LDO22_0,
MSM_RPM_STATUS_ID_LDO22_1,
MSM_RPM_STATUS_ID_LDO23_0,
MSM_RPM_STATUS_ID_LDO23_1,
MSM_RPM_STATUS_ID_LDO24_0,
MSM_RPM_STATUS_ID_LDO24_1,
MSM_RPM_STATUS_ID_LDO25_0,
MSM_RPM_STATUS_ID_LDO25_1,
MSM_RPM_STATUS_ID_LVS0,
MSM_RPM_STATUS_ID_LVS1,
MSM_RPM_STATUS_ID_NCP_0,
MSM_RPM_STATUS_ID_NCP_1,
MSM_RPM_8660_STATUS_ID_SMPS0_0,
MSM_RPM_8660_STATUS_ID_SMPS0_1,
MSM_RPM_8660_STATUS_ID_SMPS1_0,
MSM_RPM_8660_STATUS_ID_SMPS1_1,
MSM_RPM_8660_STATUS_ID_SMPS2_0,
MSM_RPM_8660_STATUS_ID_SMPS2_1,
MSM_RPM_8660_STATUS_ID_SMPS3_0,
MSM_RPM_8660_STATUS_ID_SMPS3_1,
MSM_RPM_8660_STATUS_ID_SMPS4_0,
MSM_RPM_8660_STATUS_ID_SMPS4_1,
MSM_RPM_8660_STATUS_ID_LDO0_0,
MSM_RPM_8660_STATUS_ID_LDO0_1,
MSM_RPM_8660_STATUS_ID_LDO1_0,
MSM_RPM_8660_STATUS_ID_LDO1_1,
MSM_RPM_8660_STATUS_ID_LDO2_0,
MSM_RPM_8660_STATUS_ID_LDO2_1,
MSM_RPM_8660_STATUS_ID_LDO3_0,
MSM_RPM_8660_STATUS_ID_LDO3_1,
MSM_RPM_8660_STATUS_ID_LDO4_0,
MSM_RPM_8660_STATUS_ID_LDO4_1,
MSM_RPM_8660_STATUS_ID_LDO5_0,
MSM_RPM_8660_STATUS_ID_LDO5_1,
MSM_RPM_8660_STATUS_ID_LDO6_0,
MSM_RPM_8660_STATUS_ID_LDO6_1,
MSM_RPM_8660_STATUS_ID_LDO7_0,
MSM_RPM_8660_STATUS_ID_LDO7_1,
MSM_RPM_8660_STATUS_ID_LDO8_0,
MSM_RPM_8660_STATUS_ID_LDO8_1,
MSM_RPM_8660_STATUS_ID_LDO9_0,
MSM_RPM_8660_STATUS_ID_LDO9_1,
MSM_RPM_8660_STATUS_ID_LDO10_0,
MSM_RPM_8660_STATUS_ID_LDO10_1,
MSM_RPM_8660_STATUS_ID_LDO11_0,
MSM_RPM_8660_STATUS_ID_LDO11_1,
MSM_RPM_8660_STATUS_ID_LDO12_0,
MSM_RPM_8660_STATUS_ID_LDO12_1,
MSM_RPM_8660_STATUS_ID_LDO13_0,
MSM_RPM_8660_STATUS_ID_LDO13_1,
MSM_RPM_8660_STATUS_ID_LDO14_0,
MSM_RPM_8660_STATUS_ID_LDO14_1,
MSM_RPM_8660_STATUS_ID_LDO15_0,
MSM_RPM_8660_STATUS_ID_LDO15_1,
MSM_RPM_8660_STATUS_ID_LDO16_0,
MSM_RPM_8660_STATUS_ID_LDO16_1,
MSM_RPM_8660_STATUS_ID_LDO17_0,
MSM_RPM_8660_STATUS_ID_LDO17_1,
MSM_RPM_8660_STATUS_ID_LDO18_0,
MSM_RPM_8660_STATUS_ID_LDO18_1,
MSM_RPM_8660_STATUS_ID_LDO19_0,
MSM_RPM_8660_STATUS_ID_LDO19_1,
MSM_RPM_8660_STATUS_ID_LDO20_0,
MSM_RPM_8660_STATUS_ID_LDO20_1,
MSM_RPM_8660_STATUS_ID_LDO21_0,
MSM_RPM_8660_STATUS_ID_LDO21_1,
MSM_RPM_8660_STATUS_ID_LDO22_0,
MSM_RPM_8660_STATUS_ID_LDO22_1,
MSM_RPM_8660_STATUS_ID_LDO23_0,
MSM_RPM_8660_STATUS_ID_LDO23_1,
MSM_RPM_8660_STATUS_ID_LDO24_0,
MSM_RPM_8660_STATUS_ID_LDO24_1,
MSM_RPM_8660_STATUS_ID_LDO25_0,
MSM_RPM_8660_STATUS_ID_LDO25_1,
MSM_RPM_8660_STATUS_ID_LVS0,
MSM_RPM_8660_STATUS_ID_LVS1,
MSM_RPM_8660_STATUS_ID_NCP_0,
MSM_RPM_8660_STATUS_ID_NCP_1,
MSM_RPM_STATUS_ID_CXO_BUFFERS,
MSM_RPM_8660_STATUS_ID_CXO_BUFFERS,
MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_CXO_BUFFERS
MSM_RPM_8660_STATUS_ID_LAST =
MSM_RPM_8660_STATUS_ID_CXO_BUFFERS
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_8660_H */

359
arch/arm/mach-msm/include/mach/rpm-8930.h Normal file
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/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __ARCH_ARM_MACH_MSM_RPM_8930_H
#define __ARCH_ARM_MACH_MSM_RPM_8930_H
/* RPM control message RAM enums */
enum {
MSM_RPM_8930_CTRL_VERSION_MAJOR,
MSM_RPM_8930_CTRL_VERSION_MINOR,
MSM_RPM_8930_CTRL_VERSION_BUILD,
MSM_RPM_8930_CTRL_REQ_CTX_0,
MSM_RPM_8930_CTRL_REQ_CTX_7 = MSM_RPM_8930_CTRL_REQ_CTX_0 + 7,
MSM_RPM_8930_CTRL_REQ_SEL_0,
MSM_RPM_8930_CTRL_REQ_SEL_3 = MSM_RPM_8930_CTRL_REQ_SEL_0 + 3,
MSM_RPM_8930_CTRL_ACK_CTX_0,
MSM_RPM_8930_CTRL_ACK_CTX_7 = MSM_RPM_8930_CTRL_ACK_CTX_0 + 7,
MSM_RPM_8930_CTRL_ACK_SEL_0,
MSM_RPM_8930_CTRL_ACK_SEL_7 = MSM_RPM_8930_CTRL_ACK_SEL_0 + 7,
};
/* RPM resource select enums defined for RPM core
NOT IN SEQUENTIAL ORDER */
enum {
MSM_RPM_8930_SEL_NOTIFICATION = 0,
MSM_RPM_8930_SEL_INVALIDATE = 1,
MSM_RPM_8930_SEL_TRIGGER_TIMED_0 = 2,
MSM_RPM_8930_SEL_RPM_CTL = 3,
MSM_RPM_8930_SEL_CXO_CLK = 5,
MSM_RPM_8930_SEL_PXO_CLK = 6,
MSM_RPM_8930_SEL_QDSS_CLK = 7,
MSM_RPM_8930_SEL_APPS_FABRIC_CLK = 8,
MSM_RPM_8930_SEL_SYSTEM_FABRIC_CLK = 9,
MSM_RPM_8930_SEL_MM_FABRIC_CLK = 10,
MSM_RPM_8930_SEL_DAYTONA_FABRIC_CLK = 11,
MSM_RPM_8930_SEL_SFPB_CLK = 12,
MSM_RPM_8930_SEL_CFPB_CLK = 13,
MSM_RPM_8930_SEL_MMFPB_CLK = 14,
MSM_RPM_8930_SEL_EBI1_CLK = 16,
MSM_RPM_8930_SEL_APPS_FABRIC_CFG_HALT = 18,
MSM_RPM_8930_SEL_APPS_FABRIC_CFG_CLKMOD = 19,
MSM_RPM_8930_SEL_APPS_FABRIC_CFG_IOCTL = 20,
MSM_RPM_8930_SEL_APPS_FABRIC_ARB = 21,
MSM_RPM_8930_SEL_SYS_FABRIC_CFG_HALT = 22,
MSM_RPM_8930_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
MSM_RPM_8930_SEL_SYS_FABRIC_CFG_IOCTL = 24,
MSM_RPM_8930_SEL_SYSTEM_FABRIC_ARB = 25,
MSM_RPM_8930_SEL_MMSS_FABRIC_CFG_HALT = 26,
MSM_RPM_8930_SEL_MMSS_FABRIC_CFG_CLKMOD = 27,
MSM_RPM_8930_SEL_MMSS_FABRIC_CFG_IOCTL = 28,
MSM_RPM_8930_SEL_MM_FABRIC_ARB = 29,
MSM_RPM_8930_SEL_PM8038_S1 = 30,
MSM_RPM_8930_SEL_PM8038_S2 = 31,
MSM_RPM_8930_SEL_PM8038_S3 = 32,
MSM_RPM_8930_SEL_PM8038_S4 = 33,
MSM_RPM_8930_SEL_PM8038_S5 = 34,
MSM_RPM_8930_SEL_PM8038_S6 = 35,
MSM_RPM_8930_SEL_PM8038_L1 = 36,
MSM_RPM_8930_SEL_PM8038_L2 = 37,
MSM_RPM_8930_SEL_PM8038_L3 = 38,
MSM_RPM_8930_SEL_PM8038_L4 = 39,
MSM_RPM_8930_SEL_PM8038_L5 = 40,
MSM_RPM_8930_SEL_PM8038_L6 = 41,
MSM_RPM_8930_SEL_PM8038_L7 = 42,
MSM_RPM_8930_SEL_PM8038_L8 = 43,
MSM_RPM_8930_SEL_PM8038_L9 = 44,
MSM_RPM_8930_SEL_PM8038_L10 = 45,
MSM_RPM_8930_SEL_PM8038_L11 = 46,
MSM_RPM_8930_SEL_PM8038_L12 = 47,
MSM_RPM_8930_SEL_PM8038_L13 = 48,
MSM_RPM_8930_SEL_PM8038_L14 = 49,
MSM_RPM_8930_SEL_PM8038_L15 = 50,
MSM_RPM_8930_SEL_PM8038_L16 = 51,
MSM_RPM_8930_SEL_PM8038_L17 = 52,
MSM_RPM_8930_SEL_PM8038_L18 = 53,
MSM_RPM_8930_SEL_PM8038_L19 = 54,
MSM_RPM_8930_SEL_PM8038_L20 = 55,
MSM_RPM_8930_SEL_PM8038_L21 = 56,
MSM_RPM_8930_SEL_PM8038_L22 = 57,
MSM_RPM_8930_SEL_PM8038_L23 = 58,
MSM_RPM_8930_SEL_PM8038_L24 = 59,
MSM_RPM_8930_SEL_PM8038_L25 = 60,
MSM_RPM_8930_SEL_PM8038_L26 = 61,
MSM_RPM_8930_SEL_PM8038_L27 = 62,
MSM_RPM_8930_SEL_PM8038_CLK1 = 63,
MSM_RPM_8930_SEL_PM8038_CLK2 = 64,
MSM_RPM_8930_SEL_PM8038_LVS1 = 65,
MSM_RPM_8930_SEL_PM8038_LVS2 = 66,
MSM_RPM_8930_SEL_NCP = 80,
MSM_RPM_8930_SEL_CXO_BUFFERS = 81,
MSM_RPM_8930_SEL_USB_OTG_SWITCH = 82,
MSM_RPM_8930_SEL_HDMI_SWITCH = 83,
MSM_RPM_8930_SEL_LAST = MSM_RPM_8930_SEL_HDMI_SWITCH,
};
/* RPM resource (4 byte) word ID enum */
enum {
MSM_RPM_8930_ID_NOTIFICATION_CONFIGURED_0 = 0,
MSM_RPM_8930_ID_NOTIFICATION_CONFIGURED_3 =
MSM_RPM_8930_ID_NOTIFICATION_CONFIGURED_0 + 3,
MSM_RPM_8930_ID_NOTIFICATION_REGISTERED_0 = 4,
MSM_RPM_8930_ID_NOTIFICATION_REGISTERED_3 =
MSM_RPM_8930_ID_NOTIFICATION_REGISTERED_0 + 3,
MSM_RPM_8930_ID_INVALIDATE_0 = 8,
MSM_RPM_8930_ID_INVALIDATE_7 =
MSM_RPM_8930_ID_INVALIDATE_0 + 7,
MSM_RPM_8930_ID_TRIGGER_TIMED_0 = 16,
MSM_RPM_8930_ID_TRIGGER_TIMED_1 = 17,
MSM_RPM_8930_ID_RPM_CTL = 18,
MSM_RPM_8930_ID_RESERVED_0 = 19,
MSM_RPM_8930_ID_RESERVED_5 =
MSM_RPM_8930_ID_RESERVED_0 + 5,
MSM_RPM_8930_ID_CXO_CLK = 25,
MSM_RPM_8930_ID_PXO_CLK = 26,
MSM_RPM_8930_ID_APPS_FABRIC_CLK = 27,
MSM_RPM_8930_ID_SYSTEM_FABRIC_CLK = 28,
MSM_RPM_8930_ID_MM_FABRIC_CLK = 29,
MSM_RPM_8930_ID_DAYTONA_FABRIC_CLK = 30,
MSM_RPM_8930_ID_SFPB_CLK = 31,
MSM_RPM_8930_ID_CFPB_CLK = 32,
MSM_RPM_8930_ID_MMFPB_CLK = 33,
MSM_RPM_8930_ID_EBI1_CLK = 34,
MSM_RPM_8930_ID_APPS_FABRIC_CFG_HALT_0 = 35,
MSM_RPM_8930_ID_APPS_FABRIC_CFG_HALT_1 = 36,
MSM_RPM_8930_ID_APPS_FABRIC_CFG_CLKMOD_0 = 37,
MSM_RPM_8930_ID_APPS_FABRIC_CFG_CLKMOD_1 = 38,
MSM_RPM_8930_ID_APPS_FABRIC_CFG_CLKMOD_2 = 39,
MSM_RPM_8930_ID_APPS_FABRIC_CFG_IOCTL = 40,
MSM_RPM_8930_ID_APPS_FABRIC_ARB_0 = 41,
MSM_RPM_8930_ID_APPS_FABRIC_ARB_5 =
MSM_RPM_8930_ID_APPS_FABRIC_ARB_0 + 5,
MSM_RPM_8930_ID_SYS_FABRIC_CFG_HALT_0 = 47,
MSM_RPM_8930_ID_SYS_FABRIC_CFG_HALT_1 = 48,
MSM_RPM_8930_ID_SYS_FABRIC_CFG_CLKMOD_0 = 49,
MSM_RPM_8930_ID_SYS_FABRIC_CFG_CLKMOD_1 = 50,
MSM_RPM_8930_ID_SYS_FABRIC_CFG_CLKMOD_2 = 51,
MSM_RPM_8930_ID_SYS_FABRIC_CFG_IOCTL = 52,
MSM_RPM_8930_ID_SYSTEM_FABRIC_ARB_0 = 53,
MSM_RPM_8930_ID_SYSTEM_FABRIC_ARB_19 =
MSM_RPM_8930_ID_SYSTEM_FABRIC_ARB_0 + 19,
MSM_RPM_8930_ID_MMSS_FABRIC_CFG_HALT_0 = 73,
MSM_RPM_8930_ID_MMSS_FABRIC_CFG_HALT_1 = 74,
MSM_RPM_8930_ID_MMSS_FABRIC_CFG_CLKMOD_0 = 75,
MSM_RPM_8930_ID_MMSS_FABRIC_CFG_CLKMOD_1 = 76,
MSM_RPM_8930_ID_MMSS_FABRIC_CFG_CLKMOD_2 = 77,
MSM_RPM_8930_ID_MMSS_FABRIC_CFG_IOCTL = 78,
MSM_RPM_8930_ID_MM_FABRIC_ARB_0 = 79,
MSM_RPM_8930_ID_MM_FABRIC_ARB_10 =
MSM_RPM_8930_ID_MM_FABRIC_ARB_0 + 10,
MSM_RPM_8930_ID_PM8038_S1_0 = 90,
MSM_RPM_8930_ID_PM8038_S1_1 = 91,
MSM_RPM_8930_ID_PM8038_S2_0 = 92,
MSM_RPM_8930_ID_PM8038_S2_1 = 93,
MSM_RPM_8930_ID_PM8038_S3_0 = 94,
MSM_RPM_8930_ID_PM8038_S3_1 = 95,
MSM_RPM_8930_ID_PM8038_S4_0 = 96,
MSM_RPM_8930_ID_PM8038_S4_1 = 97,
MSM_RPM_8930_ID_PM8038_S5_0 = 98,
MSM_RPM_8930_ID_PM8038_S5_1 = 99,
MSM_RPM_8930_ID_PM8038_S6_0 = 100,
MSM_RPM_8930_ID_PM8038_S6_1 = 101,
MSM_RPM_8930_ID_PM8038_L1_0 = 102,
MSM_RPM_8930_ID_PM8038_L1_1 = 103,
MSM_RPM_8930_ID_PM8038_L2_0 = 104,
MSM_RPM_8930_ID_PM8038_L2_1 = 105,
MSM_RPM_8930_ID_PM8038_L3_0 = 106,
MSM_RPM_8930_ID_PM8038_L3_1 = 107,
MSM_RPM_8930_ID_PM8038_L4_0 = 108,
MSM_RPM_8930_ID_PM8038_L4_1 = 109,
MSM_RPM_8930_ID_PM8038_L5_0 = 110,
MSM_RPM_8930_ID_PM8038_L5_1 = 111,
MSM_RPM_8930_ID_PM8038_L6_0 = 112,
MSM_RPM_8930_ID_PM8038_L6_1 = 113,
MSM_RPM_8930_ID_PM8038_L7_0 = 114,
MSM_RPM_8930_ID_PM8038_L7_1 = 115,
MSM_RPM_8930_ID_PM8038_L8_0 = 116,
MSM_RPM_8930_ID_PM8038_L8_1 = 117,
MSM_RPM_8930_ID_PM8038_L9_0 = 118,
MSM_RPM_8930_ID_PM8038_L9_1 = 119,
MSM_RPM_8930_ID_PM8038_L10_0 = 120,
MSM_RPM_8930_ID_PM8038_L10_1 = 121,
MSM_RPM_8930_ID_PM8038_L11_0 = 122,
MSM_RPM_8930_ID_PM8038_L11_1 = 123,
MSM_RPM_8930_ID_PM8038_L12_0 = 124,
MSM_RPM_8930_ID_PM8038_L12_1 = 125,
MSM_RPM_8930_ID_PM8038_L13_0 = 126,
MSM_RPM_8930_ID_PM8038_L13_1 = 127,
MSM_RPM_8930_ID_PM8038_L14_0 = 128,
MSM_RPM_8930_ID_PM8038_L14_1 = 129,
MSM_RPM_8930_ID_PM8038_L15_0 = 130,
MSM_RPM_8930_ID_PM8038_L15_1 = 131,
MSM_RPM_8930_ID_PM8038_L16_0 = 132,
MSM_RPM_8930_ID_PM8038_L16_1 = 133,
MSM_RPM_8930_ID_PM8038_L17_0 = 134,
MSM_RPM_8930_ID_PM8038_L17_1 = 135,
MSM_RPM_8930_ID_PM8038_L18_0 = 136,
MSM_RPM_8930_ID_PM8038_L18_1 = 137,
MSM_RPM_8930_ID_PM8038_L19_0 = 138,
MSM_RPM_8930_ID_PM8038_L19_1 = 139,
MSM_RPM_8930_ID_PM8038_L20_0 = 140,
MSM_RPM_8930_ID_PM8038_L20_1 = 141,
MSM_RPM_8930_ID_PM8038_L21_0 = 142,
MSM_RPM_8930_ID_PM8038_L21_1 = 143,
MSM_RPM_8930_ID_PM8038_L22_0 = 144,
MSM_RPM_8930_ID_PM8038_L22_1 = 145,
MSM_RPM_8930_ID_PM8038_L23_0 = 146,
MSM_RPM_8930_ID_PM8038_L23_1 = 147,
MSM_RPM_8930_ID_PM8038_L24_0 = 148,
MSM_RPM_8930_ID_PM8038_L24_1 = 149,
MSM_RPM_8930_ID_PM8038_L25_0 = 150,
MSM_RPM_8930_ID_PM8038_L25_1 = 151,
MSM_RPM_8930_ID_PM8038_L26_0 = 152,
MSM_RPM_8930_ID_PM8038_L26_1 = 153,
MSM_RPM_8930_ID_PM8038_L27_0 = 154,
MSM_RPM_8930_ID_PM8038_L27_1 = 155,
MSM_RPM_8930_ID_PM8038_CLK1_0 = 156,
MSM_RPM_8930_ID_PM8038_CLK1_1 = 157,
MSM_RPM_8930_ID_PM8038_CLK2_0 = 158,
MSM_RPM_8930_ID_PM8038_CLK2_1 = 159,
MSM_RPM_8930_ID_PM8038_LVS1 = 160,
MSM_RPM_8930_ID_PM8038_LVS2 = 161,
MSM_RPM_8930_ID_NCP_0 = 162,
MSM_RPM_8930_ID_NCP_1 = 163,
MSM_RPM_8930_ID_CXO_BUFFERS = 164,
MSM_RPM_8930_ID_USB_OTG_SWITCH = 165,
MSM_RPM_8930_ID_HDMI_SWITCH = 166,
MSM_RPM_8930_ID_QDSS_CLK = 167,
MSM_RPM_8930_ID_LAST = MSM_RPM_8930_ID_QDSS_CLK,
};
/* RPM status ID enum */
enum {
MSM_RPM_8930_STATUS_ID_VERSION_MAJOR = 0,
MSM_RPM_8930_STATUS_ID_VERSION_MINOR = 1,
MSM_RPM_8930_STATUS_ID_VERSION_BUILD = 2,
MSM_RPM_8930_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
MSM_RPM_8930_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
MSM_RPM_8930_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
MSM_RPM_8930_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
MSM_RPM_8930_STATUS_ID_SEQUENCE = 7,
MSM_RPM_8930_STATUS_ID_RPM_CTL = 8,
MSM_RPM_8930_STATUS_ID_CXO_CLK = 9,
MSM_RPM_8930_STATUS_ID_PXO_CLK = 10,
MSM_RPM_8930_STATUS_ID_APPS_FABRIC_CLK = 11,
MSM_RPM_8930_STATUS_ID_SYSTEM_FABRIC_CLK = 12,
MSM_RPM_8930_STATUS_ID_MM_FABRIC_CLK = 13,
MSM_RPM_8930_STATUS_ID_DAYTONA_FABRIC_CLK = 14,
MSM_RPM_8930_STATUS_ID_SFPB_CLK = 15,
MSM_RPM_8930_STATUS_ID_CFPB_CLK = 16,
MSM_RPM_8930_STATUS_ID_MMFPB_CLK = 17,
MSM_RPM_8930_STATUS_ID_EBI1_CLK = 18,
MSM_RPM_8930_STATUS_ID_APPS_FABRIC_CFG_HALT = 19,
MSM_RPM_8930_STATUS_ID_APPS_FABRIC_CFG_CLKMOD = 20,
MSM_RPM_8930_STATUS_ID_APPS_FABRIC_CFG_IOCTL = 21,
MSM_RPM_8930_STATUS_ID_APPS_FABRIC_ARB = 22,
MSM_RPM_8930_STATUS_ID_SYS_FABRIC_CFG_HALT = 23,
MSM_RPM_8930_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 24,
MSM_RPM_8930_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 25,
MSM_RPM_8930_STATUS_ID_SYSTEM_FABRIC_ARB = 26,
MSM_RPM_8930_STATUS_ID_MMSS_FABRIC_CFG_HALT = 27,
MSM_RPM_8930_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD = 28,
MSM_RPM_8930_STATUS_ID_MMSS_FABRIC_CFG_IOCTL = 29,
MSM_RPM_8930_STATUS_ID_MM_FABRIC_ARB = 30,
MSM_RPM_8930_STATUS_ID_PM8038_S1_0 = 31,
MSM_RPM_8930_STATUS_ID_PM8038_S1_1 = 32,
MSM_RPM_8930_STATUS_ID_PM8038_S2_0 = 33,
MSM_RPM_8930_STATUS_ID_PM8038_S2_1 = 34,
MSM_RPM_8930_STATUS_ID_PM8038_S3_0 = 35,
MSM_RPM_8930_STATUS_ID_PM8038_S3_1 = 36,
MSM_RPM_8930_STATUS_ID_PM8038_S4_0 = 37,
MSM_RPM_8930_STATUS_ID_PM8038_S4_1 = 38,
MSM_RPM_8930_STATUS_ID_PM8038_S5_0 = 39,
MSM_RPM_8930_STATUS_ID_PM8038_S5_1 = 40,
MSM_RPM_8930_STATUS_ID_PM8038_S6_0 = 41,
MSM_RPM_8930_STATUS_ID_PM8038_S6_1 = 42,
MSM_RPM_8930_STATUS_ID_PM8038_L1_0 = 43,
MSM_RPM_8930_STATUS_ID_PM8038_L1_1 = 44,
MSM_RPM_8930_STATUS_ID_PM8038_L2_0 = 45,
MSM_RPM_8930_STATUS_ID_PM8038_L2_1 = 46,
MSM_RPM_8930_STATUS_ID_PM8038_L3_0 = 47,
MSM_RPM_8930_STATUS_ID_PM8038_L3_1 = 48,
MSM_RPM_8930_STATUS_ID_PM8038_L4_0 = 49,
MSM_RPM_8930_STATUS_ID_PM8038_L4_1 = 50,
MSM_RPM_8930_STATUS_ID_PM8038_L5_0 = 51,
MSM_RPM_8930_STATUS_ID_PM8038_L5_1 = 52,
MSM_RPM_8930_STATUS_ID_PM8038_L6_0 = 53,
MSM_RPM_8930_STATUS_ID_PM8038_L6_1 = 54,
MSM_RPM_8930_STATUS_ID_PM8038_L7_0 = 55,
MSM_RPM_8930_STATUS_ID_PM8038_L7_1 = 56,
MSM_RPM_8930_STATUS_ID_PM8038_L8_0 = 57,
MSM_RPM_8930_STATUS_ID_PM8038_L8_1 = 58,
MSM_RPM_8930_STATUS_ID_PM8038_L9_0 = 59,
MSM_RPM_8930_STATUS_ID_PM8038_L9_1 = 60,
MSM_RPM_8930_STATUS_ID_PM8038_L10_0 = 61,
MSM_RPM_8930_STATUS_ID_PM8038_L10_1 = 62,
MSM_RPM_8930_STATUS_ID_PM8038_L11_0 = 63,
MSM_RPM_8930_STATUS_ID_PM8038_L11_1 = 64,
MSM_RPM_8930_STATUS_ID_PM8038_L12_0 = 65,
MSM_RPM_8930_STATUS_ID_PM8038_L12_1 = 66,
MSM_RPM_8930_STATUS_ID_PM8038_L13_0 = 67,
MSM_RPM_8930_STATUS_ID_PM8038_L13_1 = 68,
MSM_RPM_8930_STATUS_ID_PM8038_L14_0 = 69,
MSM_RPM_8930_STATUS_ID_PM8038_L14_1 = 70,
MSM_RPM_8930_STATUS_ID_PM8038_L15_0 = 71,
MSM_RPM_8930_STATUS_ID_PM8038_L15_1 = 72,
MSM_RPM_8930_STATUS_ID_PM8038_L16_0 = 73,
MSM_RPM_8930_STATUS_ID_PM8038_L16_1 = 74,
MSM_RPM_8930_STATUS_ID_PM8038_L17_0 = 75,
MSM_RPM_8930_STATUS_ID_PM8038_L17_1 = 76,
MSM_RPM_8930_STATUS_ID_PM8038_L18_0 = 77,
MSM_RPM_8930_STATUS_ID_PM8038_L18_1 = 78,
MSM_RPM_8930_STATUS_ID_PM8038_L19_0 = 79,
MSM_RPM_8930_STATUS_ID_PM8038_L19_1 = 80,
MSM_RPM_8930_STATUS_ID_PM8038_L20_0 = 81,
MSM_RPM_8930_STATUS_ID_PM8038_L20_1 = 82,
MSM_RPM_8930_STATUS_ID_PM8038_L21_0 = 83,
MSM_RPM_8930_STATUS_ID_PM8038_L21_1 = 84,
MSM_RPM_8930_STATUS_ID_PM8038_L22_0 = 85,
MSM_RPM_8930_STATUS_ID_PM8038_L22_1 = 86,
MSM_RPM_8930_STATUS_ID_PM8038_L23_0 = 87,
MSM_RPM_8930_STATUS_ID_PM8038_L23_1 = 88,
MSM_RPM_8930_STATUS_ID_PM8038_L24_0 = 89,
MSM_RPM_8930_STATUS_ID_PM8038_L24_1 = 90,
MSM_RPM_8930_STATUS_ID_PM8038_L25_0 = 91,
MSM_RPM_8930_STATUS_ID_PM8038_L25_1 = 92,
MSM_RPM_8930_STATUS_ID_PM8038_L26_0 = 93,
MSM_RPM_8930_STATUS_ID_PM8038_L26_1 = 94,
MSM_RPM_8930_STATUS_ID_PM8038_L27_0 = 95,
MSM_RPM_8930_STATUS_ID_PM8038_L27_1 = 96,
MSM_RPM_8930_STATUS_ID_PM8038_CLK1_0 = 97,
MSM_RPM_8930_STATUS_ID_PM8038_CLK1_1 = 98,
MSM_RPM_8930_STATUS_ID_PM8038_CLK2_0 = 99,
MSM_RPM_8930_STATUS_ID_PM8038_CLK2_1 = 100,
MSM_RPM_8930_STATUS_ID_PM8038_LVS1 = 101,
MSM_RPM_8930_STATUS_ID_PM8038_LVS2 = 102,
MSM_RPM_8930_STATUS_ID_NCP_0 = 103,
MSM_RPM_8930_STATUS_ID_NCP_1 = 104,
MSM_RPM_8930_STATUS_ID_CXO_BUFFERS = 105,
MSM_RPM_8930_STATUS_ID_USB_OTG_SWITCH = 106,
MSM_RPM_8930_STATUS_ID_HDMI_SWITCH = 107,
MSM_RPM_8930_STATUS_ID_LAST = MSM_RPM_8930_STATUS_ID_HDMI_SWITCH,
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_8930_H */

761
arch/arm/mach-msm/include/mach/rpm-8960.h
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
/* Copyright (c) 2011-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -13,439 +13,404 @@
#ifndef __ARCH_ARM_MACH_MSM_RPM_8960_H
#define __ARCH_ARM_MACH_MSM_RPM_8960_H
#define RPM_MAJOR_VER 3
#define RPM_MINOR_VER 0
#define RPM_BUILD_VER 0
/* RPM control message RAM enums */
enum {
MSM_RPM_CTRL_VERSION_MAJOR,
MSM_RPM_CTRL_VERSION_MINOR,
MSM_RPM_CTRL_VERSION_BUILD,
MSM_RPM_8960_CTRL_VERSION_MAJOR,
MSM_RPM_8960_CTRL_VERSION_MINOR,
MSM_RPM_8960_CTRL_VERSION_BUILD,
MSM_RPM_CTRL_REQ_CTX_0,
MSM_RPM_CTRL_REQ_CTX_7 = MSM_RPM_CTRL_REQ_CTX_0 + 7,
MSM_RPM_CTRL_REQ_SEL_0,
MSM_RPM_CTRL_REQ_SEL_3 = MSM_RPM_CTRL_REQ_SEL_0 + 3,
MSM_RPM_CTRL_ACK_CTX_0,
MSM_RPM_CTRL_ACK_CTX_7 = MSM_RPM_CTRL_ACK_CTX_0 + 7,
MSM_RPM_CTRL_ACK_SEL_0,
MSM_RPM_CTRL_ACK_SEL_7 = MSM_RPM_CTRL_ACK_SEL_0 + 7,
MSM_RPM_8960_CTRL_REQ_CTX_0,
MSM_RPM_8960_CTRL_REQ_CTX_7 = MSM_RPM_8960_CTRL_REQ_CTX_0 + 7,
MSM_RPM_8960_CTRL_REQ_SEL_0,
MSM_RPM_8960_CTRL_REQ_SEL_3 = MSM_RPM_8960_CTRL_REQ_SEL_0 + 3,
MSM_RPM_8960_CTRL_ACK_CTX_0,
MSM_RPM_8960_CTRL_ACK_CTX_7 = MSM_RPM_8960_CTRL_ACK_CTX_0 + 7,
MSM_RPM_8960_CTRL_ACK_SEL_0,
MSM_RPM_8960_CTRL_ACK_SEL_7 = MSM_RPM_8960_CTRL_ACK_SEL_0 + 7,
};
/* RPM resource select enums defined for RPM core
NOT IN SEQUENTIAL ORDER */
enum {
MSM_RPM_SEL_NOTIFICATION = 0,
MSM_RPM_SEL_INVALIDATE = 1,
MSM_RPM_SEL_TRIGGER_TIMED = 2,
MSM_RPM_SEL_RPM_CTL = 3,
MSM_RPM_8960_SEL_NOTIFICATION = 0,
MSM_RPM_8960_SEL_INVALIDATE = 1,
MSM_RPM_8960_SEL_TRIGGER_TIMED = 2,
MSM_RPM_8960_SEL_RPM_CTL = 3,
MSM_RPM_SEL_CXO_CLK = 5,
MSM_RPM_SEL_PXO_CLK = 6,
MSM_RPM_SEL_QDSS_CLK = 7,
MSM_RPM_SEL_APPS_FABRIC_CLK = 8,
MSM_RPM_SEL_SYSTEM_FABRIC_CLK = 9,
MSM_RPM_SEL_MM_FABRIC_CLK = 10,
MSM_RPM_SEL_DAYTONA_FABRIC_CLK = 11,
MSM_RPM_SEL_SFPB_CLK = 12,
MSM_RPM_SEL_CFPB_CLK = 13,
MSM_RPM_SEL_MMFPB_CLK = 14,
MSM_RPM_SEL_EBI1_CLK = 16,
MSM_RPM_8960_SEL_CXO_CLK = 5,
MSM_RPM_8960_SEL_PXO_CLK = 6,
MSM_RPM_8960_SEL_QDSS_CLK = 7,
MSM_RPM_8960_SEL_APPS_FABRIC_CLK = 8,
MSM_RPM_8960_SEL_SYSTEM_FABRIC_CLK = 9,
MSM_RPM_8960_SEL_MM_FABRIC_CLK = 10,
MSM_RPM_8960_SEL_DAYTONA_FABRIC_CLK = 11,
MSM_RPM_8960_SEL_SFPB_CLK = 12,
MSM_RPM_8960_SEL_CFPB_CLK = 13,
MSM_RPM_8960_SEL_MMFPB_CLK = 14,
MSM_RPM_8960_SEL_EBI1_CLK = 16,
MSM_RPM_SEL_APPS_FABRIC_CFG_HALT = 18,
MSM_RPM_SEL_APPS_FABRIC_CFG_CLKMOD = 19,
MSM_RPM_SEL_APPS_FABRIC_CFG_IOCTL = 20,
MSM_RPM_SEL_APPS_FABRIC_ARB = 21,
MSM_RPM_8960_SEL_APPS_FABRIC_CFG_HALT = 18,
MSM_RPM_8960_SEL_APPS_FABRIC_CFG_CLKMOD = 19,
MSM_RPM_8960_SEL_APPS_FABRIC_CFG_IOCTL = 20,
MSM_RPM_8960_SEL_APPS_FABRIC_ARB = 21,
MSM_RPM_SEL_SYS_FABRIC_CFG_HALT = 22,
MSM_RPM_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
MSM_RPM_SEL_SYS_FABRIC_CFG_IOCTL = 24,
MSM_RPM_SEL_SYSTEM_FABRIC_ARB = 25,
MSM_RPM_8960_SEL_SYS_FABRIC_CFG_HALT = 22,
MSM_RPM_8960_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
MSM_RPM_8960_SEL_SYS_FABRIC_CFG_IOCTL = 24,
MSM_RPM_8960_SEL_SYSTEM_FABRIC_ARB = 25,
MSM_RPM_SEL_MMSS_FABRIC_CFG_HALT = 26,
MSM_RPM_SEL_MMSS_FABRIC_CFG_CLKMOD = 27,
MSM_RPM_SEL_MMSS_FABRIC_CFG_IOCTL = 28,
MSM_RPM_SEL_MM_FABRIC_ARB = 29,
MSM_RPM_8960_SEL_MMSS_FABRIC_CFG_HALT = 26,
MSM_RPM_8960_SEL_MMSS_FABRIC_CFG_CLKMOD = 27,
MSM_RPM_8960_SEL_MMSS_FABRIC_CFG_IOCTL = 28,
MSM_RPM_8960_SEL_MM_FABRIC_ARB = 29,
MSM_RPM_SEL_PM8921_S1 = 30,
MSM_RPM_SEL_PM8921_S2 = 31,
MSM_RPM_SEL_PM8921_S3 = 32,
MSM_RPM_SEL_PM8921_S4 = 33,
MSM_RPM_SEL_PM8921_S5 = 34,
MSM_RPM_SEL_PM8921_S6 = 35,
MSM_RPM_SEL_PM8921_S7 = 36,
MSM_RPM_SEL_PM8921_S8 = 37,
MSM_RPM_SEL_PM8921_L1 = 38,
MSM_RPM_SEL_PM8921_L2 = 39,
MSM_RPM_SEL_PM8921_L3 = 40,
MSM_RPM_SEL_PM8921_L4 = 41,
MSM_RPM_SEL_PM8921_L5 = 42,
MSM_RPM_SEL_PM8921_L6 = 43,
MSM_RPM_SEL_PM8921_L7 = 44,
MSM_RPM_SEL_PM8921_L8 = 45,
MSM_RPM_SEL_PM8921_L9 = 46,
MSM_RPM_SEL_PM8921_L10 = 47,
MSM_RPM_SEL_PM8921_L11 = 48,
MSM_RPM_SEL_PM8921_L12 = 49,
MSM_RPM_SEL_PM8921_L13 = 50,
MSM_RPM_SEL_PM8921_L14 = 51,
MSM_RPM_SEL_PM8921_L15 = 52,
MSM_RPM_SEL_PM8921_L16 = 53,
MSM_RPM_SEL_PM8921_L17 = 54,
MSM_RPM_SEL_PM8921_L18 = 55,
MSM_RPM_SEL_PM8921_L19 = 56,
MSM_RPM_SEL_PM8921_L20 = 57,
MSM_RPM_SEL_PM8921_L21 = 58,
MSM_RPM_SEL_PM8921_L22 = 59,
MSM_RPM_SEL_PM8921_L23 = 60,
MSM_RPM_SEL_PM8921_L24 = 61,
MSM_RPM_SEL_PM8921_L25 = 62,
MSM_RPM_SEL_PM8921_L26 = 63,
MSM_RPM_SEL_PM8921_L27 = 64,
MSM_RPM_SEL_PM8921_L28 = 65,
MSM_RPM_SEL_PM8921_L29 = 66,
MSM_RPM_SEL_PM8921_CLK1 = 67,
MSM_RPM_SEL_PM8921_CLK2 = 68,
MSM_RPM_SEL_PM8921_LVS1 = 69,
MSM_RPM_SEL_PM8921_LVS2 = 70,
MSM_RPM_SEL_PM8921_LVS3 = 71,
MSM_RPM_SEL_PM8921_LVS4 = 72,
MSM_RPM_SEL_PM8921_LVS5 = 73,
MSM_RPM_SEL_PM8921_LVS6 = 74,
MSM_RPM_SEL_PM8921_LVS7 = 75,
MSM_RPM_8960_SEL_PM8921_S1 = 30,
MSM_RPM_8960_SEL_PM8921_S2 = 31,
MSM_RPM_8960_SEL_PM8921_S3 = 32,
MSM_RPM_8960_SEL_PM8921_S4 = 33,
MSM_RPM_8960_SEL_PM8921_S5 = 34,
MSM_RPM_8960_SEL_PM8921_S6 = 35,
MSM_RPM_8960_SEL_PM8921_S7 = 36,
MSM_RPM_8960_SEL_PM8921_S8 = 37,
MSM_RPM_8960_SEL_PM8921_L1 = 38,
MSM_RPM_8960_SEL_PM8921_L2 = 39,
MSM_RPM_8960_SEL_PM8921_L3 = 40,
MSM_RPM_8960_SEL_PM8921_L4 = 41,
MSM_RPM_8960_SEL_PM8921_L5 = 42,
MSM_RPM_8960_SEL_PM8921_L6 = 43,
MSM_RPM_8960_SEL_PM8921_L7 = 44,
MSM_RPM_8960_SEL_PM8921_L8 = 45,
MSM_RPM_8960_SEL_PM8921_L9 = 46,
MSM_RPM_8960_SEL_PM8921_L10 = 47,
MSM_RPM_8960_SEL_PM8921_L11 = 48,
MSM_RPM_8960_SEL_PM8921_L12 = 49,
MSM_RPM_8960_SEL_PM8921_L13 = 50,
MSM_RPM_8960_SEL_PM8921_L14 = 51,
MSM_RPM_8960_SEL_PM8921_L15 = 52,
MSM_RPM_8960_SEL_PM8921_L16 = 53,
MSM_RPM_8960_SEL_PM8921_L17 = 54,
MSM_RPM_8960_SEL_PM8921_L18 = 55,
MSM_RPM_8960_SEL_PM8921_L19 = 56,
MSM_RPM_8960_SEL_PM8921_L20 = 57,
MSM_RPM_8960_SEL_PM8921_L21 = 58,
MSM_RPM_8960_SEL_PM8921_L22 = 59,
MSM_RPM_8960_SEL_PM8921_L23 = 60,
MSM_RPM_8960_SEL_PM8921_L24 = 61,
MSM_RPM_8960_SEL_PM8921_L25 = 62,
MSM_RPM_8960_SEL_PM8921_L26 = 63,
MSM_RPM_8960_SEL_PM8921_L27 = 64,
MSM_RPM_8960_SEL_PM8921_L28 = 65,
MSM_RPM_8960_SEL_PM8921_L29 = 66,
MSM_RPM_8960_SEL_PM8921_CLK1 = 67,
MSM_RPM_8960_SEL_PM8921_CLK2 = 68,
MSM_RPM_8960_SEL_PM8921_LVS1 = 69,
MSM_RPM_8960_SEL_PM8921_LVS2 = 70,
MSM_RPM_8960_SEL_PM8921_LVS3 = 71,
MSM_RPM_8960_SEL_PM8921_LVS4 = 72,
MSM_RPM_8960_SEL_PM8921_LVS5 = 73,
MSM_RPM_8960_SEL_PM8921_LVS6 = 74,
MSM_RPM_8960_SEL_PM8921_LVS7 = 75,
MSM_RPM_SEL_NCP = 80,
MSM_RPM_SEL_CXO_BUFFERS = 81,
MSM_RPM_SEL_USB_OTG_SWITCH = 82,
MSM_RPM_SEL_HDMI_SWITCH = 83,
MSM_RPM_SEL_DDR_DMM = 84,
MSM_RPM_8960_SEL_NCP = 80,
MSM_RPM_8960_SEL_CXO_BUFFERS = 81,
MSM_RPM_8960_SEL_USB_OTG_SWITCH = 82,
MSM_RPM_8960_SEL_HDMI_SWITCH = 83,
MSM_RPM_8960_SEL_DDR_DMM = 84,
MSM_RPM_SEL_LAST = MSM_RPM_SEL_DDR_DMM,
MSM_RPM_8960_SEL_LAST = MSM_RPM_8960_SEL_DDR_DMM,
};
/* RPM resource (4 byte) word ID enum */
enum {
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 = 0,
MSM_RPM_ID_NOTIFICATION_CONFIGURED_3 =
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 3,
MSM_RPM_8960_ID_NOTIFICATION_CONFIGURED_0 = 0,
MSM_RPM_8960_ID_NOTIFICATION_CONFIGURED_3 =
MSM_RPM_8960_ID_NOTIFICATION_CONFIGURED_0 + 3,
MSM_RPM_ID_NOTIFICATION_REGISTERED_0 = 4,
MSM_RPM_ID_NOTIFICATION_REGISTERED_3 =
MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 3,
MSM_RPM_8960_ID_NOTIFICATION_REGISTERED_0 = 4,
MSM_RPM_8960_ID_NOTIFICATION_REGISTERED_3 =
MSM_RPM_8960_ID_NOTIFICATION_REGISTERED_0 + 3,
MSM_RPM_ID_INVALIDATE_0 = 8,
MSM_RPM_ID_INVALIDATE_7 =
MSM_RPM_ID_INVALIDATE_0 + 7,
MSM_RPM_8960_ID_INVALIDATE_0 = 8,
MSM_RPM_8960_ID_INVALIDATE_7 =
MSM_RPM_8960_ID_INVALIDATE_0 + 7,
MSM_RPM_ID_TRIGGER_TIMED_TO = 16,
MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
MSM_RPM_8960_ID_TRIGGER_TIMED_TO = 16,
MSM_RPM_8960_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
MSM_RPM_ID_RPM_CTL = 18,
MSM_RPM_8960_ID_RPM_CTL = 18,
/* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
MSM_RPM_ID_RESERVED_0 = 19,
MSM_RPM_ID_RESERVED_5 =
MSM_RPM_ID_RESERVED_0 + 5,
MSM_RPM_8960_ID_RESERVED_0 = 19,
MSM_RPM_8960_ID_RESERVED_5 =
MSM_RPM_8960_ID_RESERVED_0 + 5,
MSM_RPM_ID_CXO_CLK = 25,
MSM_RPM_ID_PXO_CLK = 26,
MSM_RPM_ID_APPS_FABRIC_CLK = 27,
MSM_RPM_ID_SYSTEM_FABRIC_CLK = 28,
MSM_RPM_ID_MM_FABRIC_CLK = 29,
MSM_RPM_ID_DAYTONA_FABRIC_CLK = 30,
MSM_RPM_ID_SFPB_CLK = 31,
MSM_RPM_ID_CFPB_CLK = 32,
MSM_RPM_ID_MMFPB_CLK = 33,
MSM_RPM_ID_EBI1_CLK = 34,
MSM_RPM_8960_ID_CXO_CLK = 25,
MSM_RPM_8960_ID_PXO_CLK = 26,
MSM_RPM_8960_ID_APPS_FABRIC_CLK = 27,
MSM_RPM_8960_ID_SYSTEM_FABRIC_CLK = 28,
MSM_RPM_8960_ID_MM_FABRIC_CLK = 29,
MSM_RPM_8960_ID_DAYTONA_FABRIC_CLK = 30,
MSM_RPM_8960_ID_SFPB_CLK = 31,
MSM_RPM_8960_ID_CFPB_CLK = 32,
MSM_RPM_8960_ID_MMFPB_CLK = 33,
MSM_RPM_8960_ID_EBI1_CLK = 34,
MSM_RPM_ID_APPS_FABRIC_CFG_HALT_0 = 35,
MSM_RPM_ID_APPS_FABRIC_CFG_HALT_1 = 36,
MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_0 = 37,
MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_1 = 38,
MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_2 = 39,
MSM_RPM_ID_APPS_FABRIC_CFG_IOCTL = 40,
MSM_RPM_ID_APPS_FABRIC_ARB_0 = 41,
MSM_RPM_ID_APPS_FABRIC_ARB_11 =
MSM_RPM_ID_APPS_FABRIC_ARB_0 + 11,
MSM_RPM_8960_ID_APPS_FABRIC_CFG_HALT_0 = 35,
MSM_RPM_8960_ID_APPS_FABRIC_CFG_HALT_1 = 36,
MSM_RPM_8960_ID_APPS_FABRIC_CFG_CLKMOD_0 = 37,
MSM_RPM_8960_ID_APPS_FABRIC_CFG_CLKMOD_1 = 38,
MSM_RPM_8960_ID_APPS_FABRIC_CFG_CLKMOD_2 = 39,
MSM_RPM_8960_ID_APPS_FABRIC_CFG_IOCTL = 40,
MSM_RPM_8960_ID_APPS_FABRIC_ARB_0 = 41,
MSM_RPM_8960_ID_APPS_FABRIC_ARB_11 =
MSM_RPM_8960_ID_APPS_FABRIC_ARB_0 + 11,
MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0 = 53,
MSM_RPM_ID_SYS_FABRIC_CFG_HALT_1 = 54,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0 = 55,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_1 = 56,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_2 = 57,
MSM_RPM_ID_SYS_FABRIC_CFG_IOCTL = 58,
MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 = 59,
MSM_RPM_ID_SYSTEM_FABRIC_ARB_28 =
MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 28,
MSM_RPM_8960_ID_SYS_FABRIC_CFG_HALT_0 = 53,
MSM_RPM_8960_ID_SYS_FABRIC_CFG_HALT_1 = 54,
MSM_RPM_8960_ID_SYS_FABRIC_CFG_CLKMOD_0 = 55,
MSM_RPM_8960_ID_SYS_FABRIC_CFG_CLKMOD_1 = 56,
MSM_RPM_8960_ID_SYS_FABRIC_CFG_CLKMOD_2 = 57,
MSM_RPM_8960_ID_SYS_FABRIC_CFG_IOCTL = 58,
MSM_RPM_8960_ID_SYSTEM_FABRIC_ARB_0 = 59,
MSM_RPM_8960_ID_SYSTEM_FABRIC_ARB_28 =
MSM_RPM_8960_ID_SYSTEM_FABRIC_ARB_0 + 28,
MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_0 = 88,
MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_1 = 89,
MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_0 = 90,
MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_1 = 91,
MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_2 = 92,
MSM_RPM_ID_MMSS_FABRIC_CFG_IOCTL = 93,
MSM_RPM_ID_MM_FABRIC_ARB_0 = 94,
MSM_RPM_ID_MM_FABRIC_ARB_22 =
MSM_RPM_ID_MM_FABRIC_ARB_0 + 22,
MSM_RPM_8960_ID_MMSS_FABRIC_CFG_HALT_0 = 88,
MSM_RPM_8960_ID_MMSS_FABRIC_CFG_HALT_1 = 89,
MSM_RPM_8960_ID_MMSS_FABRIC_CFG_CLKMOD_0 = 90,
MSM_RPM_8960_ID_MMSS_FABRIC_CFG_CLKMOD_1 = 91,
MSM_RPM_8960_ID_MMSS_FABRIC_CFG_CLKMOD_2 = 92,
MSM_RPM_8960_ID_MMSS_FABRIC_CFG_IOCTL = 93,
MSM_RPM_8960_ID_MM_FABRIC_ARB_0 = 94,
MSM_RPM_8960_ID_MM_FABRIC_ARB_22 =
MSM_RPM_8960_ID_MM_FABRIC_ARB_0 + 22,
MSM_RPM_ID_PM8921_S1_0 = 117,
MSM_RPM_ID_PM8921_S1_1 = 118,
MSM_RPM_ID_PM8921_S2_0 = 119,
MSM_RPM_ID_PM8921_S2_1 = 120,
MSM_RPM_ID_PM8921_S3_0 = 121,
MSM_RPM_ID_PM8921_S3_1 = 122,
MSM_RPM_ID_PM8921_S4_0 = 123,
MSM_RPM_ID_PM8921_S4_1 = 124,
MSM_RPM_ID_PM8921_S5_0 = 125,
MSM_RPM_ID_PM8921_S5_1 = 126,
MSM_RPM_ID_PM8921_S6_0 = 127,
MSM_RPM_ID_PM8921_S6_1 = 128,
MSM_RPM_ID_PM8921_S7_0 = 129,
MSM_RPM_ID_PM8921_S7_1 = 130,
MSM_RPM_ID_PM8921_S8_0 = 131,
MSM_RPM_ID_PM8921_S8_1 = 132,
MSM_RPM_ID_PM8921_L1_0 = 133,
MSM_RPM_ID_PM8921_L1_1 = 134,
MSM_RPM_ID_PM8921_L2_0 = 135,
MSM_RPM_ID_PM8921_L2_1 = 136,
MSM_RPM_ID_PM8921_L3_0 = 137,
MSM_RPM_ID_PM8921_L3_1 = 138,
MSM_RPM_ID_PM8921_L4_0 = 139,
MSM_RPM_ID_PM8921_L4_1 = 140,
MSM_RPM_ID_PM8921_L5_0 = 141,
MSM_RPM_ID_PM8921_L5_1 = 142,
MSM_RPM_ID_PM8921_L6_0 = 143,
MSM_RPM_ID_PM8921_L6_1 = 144,
MSM_RPM_ID_PM8921_L7_0 = 145,
MSM_RPM_ID_PM8921_L7_1 = 146,
MSM_RPM_ID_PM8921_L8_0 = 147,
MSM_RPM_ID_PM8921_L8_1 = 148,
MSM_RPM_ID_PM8921_L9_0 = 149,
MSM_RPM_ID_PM8921_L9_1 = 150,
MSM_RPM_ID_PM8921_L10_0 = 151,
MSM_RPM_ID_PM8921_L10_1 = 152,
MSM_RPM_ID_PM8921_L11_0 = 153,
MSM_RPM_ID_PM8921_L11_1 = 154,
MSM_RPM_ID_PM8921_L12_0 = 155,
MSM_RPM_ID_PM8921_L12_1 = 156,
MSM_RPM_ID_PM8921_L13_0 = 157,
MSM_RPM_ID_PM8921_L13_1 = 158,
MSM_RPM_ID_PM8921_L14_0 = 159,
MSM_RPM_ID_PM8921_L14_1 = 160,
MSM_RPM_ID_PM8921_L15_0 = 161,
MSM_RPM_ID_PM8921_L15_1 = 162,
MSM_RPM_ID_PM8921_L16_0 = 163,
MSM_RPM_ID_PM8921_L16_1 = 164,
MSM_RPM_ID_PM8921_L17_0 = 165,
MSM_RPM_ID_PM8921_L17_1 = 166,
MSM_RPM_ID_PM8921_L18_0 = 167,
MSM_RPM_ID_PM8921_L18_1 = 168,
MSM_RPM_ID_PM8921_L19_0 = 169,
MSM_RPM_ID_PM8921_L19_1 = 170,
MSM_RPM_ID_PM8921_L20_0 = 171,
MSM_RPM_ID_PM8921_L20_1 = 172,
MSM_RPM_ID_PM8921_L21_0 = 173,
MSM_RPM_ID_PM8921_L21_1 = 174,
MSM_RPM_ID_PM8921_L22_0 = 175,
MSM_RPM_ID_PM8921_L22_1 = 176,
MSM_RPM_ID_PM8921_L23_0 = 177,
MSM_RPM_ID_PM8921_L23_1 = 178,
MSM_RPM_ID_PM8921_L24_0 = 179,
MSM_RPM_ID_PM8921_L24_1 = 180,
MSM_RPM_ID_PM8921_L25_0 = 181,
MSM_RPM_ID_PM8921_L25_1 = 182,
MSM_RPM_ID_PM8921_L26_0 = 183,
MSM_RPM_ID_PM8921_L26_1 = 184,
MSM_RPM_ID_PM8921_L27_0 = 185,
MSM_RPM_ID_PM8921_L27_1 = 186,
MSM_RPM_ID_PM8921_L28_0 = 187,
MSM_RPM_ID_PM8921_L28_1 = 188,
MSM_RPM_ID_PM8921_L29_0 = 189,
MSM_RPM_ID_PM8921_L29_1 = 190,
MSM_RPM_ID_PM8921_CLK1_0 = 191,
MSM_RPM_ID_PM8921_CLK1_1 = 192,
MSM_RPM_ID_PM8921_CLK2_0 = 193,
MSM_RPM_ID_PM8921_CLK2_1 = 194,
MSM_RPM_ID_PM8921_LVS1 = 195,
MSM_RPM_ID_PM8921_LVS2 = 196,
MSM_RPM_ID_PM8921_LVS3 = 197,
MSM_RPM_ID_PM8921_LVS4 = 198,
MSM_RPM_ID_PM8921_LVS5 = 199,
MSM_RPM_ID_PM8921_LVS6 = 200,
MSM_RPM_ID_PM8921_LVS7 = 201,
MSM_RPM_ID_NCP_0 = 202,
MSM_RPM_ID_NCP_1 = 203,
MSM_RPM_ID_CXO_BUFFERS = 204,
MSM_RPM_ID_USB_OTG_SWITCH = 205,
MSM_RPM_ID_HDMI_SWITCH = 206,
MSM_RPM_ID_DDR_DMM_0 = 207,
MSM_RPM_ID_DDR_DMM_1 = 208,
MSM_RPM_ID_QDSS_CLK = 209,
MSM_RPM_8960_ID_PM8921_S1_0 = 117,
MSM_RPM_8960_ID_PM8921_S1_1 = 118,
MSM_RPM_8960_ID_PM8921_S2_0 = 119,
MSM_RPM_8960_ID_PM8921_S2_1 = 120,
MSM_RPM_8960_ID_PM8921_S3_0 = 121,
MSM_RPM_8960_ID_PM8921_S3_1 = 122,
MSM_RPM_8960_ID_PM8921_S4_0 = 123,
MSM_RPM_8960_ID_PM8921_S4_1 = 124,
MSM_RPM_8960_ID_PM8921_S5_0 = 125,
MSM_RPM_8960_ID_PM8921_S5_1 = 126,
MSM_RPM_8960_ID_PM8921_S6_0 = 127,
MSM_RPM_8960_ID_PM8921_S6_1 = 128,
MSM_RPM_8960_ID_PM8921_S7_0 = 129,
MSM_RPM_8960_ID_PM8921_S7_1 = 130,
MSM_RPM_8960_ID_PM8921_S8_0 = 131,
MSM_RPM_8960_ID_PM8921_S8_1 = 132,
MSM_RPM_8960_ID_PM8921_L1_0 = 133,
MSM_RPM_8960_ID_PM8921_L1_1 = 134,
MSM_RPM_8960_ID_PM8921_L2_0 = 135,
MSM_RPM_8960_ID_PM8921_L2_1 = 136,
MSM_RPM_8960_ID_PM8921_L3_0 = 137,
MSM_RPM_8960_ID_PM8921_L3_1 = 138,
MSM_RPM_8960_ID_PM8921_L4_0 = 139,
MSM_RPM_8960_ID_PM8921_L4_1 = 140,
MSM_RPM_8960_ID_PM8921_L5_0 = 141,
MSM_RPM_8960_ID_PM8921_L5_1 = 142,
MSM_RPM_8960_ID_PM8921_L6_0 = 143,
MSM_RPM_8960_ID_PM8921_L6_1 = 144,
MSM_RPM_8960_ID_PM8921_L7_0 = 145,
MSM_RPM_8960_ID_PM8921_L7_1 = 146,
MSM_RPM_8960_ID_PM8921_L8_0 = 147,
MSM_RPM_8960_ID_PM8921_L8_1 = 148,
MSM_RPM_8960_ID_PM8921_L9_0 = 149,
MSM_RPM_8960_ID_PM8921_L9_1 = 150,
MSM_RPM_8960_ID_PM8921_L10_0 = 151,
MSM_RPM_8960_ID_PM8921_L10_1 = 152,
MSM_RPM_8960_ID_PM8921_L11_0 = 153,
MSM_RPM_8960_ID_PM8921_L11_1 = 154,
MSM_RPM_8960_ID_PM8921_L12_0 = 155,
MSM_RPM_8960_ID_PM8921_L12_1 = 156,
MSM_RPM_8960_ID_PM8921_L13_0 = 157,
MSM_RPM_8960_ID_PM8921_L13_1 = 158,
MSM_RPM_8960_ID_PM8921_L14_0 = 159,
MSM_RPM_8960_ID_PM8921_L14_1 = 160,
MSM_RPM_8960_ID_PM8921_L15_0 = 161,
MSM_RPM_8960_ID_PM8921_L15_1 = 162,
MSM_RPM_8960_ID_PM8921_L16_0 = 163,
MSM_RPM_8960_ID_PM8921_L16_1 = 164,
MSM_RPM_8960_ID_PM8921_L17_0 = 165,
MSM_RPM_8960_ID_PM8921_L17_1 = 166,
MSM_RPM_8960_ID_PM8921_L18_0 = 167,
MSM_RPM_8960_ID_PM8921_L18_1 = 168,
MSM_RPM_8960_ID_PM8921_L19_0 = 169,
MSM_RPM_8960_ID_PM8921_L19_1 = 170,
MSM_RPM_8960_ID_PM8921_L20_0 = 171,
MSM_RPM_8960_ID_PM8921_L20_1 = 172,
MSM_RPM_8960_ID_PM8921_L21_0 = 173,
MSM_RPM_8960_ID_PM8921_L21_1 = 174,
MSM_RPM_8960_ID_PM8921_L22_0 = 175,
MSM_RPM_8960_ID_PM8921_L22_1 = 176,
MSM_RPM_8960_ID_PM8921_L23_0 = 177,
MSM_RPM_8960_ID_PM8921_L23_1 = 178,
MSM_RPM_8960_ID_PM8921_L24_0 = 179,
MSM_RPM_8960_ID_PM8921_L24_1 = 180,
MSM_RPM_8960_ID_PM8921_L25_0 = 181,
MSM_RPM_8960_ID_PM8921_L25_1 = 182,
MSM_RPM_8960_ID_PM8921_L26_0 = 183,
MSM_RPM_8960_ID_PM8921_L26_1 = 184,
MSM_RPM_8960_ID_PM8921_L27_0 = 185,
MSM_RPM_8960_ID_PM8921_L27_1 = 186,
MSM_RPM_8960_ID_PM8921_L28_0 = 187,
MSM_RPM_8960_ID_PM8921_L28_1 = 188,
MSM_RPM_8960_ID_PM8921_L29_0 = 189,
MSM_RPM_8960_ID_PM8921_L29_1 = 190,
MSM_RPM_8960_ID_PM8921_CLK1_0 = 191,
MSM_RPM_8960_ID_PM8921_CLK1_1 = 192,
MSM_RPM_8960_ID_PM8921_CLK2_0 = 193,
MSM_RPM_8960_ID_PM8921_CLK2_1 = 194,
MSM_RPM_8960_ID_PM8921_LVS1 = 195,
MSM_RPM_8960_ID_PM8921_LVS2 = 196,
MSM_RPM_8960_ID_PM8921_LVS3 = 197,
MSM_RPM_8960_ID_PM8921_LVS4 = 198,
MSM_RPM_8960_ID_PM8921_LVS5 = 199,
MSM_RPM_8960_ID_PM8921_LVS6 = 200,
MSM_RPM_8960_ID_PM8921_LVS7 = 201,
MSM_RPM_8960_ID_NCP_0 = 202,
MSM_RPM_8960_ID_NCP_1 = 203,
MSM_RPM_8960_ID_CXO_BUFFERS = 204,
MSM_RPM_8960_ID_USB_OTG_SWITCH = 205,
MSM_RPM_8960_ID_HDMI_SWITCH = 206,
MSM_RPM_8960_ID_DDR_DMM_0 = 207,
MSM_RPM_8960_ID_DDR_DMM_1 = 208,
MSM_RPM_8960_ID_QDSS_CLK = 209,
MSM_RPM_ID_LAST = MSM_RPM_ID_QDSS_CLK,
};
/* RPM resources RPM_ID aliases */
enum {
MSM_RPMRS_ID_RPM_CTL = MSM_RPM_ID_RPM_CTL,
MSM_RPMRS_ID_PXO_CLK = MSM_RPM_ID_PXO_CLK,
MSM_RPMRS_ID_VDD_DIG_0 = MSM_RPM_ID_PM8921_S3_0,
MSM_RPMRS_ID_VDD_DIG_1 = MSM_RPM_ID_PM8921_S3_1,
MSM_RPMRS_ID_VDD_MEM_0 = MSM_RPM_ID_PM8921_L24_0,
MSM_RPMRS_ID_VDD_MEM_1 = MSM_RPM_ID_PM8921_L24_1,
/* MSM8960 L2 cache power control not via RPM
* MSM_RPM_ID_LAST + 1 indicates invalid */
MSM_RPMRS_ID_APPS_L2_CACHE_CTL = MSM_RPM_ID_LAST + 1
};
/* VDD values are in microvolts */
#define MSM_RPMRS_VDD_MASK 0x7fffff
enum {
MSM_RPMRS_VDD_MEM_RET_LOW = 750000,
MSM_RPMRS_VDD_MEM_RET_HIGH = 750000,
MSM_RPMRS_VDD_MEM_ACTIVE = 1050000,
MSM_RPMRS_VDD_MEM_MAX = 1150000,
};
enum {
MSM_RPMRS_VDD_DIG_RET_LOW = 500000,
MSM_RPMRS_VDD_DIG_RET_HIGH = 750000,
MSM_RPMRS_VDD_DIG_ACTIVE = 950000,
MSM_RPMRS_VDD_DIG_MAX = 1150000,
MSM_RPM_8960_ID_LAST = MSM_RPM_8960_ID_QDSS_CLK,
};
/* RPM status ID enum */
enum {
MSM_RPM_STATUS_ID_VERSION_MAJOR = 0,
MSM_RPM_STATUS_ID_VERSION_MINOR = 1,
MSM_RPM_STATUS_ID_VERSION_BUILD = 2,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
MSM_RPM_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
MSM_RPM_STATUS_ID_SEQUENCE = 7,
MSM_RPM_STATUS_ID_RPM_CTL = 8,
MSM_RPM_STATUS_ID_CXO_CLK = 9,
MSM_RPM_STATUS_ID_PXO_CLK = 10,
MSM_RPM_STATUS_ID_APPS_FABRIC_CLK = 11,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK = 12,
MSM_RPM_STATUS_ID_MM_FABRIC_CLK = 13,
MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK = 14,
MSM_RPM_STATUS_ID_SFPB_CLK = 15,
MSM_RPM_STATUS_ID_CFPB_CLK = 16,
MSM_RPM_STATUS_ID_MMFPB_CLK = 17,
MSM_RPM_STATUS_ID_EBI1_CLK = 18,
MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_HALT = 19,
MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_CLKMOD = 20,
MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_IOCTL = 21,
MSM_RPM_STATUS_ID_APPS_FABRIC_ARB = 22,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT = 23,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 24,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 25,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB = 26,
MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_HALT = 27,
MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD = 28,
MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_IOCTL = 29,
MSM_RPM_STATUS_ID_MM_FABRIC_ARB = 30,
MSM_RPM_STATUS_ID_PM8921_S1_0 = 31,
MSM_RPM_STATUS_ID_PM8921_S1_1 = 32,
MSM_RPM_STATUS_ID_PM8921_S2_0 = 33,
MSM_RPM_STATUS_ID_PM8921_S2_1 = 34,
MSM_RPM_STATUS_ID_PM8921_S3_0 = 35,
MSM_RPM_STATUS_ID_PM8921_S3_1 = 36,
MSM_RPM_STATUS_ID_PM8921_S4_0 = 37,
MSM_RPM_STATUS_ID_PM8921_S4_1 = 38,
MSM_RPM_STATUS_ID_PM8921_S5_0 = 39,
MSM_RPM_STATUS_ID_PM8921_S5_1 = 40,
MSM_RPM_STATUS_ID_PM8921_S6_0 = 41,
MSM_RPM_STATUS_ID_PM8921_S6_1 = 42,
MSM_RPM_STATUS_ID_PM8921_S7_0 = 43,
MSM_RPM_STATUS_ID_PM8921_S7_1 = 44,
MSM_RPM_STATUS_ID_PM8921_S8_0 = 45,
MSM_RPM_STATUS_ID_PM8921_S8_1 = 46,
MSM_RPM_STATUS_ID_PM8921_L1_0 = 47,
MSM_RPM_STATUS_ID_PM8921_L1_1 = 48,
MSM_RPM_STATUS_ID_PM8921_L2_0 = 49,
MSM_RPM_STATUS_ID_PM8921_L2_1 = 50,
MSM_RPM_STATUS_ID_PM8921_L3_0 = 51,
MSM_RPM_STATUS_ID_PM8921_L3_1 = 52,
MSM_RPM_STATUS_ID_PM8921_L4_0 = 53,
MSM_RPM_STATUS_ID_PM8921_L4_1 = 54,
MSM_RPM_STATUS_ID_PM8921_L5_0 = 55,
MSM_RPM_STATUS_ID_PM8921_L5_1 = 56,
MSM_RPM_STATUS_ID_PM8921_L6_0 = 57,
MSM_RPM_STATUS_ID_PM8921_L6_1 = 58,
MSM_RPM_STATUS_ID_PM8921_L7_0 = 59,
MSM_RPM_STATUS_ID_PM8921_L7_1 = 60,
MSM_RPM_STATUS_ID_PM8921_L8_0 = 61,
MSM_RPM_STATUS_ID_PM8921_L8_1 = 62,
MSM_RPM_STATUS_ID_PM8921_L9_0 = 63,
MSM_RPM_STATUS_ID_PM8921_L9_1 = 64,
MSM_RPM_STATUS_ID_PM8921_L10_0 = 65,
MSM_RPM_STATUS_ID_PM8921_L10_1 = 66,
MSM_RPM_STATUS_ID_PM8921_L11_0 = 67,
MSM_RPM_STATUS_ID_PM8921_L11_1 = 68,
MSM_RPM_STATUS_ID_PM8921_L12_0 = 69,
MSM_RPM_STATUS_ID_PM8921_L12_1 = 70,
MSM_RPM_STATUS_ID_PM8921_L13_0 = 71,
MSM_RPM_STATUS_ID_PM8921_L13_1 = 72,
MSM_RPM_STATUS_ID_PM8921_L14_0 = 73,
MSM_RPM_STATUS_ID_PM8921_L14_1 = 74,
MSM_RPM_STATUS_ID_PM8921_L15_0 = 75,
MSM_RPM_STATUS_ID_PM8921_L15_1 = 76,
MSM_RPM_STATUS_ID_PM8921_L16_0 = 77,
MSM_RPM_STATUS_ID_PM8921_L16_1 = 78,
MSM_RPM_STATUS_ID_PM8921_L17_0 = 79,
MSM_RPM_STATUS_ID_PM8921_L17_1 = 80,
MSM_RPM_STATUS_ID_PM8921_L18_0 = 81,
MSM_RPM_STATUS_ID_PM8921_L18_1 = 82,
MSM_RPM_STATUS_ID_PM8921_L19_0 = 83,
MSM_RPM_STATUS_ID_PM8921_L19_1 = 84,
MSM_RPM_STATUS_ID_PM8921_L20_0 = 85,
MSM_RPM_STATUS_ID_PM8921_L20_1 = 86,
MSM_RPM_STATUS_ID_PM8921_L21_0 = 87,
MSM_RPM_STATUS_ID_PM8921_L21_1 = 88,
MSM_RPM_STATUS_ID_PM8921_L22_0 = 89,
MSM_RPM_STATUS_ID_PM8921_L22_1 = 90,
MSM_RPM_STATUS_ID_PM8921_L23_0 = 91,
MSM_RPM_STATUS_ID_PM8921_L23_1 = 92,
MSM_RPM_STATUS_ID_PM8921_L24_0 = 93,
MSM_RPM_STATUS_ID_PM8921_L24_1 = 94,
MSM_RPM_STATUS_ID_PM8921_L25_0 = 95,
MSM_RPM_STATUS_ID_PM8921_L25_1 = 96,
MSM_RPM_STATUS_ID_PM8921_L26_0 = 97,
MSM_RPM_STATUS_ID_PM8921_L26_1 = 98,
MSM_RPM_STATUS_ID_PM8921_L27_0 = 99,
MSM_RPM_STATUS_ID_PM8921_L27_1 = 100,
MSM_RPM_STATUS_ID_PM8921_L28_0 = 101,
MSM_RPM_STATUS_ID_PM8921_L28_1 = 102,
MSM_RPM_STATUS_ID_PM8921_L29_0 = 103,
MSM_RPM_STATUS_ID_PM8921_L29_1 = 104,
MSM_RPM_STATUS_ID_PM8921_CLK1_0 = 105,
MSM_RPM_STATUS_ID_PM8921_CLK1_1 = 106,
MSM_RPM_STATUS_ID_PM8921_CLK2_0 = 107,
MSM_RPM_STATUS_ID_PM8921_CLK2_1 = 108,
MSM_RPM_STATUS_ID_PM8921_LVS1 = 109,
MSM_RPM_STATUS_ID_PM8921_LVS2 = 110,
MSM_RPM_STATUS_ID_PM8921_LVS3 = 111,
MSM_RPM_STATUS_ID_PM8921_LVS4 = 112,
MSM_RPM_STATUS_ID_PM8921_LVS5 = 113,
MSM_RPM_STATUS_ID_PM8921_LVS6 = 114,
MSM_RPM_STATUS_ID_PM8921_LVS7 = 115,
MSM_RPM_STATUS_ID_NCP_0 = 116,
MSM_RPM_STATUS_ID_NCP_1 = 117,
MSM_RPM_STATUS_ID_CXO_BUFFERS = 118,
MSM_RPM_STATUS_ID_USB_OTG_SWITCH = 119,
MSM_RPM_STATUS_ID_HDMI_SWITCH = 120,
MSM_RPM_STATUS_ID_DDR_DMM_0 = 121,
MSM_RPM_STATUS_ID_DDR_DMM_1 = 122,
MSM_RPM_STATUS_ID_EBI1_CH0_RANGE = 123,
MSM_RPM_STATUS_ID_EBI1_CH1_RANGE = 124,
MSM_RPM_8960_STATUS_ID_VERSION_MAJOR = 0,
MSM_RPM_8960_STATUS_ID_VERSION_MINOR = 1,
MSM_RPM_8960_STATUS_ID_VERSION_BUILD = 2,
MSM_RPM_8960_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
MSM_RPM_8960_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
MSM_RPM_8960_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
MSM_RPM_8960_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
MSM_RPM_8960_STATUS_ID_SEQUENCE = 7,
MSM_RPM_8960_STATUS_ID_RPM_CTL = 8,
MSM_RPM_8960_STATUS_ID_CXO_CLK = 9,
MSM_RPM_8960_STATUS_ID_PXO_CLK = 10,
MSM_RPM_8960_STATUS_ID_APPS_FABRIC_CLK = 11,
MSM_RPM_8960_STATUS_ID_SYSTEM_FABRIC_CLK = 12,
MSM_RPM_8960_STATUS_ID_MM_FABRIC_CLK = 13,
MSM_RPM_8960_STATUS_ID_DAYTONA_FABRIC_CLK = 14,
MSM_RPM_8960_STATUS_ID_SFPB_CLK = 15,
MSM_RPM_8960_STATUS_ID_CFPB_CLK = 16,
MSM_RPM_8960_STATUS_ID_MMFPB_CLK = 17,
MSM_RPM_8960_STATUS_ID_EBI1_CLK = 18,
MSM_RPM_8960_STATUS_ID_APPS_FABRIC_CFG_HALT = 19,
MSM_RPM_8960_STATUS_ID_APPS_FABRIC_CFG_CLKMOD = 20,
MSM_RPM_8960_STATUS_ID_APPS_FABRIC_CFG_IOCTL = 21,
MSM_RPM_8960_STATUS_ID_APPS_FABRIC_ARB = 22,
MSM_RPM_8960_STATUS_ID_SYS_FABRIC_CFG_HALT = 23,
MSM_RPM_8960_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 24,
MSM_RPM_8960_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 25,
MSM_RPM_8960_STATUS_ID_SYSTEM_FABRIC_ARB = 26,
MSM_RPM_8960_STATUS_ID_MMSS_FABRIC_CFG_HALT = 27,
MSM_RPM_8960_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD = 28,
MSM_RPM_8960_STATUS_ID_MMSS_FABRIC_CFG_IOCTL = 29,
MSM_RPM_8960_STATUS_ID_MM_FABRIC_ARB = 30,
MSM_RPM_8960_STATUS_ID_PM8921_S1_0 = 31,
MSM_RPM_8960_STATUS_ID_PM8921_S1_1 = 32,
MSM_RPM_8960_STATUS_ID_PM8921_S2_0 = 33,
MSM_RPM_8960_STATUS_ID_PM8921_S2_1 = 34,
MSM_RPM_8960_STATUS_ID_PM8921_S3_0 = 35,
MSM_RPM_8960_STATUS_ID_PM8921_S3_1 = 36,
MSM_RPM_8960_STATUS_ID_PM8921_S4_0 = 37,
MSM_RPM_8960_STATUS_ID_PM8921_S4_1 = 38,
MSM_RPM_8960_STATUS_ID_PM8921_S5_0 = 39,
MSM_RPM_8960_STATUS_ID_PM8921_S5_1 = 40,
MSM_RPM_8960_STATUS_ID_PM8921_S6_0 = 41,
MSM_RPM_8960_STATUS_ID_PM8921_S6_1 = 42,
MSM_RPM_8960_STATUS_ID_PM8921_S7_0 = 43,
MSM_RPM_8960_STATUS_ID_PM8921_S7_1 = 44,
MSM_RPM_8960_STATUS_ID_PM8921_S8_0 = 45,
MSM_RPM_8960_STATUS_ID_PM8921_S8_1 = 46,
MSM_RPM_8960_STATUS_ID_PM8921_L1_0 = 47,
MSM_RPM_8960_STATUS_ID_PM8921_L1_1 = 48,
MSM_RPM_8960_STATUS_ID_PM8921_L2_0 = 49,
MSM_RPM_8960_STATUS_ID_PM8921_L2_1 = 50,
MSM_RPM_8960_STATUS_ID_PM8921_L3_0 = 51,
MSM_RPM_8960_STATUS_ID_PM8921_L3_1 = 52,
MSM_RPM_8960_STATUS_ID_PM8921_L4_0 = 53,
MSM_RPM_8960_STATUS_ID_PM8921_L4_1 = 54,
MSM_RPM_8960_STATUS_ID_PM8921_L5_0 = 55,
MSM_RPM_8960_STATUS_ID_PM8921_L5_1 = 56,
MSM_RPM_8960_STATUS_ID_PM8921_L6_0 = 57,
MSM_RPM_8960_STATUS_ID_PM8921_L6_1 = 58,
MSM_RPM_8960_STATUS_ID_PM8921_L7_0 = 59,
MSM_RPM_8960_STATUS_ID_PM8921_L7_1 = 60,
MSM_RPM_8960_STATUS_ID_PM8921_L8_0 = 61,
MSM_RPM_8960_STATUS_ID_PM8921_L8_1 = 62,
MSM_RPM_8960_STATUS_ID_PM8921_L9_0 = 63,
MSM_RPM_8960_STATUS_ID_PM8921_L9_1 = 64,
MSM_RPM_8960_STATUS_ID_PM8921_L10_0 = 65,
MSM_RPM_8960_STATUS_ID_PM8921_L10_1 = 66,
MSM_RPM_8960_STATUS_ID_PM8921_L11_0 = 67,
MSM_RPM_8960_STATUS_ID_PM8921_L11_1 = 68,
MSM_RPM_8960_STATUS_ID_PM8921_L12_0 = 69,
MSM_RPM_8960_STATUS_ID_PM8921_L12_1 = 70,
MSM_RPM_8960_STATUS_ID_PM8921_L13_0 = 71,
MSM_RPM_8960_STATUS_ID_PM8921_L13_1 = 72,
MSM_RPM_8960_STATUS_ID_PM8921_L14_0 = 73,
MSM_RPM_8960_STATUS_ID_PM8921_L14_1 = 74,
MSM_RPM_8960_STATUS_ID_PM8921_L15_0 = 75,
MSM_RPM_8960_STATUS_ID_PM8921_L15_1 = 76,
MSM_RPM_8960_STATUS_ID_PM8921_L16_0 = 77,
MSM_RPM_8960_STATUS_ID_PM8921_L16_1 = 78,
MSM_RPM_8960_STATUS_ID_PM8921_L17_0 = 79,
MSM_RPM_8960_STATUS_ID_PM8921_L17_1 = 80,
MSM_RPM_8960_STATUS_ID_PM8921_L18_0 = 81,
MSM_RPM_8960_STATUS_ID_PM8921_L18_1 = 82,
MSM_RPM_8960_STATUS_ID_PM8921_L19_0 = 83,
MSM_RPM_8960_STATUS_ID_PM8921_L19_1 = 84,
MSM_RPM_8960_STATUS_ID_PM8921_L20_0 = 85,
MSM_RPM_8960_STATUS_ID_PM8921_L20_1 = 86,
MSM_RPM_8960_STATUS_ID_PM8921_L21_0 = 87,
MSM_RPM_8960_STATUS_ID_PM8921_L21_1 = 88,
MSM_RPM_8960_STATUS_ID_PM8921_L22_0 = 89,
MSM_RPM_8960_STATUS_ID_PM8921_L22_1 = 90,
MSM_RPM_8960_STATUS_ID_PM8921_L23_0 = 91,
MSM_RPM_8960_STATUS_ID_PM8921_L23_1 = 92,
MSM_RPM_8960_STATUS_ID_PM8921_L24_0 = 93,
MSM_RPM_8960_STATUS_ID_PM8921_L24_1 = 94,
MSM_RPM_8960_STATUS_ID_PM8921_L25_0 = 95,
MSM_RPM_8960_STATUS_ID_PM8921_L25_1 = 96,
MSM_RPM_8960_STATUS_ID_PM8921_L26_0 = 97,
MSM_RPM_8960_STATUS_ID_PM8921_L26_1 = 98,
MSM_RPM_8960_STATUS_ID_PM8921_L27_0 = 99,
MSM_RPM_8960_STATUS_ID_PM8921_L27_1 = 100,
MSM_RPM_8960_STATUS_ID_PM8921_L28_0 = 101,
MSM_RPM_8960_STATUS_ID_PM8921_L28_1 = 102,
MSM_RPM_8960_STATUS_ID_PM8921_L29_0 = 103,
MSM_RPM_8960_STATUS_ID_PM8921_L29_1 = 104,
MSM_RPM_8960_STATUS_ID_PM8921_CLK1_0 = 105,
MSM_RPM_8960_STATUS_ID_PM8921_CLK1_1 = 106,
MSM_RPM_8960_STATUS_ID_PM8921_CLK2_0 = 107,
MSM_RPM_8960_STATUS_ID_PM8921_CLK2_1 = 108,
MSM_RPM_8960_STATUS_ID_PM8921_LVS1 = 109,
MSM_RPM_8960_STATUS_ID_PM8921_LVS2 = 110,
MSM_RPM_8960_STATUS_ID_PM8921_LVS3 = 111,
MSM_RPM_8960_STATUS_ID_PM8921_LVS4 = 112,
MSM_RPM_8960_STATUS_ID_PM8921_LVS5 = 113,
MSM_RPM_8960_STATUS_ID_PM8921_LVS6 = 114,
MSM_RPM_8960_STATUS_ID_PM8921_LVS7 = 115,
MSM_RPM_8960_STATUS_ID_NCP_0 = 116,
MSM_RPM_8960_STATUS_ID_NCP_1 = 117,
MSM_RPM_8960_STATUS_ID_CXO_BUFFERS = 118,
MSM_RPM_8960_STATUS_ID_USB_OTG_SWITCH = 119,
MSM_RPM_8960_STATUS_ID_HDMI_SWITCH = 120,
MSM_RPM_8960_STATUS_ID_DDR_DMM_0 = 121,
MSM_RPM_8960_STATUS_ID_DDR_DMM_1 = 122,
MSM_RPM_8960_STATUS_ID_EBI1_CH0_RANGE = 123,
MSM_RPM_8960_STATUS_ID_EBI1_CH1_RANGE = 124,
MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_EBI1_CH1_RANGE,
MSM_RPM_8960_STATUS_ID_LAST = MSM_RPM_8960_STATUS_ID_EBI1_CH1_RANGE,
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_8960_H */

416
arch/arm/mach-msm/include/mach/rpm-9615.h
View File

@@ -13,264 +13,226 @@
#ifndef __ARCH_ARM_MACH_MSM_RPM_9615_H
#define __ARCH_ARM_MACH_MSM_RPM_9615_H
#define RPM_MAJOR_VER 3
#define RPM_MINOR_VER 0
#define RPM_BUILD_VER 0
/* RPM control message RAM enums */
enum {
MSM_RPM_CTRL_VERSION_MAJOR,
MSM_RPM_CTRL_VERSION_MINOR,
MSM_RPM_CTRL_VERSION_BUILD,
MSM_RPM_9615_CTRL_VERSION_MAJOR,
MSM_RPM_9615_CTRL_VERSION_MINOR,
MSM_RPM_9615_CTRL_VERSION_BUILD,
MSM_RPM_CTRL_REQ_CTX_0,
MSM_RPM_CTRL_REQ_CTX_7 = MSM_RPM_CTRL_REQ_CTX_0 + 7,
MSM_RPM_CTRL_REQ_SEL_0,
MSM_RPM_CTRL_REQ_SEL_3 = MSM_RPM_CTRL_REQ_SEL_0 + 3,
MSM_RPM_CTRL_ACK_CTX_0,
MSM_RPM_CTRL_ACK_CTX_7 = MSM_RPM_CTRL_ACK_CTX_0 + 7,
MSM_RPM_CTRL_ACK_SEL_0,
MSM_RPM_CTRL_ACK_SEL_7 = MSM_RPM_CTRL_ACK_SEL_0 + 7,
MSM_RPM_9615_CTRL_REQ_CTX_0,
MSM_RPM_9615_CTRL_REQ_CTX_7 = MSM_RPM_9615_CTRL_REQ_CTX_0 + 7,
MSM_RPM_9615_CTRL_REQ_SEL_0,
MSM_RPM_9615_CTRL_REQ_SEL_3 = MSM_RPM_9615_CTRL_REQ_SEL_0 + 3,
MSM_RPM_9615_CTRL_ACK_CTX_0,
MSM_RPM_9615_CTRL_ACK_CTX_7 = MSM_RPM_9615_CTRL_ACK_CTX_0 + 7,
MSM_RPM_9615_CTRL_ACK_SEL_0,
MSM_RPM_9615_CTRL_ACK_SEL_7 = MSM_RPM_9615_CTRL_ACK_SEL_0 + 7,
};
/* RPM resource select enums defined for RPM core
NOT IN SEQUENTIAL ORDER */
enum {
MSM_RPM_SEL_NOTIFICATION = 0,
MSM_RPM_SEL_INVALIDATE = 1,
MSM_RPM_SEL_TRIGGER_TIMED = 2,
MSM_RPM_SEL_RPM_CTL = 3,
MSM_RPM_9615_SEL_NOTIFICATION = 0,
MSM_RPM_9615_SEL_INVALIDATE = 1,
MSM_RPM_9615_SEL_TRIGGER_TIMED = 2,
MSM_RPM_9615_SEL_RPM_CTL = 3,
MSM_RPM_SEL_CXO_CLK = 5,
MSM_RPM_SEL_SYSTEM_FABRIC_CLK = 9,
MSM_RPM_SEL_DAYTONA_FABRIC_CLK = 11,
MSM_RPM_SEL_SFPB_CLK = 12,
MSM_RPM_SEL_CFPB_CLK = 13,
MSM_RPM_SEL_EBI1_CLK = 16,
MSM_RPM_9615_SEL_CXO_CLK = 5,
MSM_RPM_9615_SEL_SYSTEM_FABRIC_CLK = 9,
MSM_RPM_9615_SEL_DAYTONA_FABRIC_CLK = 11,
MSM_RPM_9615_SEL_SFPB_CLK = 12,
MSM_RPM_9615_SEL_CFPB_CLK = 13,
MSM_RPM_9615_SEL_EBI1_CLK = 16,
MSM_RPM_SEL_SYS_FABRIC_CFG_HALT = 22,
MSM_RPM_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
MSM_RPM_SEL_SYS_FABRIC_CFG_IOCTL = 24,
MSM_RPM_SEL_SYSTEM_FABRIC_ARB = 25,
MSM_RPM_9615_SEL_SYS_FABRIC_CFG_HALT = 22,
MSM_RPM_9615_SEL_SYS_FABRIC_CFG_CLKMOD = 23,
MSM_RPM_9615_SEL_SYS_FABRIC_CFG_IOCTL = 24,
MSM_RPM_9615_SEL_SYSTEM_FABRIC_ARB = 25,
MSM_RPM_SEL_PM8018_S1 = 30,
MSM_RPM_SEL_PM8018_S2 = 31,
MSM_RPM_SEL_PM8018_S3 = 32,
MSM_RPM_SEL_PM8018_S4 = 33,
MSM_RPM_SEL_PM8018_S5 = 34,
MSM_RPM_SEL_PM8018_L1 = 35,
MSM_RPM_SEL_PM8018_L2 = 36,
MSM_RPM_SEL_PM8018_L3 = 37,
MSM_RPM_SEL_PM8018_L4 = 38,
MSM_RPM_SEL_PM8018_L5 = 39,
MSM_RPM_SEL_PM8018_L6 = 40,
MSM_RPM_SEL_PM8018_L7 = 41,
MSM_RPM_SEL_PM8018_L8 = 42,
MSM_RPM_SEL_PM8018_L9 = 43,
MSM_RPM_SEL_PM8018_L10 = 44,
MSM_RPM_SEL_PM8018_L11 = 45,
MSM_RPM_SEL_PM8018_L12 = 46,
MSM_RPM_SEL_PM8018_L13 = 47,
MSM_RPM_SEL_PM8018_L14 = 48,
MSM_RPM_SEL_PM8018_LVS1 = 49,
MSM_RPM_9615_SEL_PM8018_S1 = 30,
MSM_RPM_9615_SEL_PM8018_S2 = 31,
MSM_RPM_9615_SEL_PM8018_S3 = 32,
MSM_RPM_9615_SEL_PM8018_S4 = 33,
MSM_RPM_9615_SEL_PM8018_S5 = 34,
MSM_RPM_9615_SEL_PM8018_L1 = 35,
MSM_RPM_9615_SEL_PM8018_L2 = 36,
MSM_RPM_9615_SEL_PM8018_L3 = 37,
MSM_RPM_9615_SEL_PM8018_L4 = 38,
MSM_RPM_9615_SEL_PM8018_L5 = 39,
MSM_RPM_9615_SEL_PM8018_L6 = 40,
MSM_RPM_9615_SEL_PM8018_L7 = 41,
MSM_RPM_9615_SEL_PM8018_L8 = 42,
MSM_RPM_9615_SEL_PM8018_L9 = 43,
MSM_RPM_9615_SEL_PM8018_L10 = 44,
MSM_RPM_9615_SEL_PM8018_L11 = 45,
MSM_RPM_9615_SEL_PM8018_L12 = 46,
MSM_RPM_9615_SEL_PM8018_L13 = 47,
MSM_RPM_9615_SEL_PM8018_L14 = 48,
MSM_RPM_9615_SEL_PM8018_LVS1 = 49,
MSM_RPM_SEL_NCP = 80,
MSM_RPM_SEL_CXO_BUFFERS = 81,
MSM_RPM_SEL_USB_OTG_SWITCH = 82,
MSM_RPM_SEL_HDMI_SWITCH = 83,
MSM_RPM_9615_SEL_NCP = 80,
MSM_RPM_9615_SEL_CXO_BUFFERS = 81,
MSM_RPM_9615_SEL_USB_OTG_SWITCH = 82,
MSM_RPM_9615_SEL_HDMI_SWITCH = 83,
MSM_RPM_SEL_LAST = MSM_RPM_SEL_HDMI_SWITCH,
MSM_RPM_9615_SEL_LAST = MSM_RPM_9615_SEL_HDMI_SWITCH,
};
/* RPM resource (4 byte) word ID enum */
enum {
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 = 0,
MSM_RPM_ID_NOTIFICATION_CONFIGURED_3 =
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 3,
MSM_RPM_9615_ID_NOTIFICATION_CONFIGURED_0 = 0,
MSM_RPM_9615_ID_NOTIFICATION_CONFIGURED_3 =
MSM_RPM_9615_ID_NOTIFICATION_CONFIGURED_0 + 3,
MSM_RPM_ID_NOTIFICATION_REGISTERED_0 = 4,
MSM_RPM_ID_NOTIFICATION_REGISTERED_3 =
MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 3,
MSM_RPM_9615_ID_NOTIFICATION_REGISTERED_0 = 4,
MSM_RPM_9615_ID_NOTIFICATION_REGISTERED_3 =
MSM_RPM_9615_ID_NOTIFICATION_REGISTERED_0 + 3,
MSM_RPM_ID_INVALIDATE_0 = 8,
MSM_RPM_ID_INVALIDATE_7 =
MSM_RPM_ID_INVALIDATE_0 + 7,
MSM_RPM_9615_ID_INVALIDATE_0 = 8,
MSM_RPM_9615_ID_INVALIDATE_7 =
MSM_RPM_9615_ID_INVALIDATE_0 + 7,
MSM_RPM_ID_TRIGGER_TIMED_TO = 16,
MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
MSM_RPM_9615_ID_TRIGGER_TIMED_TO = 16,
MSM_RPM_9615_ID_TRIGGER_TIMED_SCLK_COUNT = 17,
MSM_RPM_ID_RPM_CTL = 18,
MSM_RPM_9615_ID_RPM_CTL = 18,
/* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
MSM_RPM_ID_RESERVED_0 = 19,
MSM_RPM_ID_RESERVED_5 =
MSM_RPM_ID_RESERVED_0 + 5,
MSM_RPM_9615_ID_RESERVED_0 = 19,
MSM_RPM_9615_ID_RESERVED_5 =
MSM_RPM_9615_ID_RESERVED_0 + 5,
MSM_RPM_ID_CXO_CLK = 25,
MSM_RPM_ID_SYSTEM_FABRIC_CLK = 26,
MSM_RPM_ID_DAYTONA_FABRIC_CLK = 27,
MSM_RPM_ID_SFPB_CLK = 28,
MSM_RPM_ID_CFPB_CLK = 29,
MSM_RPM_ID_EBI1_CLK = 30,
MSM_RPM_9615_ID_CXO_CLK = 25,
MSM_RPM_9615_ID_SYSTEM_FABRIC_CLK = 26,
MSM_RPM_9615_ID_DAYTONA_FABRIC_CLK = 27,
MSM_RPM_9615_ID_SFPB_CLK = 28,
MSM_RPM_9615_ID_CFPB_CLK = 29,
MSM_RPM_9615_ID_EBI1_CLK = 30,
MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0 = 31,
MSM_RPM_ID_SYS_FABRIC_CFG_HALT_1 = 32,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0 = 33,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_1 = 34,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_2 = 35,
MSM_RPM_ID_SYS_FABRIC_CFG_IOCTL = 36,
MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 = 37,
MSM_RPM_ID_SYSTEM_FABRIC_ARB_26 =
MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 26,
MSM_RPM_9615_ID_SYS_FABRIC_CFG_HALT_0 = 31,
MSM_RPM_9615_ID_SYS_FABRIC_CFG_HALT_1 = 32,
MSM_RPM_9615_ID_SYS_FABRIC_CFG_CLKMOD_0 = 33,
MSM_RPM_9615_ID_SYS_FABRIC_CFG_CLKMOD_1 = 34,
MSM_RPM_9615_ID_SYS_FABRIC_CFG_CLKMOD_2 = 35,
MSM_RPM_9615_ID_SYS_FABRIC_CFG_IOCTL = 36,
MSM_RPM_9615_ID_SYSTEM_FABRIC_ARB_0 = 37,
MSM_RPM_9615_ID_SYSTEM_FABRIC_ARB_26 =
MSM_RPM_9615_ID_SYSTEM_FABRIC_ARB_0 + 26,
MSM_RPM_ID_PM8018_S1_0 = 64,
MSM_RPM_ID_PM8018_S1_1 = 65,
MSM_RPM_ID_PM8018_S2_0 = 66,
MSM_RPM_ID_PM8018_S2_1 = 67,
MSM_RPM_ID_PM8018_S3_0 = 68,
MSM_RPM_ID_PM8018_S3_1 = 69,
MSM_RPM_ID_PM8018_S4_0 = 70,
MSM_RPM_ID_PM8018_S4_1 = 71,
MSM_RPM_ID_PM8018_S5_0 = 72,
MSM_RPM_ID_PM8018_S5_1 = 73,
MSM_RPM_ID_PM8018_L1_0 = 74,
MSM_RPM_ID_PM8018_L1_1 = 75,
MSM_RPM_ID_PM8018_L2_0 = 76,
MSM_RPM_ID_PM8018_L2_1 = 77,
MSM_RPM_ID_PM8018_L3_0 = 78,
MSM_RPM_ID_PM8018_L3_1 = 79,
MSM_RPM_ID_PM8018_L4_0 = 80,
MSM_RPM_ID_PM8018_L4_1 = 81,
MSM_RPM_ID_PM8018_L5_0 = 82,
MSM_RPM_ID_PM8018_L5_1 = 83,
MSM_RPM_ID_PM8018_L6_0 = 84,
MSM_RPM_ID_PM8018_L6_1 = 85,
MSM_RPM_ID_PM8018_L7_0 = 86,
MSM_RPM_ID_PM8018_L7_1 = 87,
MSM_RPM_ID_PM8018_L8_0 = 88,
MSM_RPM_ID_PM8018_L8_1 = 89,
MSM_RPM_ID_PM8018_L9_0 = 90,
MSM_RPM_ID_PM8018_L9_1 = 91,
MSM_RPM_ID_PM8018_L10_0 = 92,
MSM_RPM_ID_PM8018_L10_1 = 93,
MSM_RPM_ID_PM8018_L11_0 = 94,
MSM_RPM_ID_PM8018_L11_1 = 95,
MSM_RPM_ID_PM8018_L12_0 = 96,
MSM_RPM_ID_PM8018_L12_1 = 97,
MSM_RPM_ID_PM8018_L13_0 = 98,
MSM_RPM_ID_PM8018_L13_1 = 99,
MSM_RPM_ID_PM8018_L14_0 = 100,
MSM_RPM_ID_PM8018_L14_1 = 101,
MSM_RPM_ID_PM8018_LVS1 = 102,
MSM_RPM_9615_ID_PM8018_S1_0 = 64,
MSM_RPM_9615_ID_PM8018_S1_1 = 65,
MSM_RPM_9615_ID_PM8018_S2_0 = 66,
MSM_RPM_9615_ID_PM8018_S2_1 = 67,
MSM_RPM_9615_ID_PM8018_S3_0 = 68,
MSM_RPM_9615_ID_PM8018_S3_1 = 69,
MSM_RPM_9615_ID_PM8018_S4_0 = 70,
MSM_RPM_9615_ID_PM8018_S4_1 = 71,
MSM_RPM_9615_ID_PM8018_S5_0 = 72,
MSM_RPM_9615_ID_PM8018_S5_1 = 73,
MSM_RPM_9615_ID_PM8018_L1_0 = 74,
MSM_RPM_9615_ID_PM8018_L1_1 = 75,
MSM_RPM_9615_ID_PM8018_L2_0 = 76,
MSM_RPM_9615_ID_PM8018_L2_1 = 77,
MSM_RPM_9615_ID_PM8018_L3_0 = 78,
MSM_RPM_9615_ID_PM8018_L3_1 = 79,
MSM_RPM_9615_ID_PM8018_L4_0 = 80,
MSM_RPM_9615_ID_PM8018_L4_1 = 81,
MSM_RPM_9615_ID_PM8018_L5_0 = 82,
MSM_RPM_9615_ID_PM8018_L5_1 = 83,
MSM_RPM_9615_ID_PM8018_L6_0 = 84,
MSM_RPM_9615_ID_PM8018_L6_1 = 85,
MSM_RPM_9615_ID_PM8018_L7_0 = 86,
MSM_RPM_9615_ID_PM8018_L7_1 = 87,
MSM_RPM_9615_ID_PM8018_L8_0 = 88,
MSM_RPM_9615_ID_PM8018_L8_1 = 89,
MSM_RPM_9615_ID_PM8018_L9_0 = 90,
MSM_RPM_9615_ID_PM8018_L9_1 = 91,
MSM_RPM_9615_ID_PM8018_L10_0 = 92,
MSM_RPM_9615_ID_PM8018_L10_1 = 93,
MSM_RPM_9615_ID_PM8018_L11_0 = 94,
MSM_RPM_9615_ID_PM8018_L11_1 = 95,
MSM_RPM_9615_ID_PM8018_L12_0 = 96,
MSM_RPM_9615_ID_PM8018_L12_1 = 97,
MSM_RPM_9615_ID_PM8018_L13_0 = 98,
MSM_RPM_9615_ID_PM8018_L13_1 = 99,
MSM_RPM_9615_ID_PM8018_L14_0 = 100,
MSM_RPM_9615_ID_PM8018_L14_1 = 101,
MSM_RPM_9615_ID_PM8018_LVS1 = 102,
MSM_RPM_ID_NCP_0 = 103,
MSM_RPM_ID_NCP_1 = 104,
MSM_RPM_ID_CXO_BUFFERS = 105,
MSM_RPM_ID_USB_OTG_SWITCH = 106,
MSM_RPM_ID_HDMI_SWITCH = 107,
MSM_RPM_9615_ID_NCP_0 = 103,
MSM_RPM_9615_ID_NCP_1 = 104,
MSM_RPM_9615_ID_CXO_BUFFERS = 105,
MSM_RPM_9615_ID_USB_OTG_SWITCH = 106,
MSM_RPM_9615_ID_HDMI_SWITCH = 107,
MSM_RPM_ID_LAST = MSM_RPM_ID_HDMI_SWITCH,
};
/* RPM resources RPM_ID aliases */
enum {
MSM_RPMRS_ID_RPM_CTL = MSM_RPM_ID_RPM_CTL,
/* XO clock for this target is CXO */
MSM_RPMRS_ID_PXO_CLK = MSM_RPM_ID_CXO_CLK,
MSM_RPMRS_ID_VDD_DIG_0 = MSM_RPM_ID_PM8018_S1_0,
MSM_RPMRS_ID_VDD_DIG_1 = MSM_RPM_ID_PM8018_S1_1,
MSM_RPMRS_ID_VDD_MEM_0 = MSM_RPM_ID_PM8018_L9_0,
MSM_RPMRS_ID_VDD_MEM_1 = MSM_RPM_ID_PM8018_L9_1,
/* MSM9615 L2 cache power control not via RPM
* MSM_RPM_ID_LAST + 1 indicates invalid */
MSM_RPMRS_ID_APPS_L2_CACHE_CTL = MSM_RPM_ID_LAST + 1
};
/* VDD values are in microvolts */
#define MSM_RPMRS_VDD_MASK 0x7fffff
enum {
MSM_RPMRS_VDD_MEM_RET_LOW = 750000,
MSM_RPMRS_VDD_MEM_RET_HIGH = 750000,
MSM_RPMRS_VDD_MEM_ACTIVE = 1050000,
MSM_RPMRS_VDD_MEM_MAX = 1150000,
};
enum {
MSM_RPMRS_VDD_DIG_RET_LOW = 500000,
MSM_RPMRS_VDD_DIG_RET_HIGH = 750000,
MSM_RPMRS_VDD_DIG_ACTIVE = 950000,
MSM_RPMRS_VDD_DIG_MAX = 1150000,
MSM_RPM_9615_ID_LAST = MSM_RPM_9615_ID_HDMI_SWITCH,
};
/* RPM status ID enum */
enum {
MSM_RPM_STATUS_ID_VERSION_MAJOR = 0,
MSM_RPM_STATUS_ID_VERSION_MINOR = 1,
MSM_RPM_STATUS_ID_VERSION_BUILD = 2,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
MSM_RPM_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
MSM_RPM_STATUS_ID_SEQUENCE = 7,
MSM_RPM_STATUS_ID_RPM_CTL = 8,
MSM_RPM_STATUS_ID_CXO_CLK = 9,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK = 10,
MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK = 11,
MSM_RPM_STATUS_ID_SFPB_CLK = 12,
MSM_RPM_STATUS_ID_CFPB_CLK = 13,
MSM_RPM_STATUS_ID_EBI1_CLK = 14,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT = 15,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 16,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 17,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB = 18,
MSM_RPM_STATUS_ID_PM8018_S1_0 = 19,
MSM_RPM_STATUS_ID_PM8018_S1_1 = 20,
MSM_RPM_STATUS_ID_PM8018_S2_0 = 21,
MSM_RPM_STATUS_ID_PM8018_S2_1 = 22,
MSM_RPM_STATUS_ID_PM8018_S3_0 = 23,
MSM_RPM_STATUS_ID_PM8018_S3_1 = 24,
MSM_RPM_STATUS_ID_PM8018_S4_0 = 25,
MSM_RPM_STATUS_ID_PM8018_S4_1 = 26,
MSM_RPM_STATUS_ID_PM8018_S5_0 = 27,
MSM_RPM_STATUS_ID_PM8018_S5_1 = 28,
MSM_RPM_STATUS_ID_PM8018_L1_0 = 29,
MSM_RPM_STATUS_ID_PM8018_L1_1 = 30,
MSM_RPM_STATUS_ID_PM8018_L2_0 = 31,
MSM_RPM_STATUS_ID_PM8018_L2_1 = 32,
MSM_RPM_STATUS_ID_PM8018_L3_0 = 33,
MSM_RPM_STATUS_ID_PM8018_L3_1 = 34,
MSM_RPM_STATUS_ID_PM8018_L4_0 = 35,
MSM_RPM_STATUS_ID_PM8018_L4_1 = 36,
MSM_RPM_STATUS_ID_PM8018_L5_0 = 37,
MSM_RPM_STATUS_ID_PM8018_L5_1 = 38,
MSM_RPM_STATUS_ID_PM8018_L6_0 = 39,
MSM_RPM_STATUS_ID_PM8018_L6_1 = 40,
MSM_RPM_STATUS_ID_PM8018_L7_0 = 41,
MSM_RPM_STATUS_ID_PM8018_L7_1 = 42,
MSM_RPM_STATUS_ID_PM8018_L8_0 = 43,
MSM_RPM_STATUS_ID_PM8018_L8_1 = 44,
MSM_RPM_STATUS_ID_PM8018_L9_0 = 45,
MSM_RPM_STATUS_ID_PM8018_L9_1 = 46,
MSM_RPM_STATUS_ID_PM8018_L10_0 = 47,
MSM_RPM_STATUS_ID_PM8018_L10_1 = 48,
MSM_RPM_STATUS_ID_PM8018_L11_0 = 49,
MSM_RPM_STATUS_ID_PM8018_L11_1 = 50,
MSM_RPM_STATUS_ID_PM8018_L12_0 = 51,
MSM_RPM_STATUS_ID_PM8018_L12_1 = 52,
MSM_RPM_STATUS_ID_PM8018_L13_0 = 53,
MSM_RPM_STATUS_ID_PM8018_L13_1 = 54,
MSM_RPM_STATUS_ID_PM8018_L14_0 = 55,
MSM_RPM_STATUS_ID_PM8018_L14_1 = 56,
MSM_RPM_STATUS_ID_PM8018_LVS1 = 57,
MSM_RPM_STATUS_ID_NCP_0 = 58,
MSM_RPM_STATUS_ID_NCP_1 = 59,
MSM_RPM_STATUS_ID_CXO_BUFFERS = 60,
MSM_RPM_STATUS_ID_USB_OTG_SWITCH = 61,
MSM_RPM_STATUS_ID_HDMI_SWITCH = 62,
MSM_RPM_9615_STATUS_ID_VERSION_MAJOR = 0,
MSM_RPM_9615_STATUS_ID_VERSION_MINOR = 1,
MSM_RPM_9615_STATUS_ID_VERSION_BUILD = 2,
MSM_RPM_9615_STATUS_ID_SUPPORTED_RESOURCES_0 = 3,
MSM_RPM_9615_STATUS_ID_SUPPORTED_RESOURCES_1 = 4,
MSM_RPM_9615_STATUS_ID_SUPPORTED_RESOURCES_2 = 5,
MSM_RPM_9615_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0 = 6,
MSM_RPM_9615_STATUS_ID_SEQUENCE = 7,
MSM_RPM_9615_STATUS_ID_RPM_CTL = 8,
MSM_RPM_9615_STATUS_ID_CXO_CLK = 9,
MSM_RPM_9615_STATUS_ID_SYSTEM_FABRIC_CLK = 10,
MSM_RPM_9615_STATUS_ID_DAYTONA_FABRIC_CLK = 11,
MSM_RPM_9615_STATUS_ID_SFPB_CLK = 12,
MSM_RPM_9615_STATUS_ID_CFPB_CLK = 13,
MSM_RPM_9615_STATUS_ID_EBI1_CLK = 14,
MSM_RPM_9615_STATUS_ID_SYS_FABRIC_CFG_HALT = 15,
MSM_RPM_9615_STATUS_ID_SYS_FABRIC_CFG_CLKMOD = 16,
MSM_RPM_9615_STATUS_ID_SYS_FABRIC_CFG_IOCTL = 17,
MSM_RPM_9615_STATUS_ID_SYSTEM_FABRIC_ARB = 18,
MSM_RPM_9615_STATUS_ID_PM8018_S1_0 = 19,
MSM_RPM_9615_STATUS_ID_PM8018_S1_1 = 20,
MSM_RPM_9615_STATUS_ID_PM8018_S2_0 = 21,
MSM_RPM_9615_STATUS_ID_PM8018_S2_1 = 22,
MSM_RPM_9615_STATUS_ID_PM8018_S3_0 = 23,
MSM_RPM_9615_STATUS_ID_PM8018_S3_1 = 24,
MSM_RPM_9615_STATUS_ID_PM8018_S4_0 = 25,
MSM_RPM_9615_STATUS_ID_PM8018_S4_1 = 26,
MSM_RPM_9615_STATUS_ID_PM8018_S5_0 = 27,
MSM_RPM_9615_STATUS_ID_PM8018_S5_1 = 28,
MSM_RPM_9615_STATUS_ID_PM8018_L1_0 = 29,
MSM_RPM_9615_STATUS_ID_PM8018_L1_1 = 30,
MSM_RPM_9615_STATUS_ID_PM8018_L2_0 = 31,
MSM_RPM_9615_STATUS_ID_PM8018_L2_1 = 32,
MSM_RPM_9615_STATUS_ID_PM8018_L3_0 = 33,
MSM_RPM_9615_STATUS_ID_PM8018_L3_1 = 34,
MSM_RPM_9615_STATUS_ID_PM8018_L4_0 = 35,
MSM_RPM_9615_STATUS_ID_PM8018_L4_1 = 36,
MSM_RPM_9615_STATUS_ID_PM8018_L5_0 = 37,
MSM_RPM_9615_STATUS_ID_PM8018_L5_1 = 38,
MSM_RPM_9615_STATUS_ID_PM8018_L6_0 = 39,
MSM_RPM_9615_STATUS_ID_PM8018_L6_1 = 40,
MSM_RPM_9615_STATUS_ID_PM8018_L7_0 = 41,
MSM_RPM_9615_STATUS_ID_PM8018_L7_1 = 42,
MSM_RPM_9615_STATUS_ID_PM8018_L8_0 = 43,
MSM_RPM_9615_STATUS_ID_PM8018_L8_1 = 44,
MSM_RPM_9615_STATUS_ID_PM8018_L9_0 = 45,
MSM_RPM_9615_STATUS_ID_PM8018_L9_1 = 46,
MSM_RPM_9615_STATUS_ID_PM8018_L10_0 = 47,
MSM_RPM_9615_STATUS_ID_PM8018_L10_1 = 48,
MSM_RPM_9615_STATUS_ID_PM8018_L11_0 = 49,
MSM_RPM_9615_STATUS_ID_PM8018_L11_1 = 50,
MSM_RPM_9615_STATUS_ID_PM8018_L12_0 = 51,
MSM_RPM_9615_STATUS_ID_PM8018_L12_1 = 52,
MSM_RPM_9615_STATUS_ID_PM8018_L13_0 = 53,
MSM_RPM_9615_STATUS_ID_PM8018_L13_1 = 54,
MSM_RPM_9615_STATUS_ID_PM8018_L14_0 = 55,
MSM_RPM_9615_STATUS_ID_PM8018_L14_1 = 56,
MSM_RPM_9615_STATUS_ID_PM8018_LVS1 = 57,
MSM_RPM_9615_STATUS_ID_NCP_0 = 58,
MSM_RPM_9615_STATUS_ID_NCP_1 = 59,
MSM_RPM_9615_STATUS_ID_CXO_BUFFERS = 60,
MSM_RPM_9615_STATUS_ID_USB_OTG_SWITCH = 61,
MSM_RPM_9615_STATUS_ID_HDMI_SWITCH = 62,
MSM_RPM_STATUS_ID_LAST = MSM_RPM_STATUS_ID_HDMI_SWITCH,
MSM_RPM_9615_STATUS_ID_LAST = MSM_RPM_9615_STATUS_ID_HDMI_SWITCH,
};
#endif /* __ARCH_ARM_MACH_MSM_RPM_9615_H */

833
arch/arm/mach-msm/include/mach/rpm.h
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -18,14 +18,13 @@
#include <linux/list.h>
#include <linux/semaphore.h>
#if defined(CONFIG_ARCH_MSM8X60)
#include <mach/rpm-8660.h>
#elif defined(CONFIG_ARCH_MSM9615)
#include <mach/rpm-9615.h>
#elif defined(CONFIG_ARCH_MSM8960)
#include <mach/rpm-8960.h>
#endif
#include <mach/rpm-8930.h>
#include <mach/rpm-8064.h>
#define SEL_MASK_SIZE (5)
enum {
MSM_RPM_PAGE_STATUS,
@@ -44,13 +43,794 @@ enum {
MSM_RPM_CTX_REJECTED = 31,
};
/* RPM control message RAM enums */
enum {
MSM_RPM_CTRL_VERSION_MAJOR,
MSM_RPM_CTRL_VERSION_MINOR,
MSM_RPM_CTRL_VERSION_BUILD,
MSM_RPM_CTRL_REQ_CTX_0,
MSM_RPM_CTRL_REQ_SEL_0,
MSM_RPM_CTRL_ACK_CTX_0,
MSM_RPM_CTRL_ACK_SEL_0,
MSM_RPM_CTRL_LAST,
};
enum {
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 = 0,
MSM_RPM_ID_NOTIFICATION_CONFIGURED_7 =
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + 7,
MSM_RPM_ID_NOTIFICATION_REGISTERED_0,
MSM_RPM_ID_NOTIFICATION_REGISTERED_7 =
MSM_RPM_ID_NOTIFICATION_REGISTERED_0 + 7,
MSM_RPM_ID_INVALIDATE_0,
MSM_RPM_ID_INVALIDATE_7 =
MSM_RPM_ID_INVALIDATE_0 + 7,
MSM_RPM_ID_TRIGGER_TIMED_TO,
MSM_RPM_ID_TRIGGER_TIMED_0,
MSM_RPM_ID_TRIGGER_TIMED_SCLK_COUNT,
MSM_RPM_ID_RPM_CTL,
/* TRIGGER_CLEAR/SET deprecated in these 24 RESERVED bytes */
MSM_RPM_ID_RESERVED_0,
MSM_RPM_ID_RESERVED_5 =
MSM_RPM_ID_RESERVED_0 + 5,
MSM_RPM_ID_CXO_CLK,
MSM_RPM_ID_PXO_CLK,
MSM_RPM_ID_APPS_FABRIC_CLK,
MSM_RPM_ID_SYSTEM_FABRIC_CLK,
MSM_RPM_ID_MM_FABRIC_CLK,
MSM_RPM_ID_DAYTONA_FABRIC_CLK,
MSM_RPM_ID_SFPB_CLK,
MSM_RPM_ID_CFPB_CLK,
MSM_RPM_ID_MMFPB_CLK,
MSM_RPM_ID_EBI1_CLK,
MSM_RPM_ID_APPS_FABRIC_CFG_HALT_0,
MSM_RPM_ID_APPS_FABRIC_HALT_0 =
MSM_RPM_ID_APPS_FABRIC_CFG_HALT_0,
MSM_RPM_ID_APPS_FABRIC_CFG_HALT_1,
MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_0,
MSM_RPM_ID_APPS_FABRIC_CLOCK_MODE_0 =
MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_0,
MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_1,
MSM_RPM_ID_APPS_FABRIC_CFG_CLKMOD_2,
MSM_RPM_ID_APPS_FABRIC_CFG_IOCTL,
MSM_RPM_ID_APPS_FABRIC_ARB_0,
MSM_RPM_ID_APPS_FABRIC_ARB_11 =
MSM_RPM_ID_APPS_FABRIC_ARB_0 + 11,
MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0,
MSM_RPM_ID_SYSTEM_FABRIC_HALT_0 =
MSM_RPM_ID_SYS_FABRIC_CFG_HALT_0,
MSM_RPM_ID_SYS_FABRIC_CFG_HALT_1,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0,
MSM_RPM_ID_SYSTEM_FABRIC_CLOCK_MODE_0 =
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_0,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_1,
MSM_RPM_ID_SYS_FABRIC_CFG_CLKMOD_2,
MSM_RPM_ID_SYS_FABRIC_CFG_IOCTL,
MSM_RPM_ID_SYSTEM_FABRIC_ARB_0,
MSM_RPM_ID_SYSTEM_FABRIC_ARB_28 =
MSM_RPM_ID_SYSTEM_FABRIC_ARB_0 + 28,
MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_0,
MSM_RPM_ID_MM_FABRIC_HALT_0 =
MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_0,
MSM_RPM_ID_MMSS_FABRIC_CFG_HALT_1,
MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_0,
MSM_RPM_ID_MM_FABRIC_CLOCK_MODE_0 =
MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_0,
MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_1,
MSM_RPM_ID_MMSS_FABRIC_CFG_CLKMOD_2,
MSM_RPM_ID_MMSS_FABRIC_CFG_IOCTL,
MSM_RPM_ID_MM_FABRIC_ARB_0,
MSM_RPM_ID_MM_FABRIC_ARB_22 =
MSM_RPM_ID_MM_FABRIC_ARB_0 + 22,
MSM_RPM_ID_PM8921_S1_0,
MSM_RPM_ID_PM8921_S1_1,
MSM_RPM_ID_PM8921_S2_0,
MSM_RPM_ID_PM8921_S2_1,
MSM_RPM_ID_PM8921_S3_0,
MSM_RPM_ID_PM8921_S3_1,
MSM_RPM_ID_PM8921_S4_0,
MSM_RPM_ID_PM8921_S4_1,
MSM_RPM_ID_PM8921_S5_0,
MSM_RPM_ID_PM8921_S5_1,
MSM_RPM_ID_PM8921_S6_0,
MSM_RPM_ID_PM8921_S6_1,
MSM_RPM_ID_PM8921_S7_0,
MSM_RPM_ID_PM8921_S7_1,
MSM_RPM_ID_PM8921_S8_0,
MSM_RPM_ID_PM8921_S8_1,
MSM_RPM_ID_PM8921_L1_0,
MSM_RPM_ID_PM8921_L1_1,
MSM_RPM_ID_PM8921_L2_0,
MSM_RPM_ID_PM8921_L2_1,
MSM_RPM_ID_PM8921_L3_0,
MSM_RPM_ID_PM8921_L3_1,
MSM_RPM_ID_PM8921_L4_0,
MSM_RPM_ID_PM8921_L4_1,
MSM_RPM_ID_PM8921_L5_0,
MSM_RPM_ID_PM8921_L5_1,
MSM_RPM_ID_PM8921_L6_0,
MSM_RPM_ID_PM8921_L6_1,
MSM_RPM_ID_PM8921_L7_0,
MSM_RPM_ID_PM8921_L7_1,
MSM_RPM_ID_PM8921_L8_0,
MSM_RPM_ID_PM8921_L8_1,
MSM_RPM_ID_PM8921_L9_0,
MSM_RPM_ID_PM8921_L9_1,
MSM_RPM_ID_PM8921_L10_0,
MSM_RPM_ID_PM8921_L10_1,
MSM_RPM_ID_PM8921_L11_0,
MSM_RPM_ID_PM8921_L11_1,
MSM_RPM_ID_PM8921_L12_0,
MSM_RPM_ID_PM8921_L12_1,
MSM_RPM_ID_PM8921_L13_0,
MSM_RPM_ID_PM8921_L13_1,
MSM_RPM_ID_PM8921_L14_0,
MSM_RPM_ID_PM8921_L14_1,
MSM_RPM_ID_PM8921_L15_0,
MSM_RPM_ID_PM8921_L15_1,
MSM_RPM_ID_PM8921_L16_0,
MSM_RPM_ID_PM8921_L16_1,
MSM_RPM_ID_PM8921_L17_0,
MSM_RPM_ID_PM8921_L17_1,
MSM_RPM_ID_PM8921_L18_0,
MSM_RPM_ID_PM8921_L18_1,
MSM_RPM_ID_PM8921_L19_0,
MSM_RPM_ID_PM8921_L19_1,
MSM_RPM_ID_PM8921_L20_0,
MSM_RPM_ID_PM8921_L20_1,
MSM_RPM_ID_PM8921_L21_0,
MSM_RPM_ID_PM8921_L21_1,
MSM_RPM_ID_PM8921_L22_0,
MSM_RPM_ID_PM8921_L22_1,
MSM_RPM_ID_PM8921_L23_0,
MSM_RPM_ID_PM8921_L23_1,
MSM_RPM_ID_PM8921_L24_0,
MSM_RPM_ID_PM8921_L24_1,
MSM_RPM_ID_PM8921_L25_0,
MSM_RPM_ID_PM8921_L25_1,
MSM_RPM_ID_PM8921_L26_0,
MSM_RPM_ID_PM8921_L26_1,
MSM_RPM_ID_PM8921_L27_0,
MSM_RPM_ID_PM8921_L27_1,
MSM_RPM_ID_PM8921_L28_0,
MSM_RPM_ID_PM8921_L28_1,
MSM_RPM_ID_PM8921_L29_0,
MSM_RPM_ID_PM8921_L29_1,
MSM_RPM_ID_PM8921_CLK1_0,
MSM_RPM_ID_PM8921_CLK1_1,
MSM_RPM_ID_PM8921_CLK2_0,
MSM_RPM_ID_PM8921_CLK2_1,
MSM_RPM_ID_PM8921_LVS1,
MSM_RPM_ID_PM8921_LVS2,
MSM_RPM_ID_PM8921_LVS3,
MSM_RPM_ID_PM8921_LVS4,
MSM_RPM_ID_PM8921_LVS5,
MSM_RPM_ID_PM8921_LVS6,
MSM_RPM_ID_PM8921_LVS7,
MSM_RPM_ID_NCP_0,
MSM_RPM_ID_NCP_1,
MSM_RPM_ID_CXO_BUFFERS,
MSM_RPM_ID_USB_OTG_SWITCH,
MSM_RPM_ID_HDMI_SWITCH,
MSM_RPM_ID_DDR_DMM_0,
MSM_RPM_ID_DDR_DMM_1,
MSM_RPM_ID_QDSS_CLK,
/* 8660 specific ids */
MSM_RPM_ID_TRIGGER_SET_FROM,
MSM_RPM_ID_TRIGGER_SET_TO,
MSM_RPM_ID_TRIGGER_SET_TRIGGER,
MSM_RPM_ID_TRIGGER_CLEAR_FROM,
MSM_RPM_ID_TRIGGER_CLEAR_TO,
MSM_RPM_ID_TRIGGER_CLEAR_TRIGGER,
MSM_RPM_ID_PLL_4,
MSM_RPM_ID_SMI_CLK,
MSM_RPM_ID_APPS_L2_CACHE_CTL,
/* pmic 8901 */
MSM_RPM_ID_SMPS0B_0,
MSM_RPM_ID_SMPS0B_1,
MSM_RPM_ID_SMPS1B_0,
MSM_RPM_ID_SMPS1B_1,
MSM_RPM_ID_SMPS2B_0,
MSM_RPM_ID_SMPS2B_1,
MSM_RPM_ID_SMPS3B_0,
MSM_RPM_ID_SMPS3B_1,
MSM_RPM_ID_SMPS4B_0,
MSM_RPM_ID_SMPS4B_1,
MSM_RPM_ID_LDO0B_0,
MSM_RPM_ID_LDO0B_1,
MSM_RPM_ID_LDO1B_0,
MSM_RPM_ID_LDO1B_1,
MSM_RPM_ID_LDO2B_0,
MSM_RPM_ID_LDO2B_1,
MSM_RPM_ID_LDO3B_0,
MSM_RPM_ID_LDO3B_1,
MSM_RPM_ID_LDO4B_0,
MSM_RPM_ID_LDO4B_1,
MSM_RPM_ID_LDO5B_0,
MSM_RPM_ID_LDO5B_1,
MSM_RPM_ID_LDO6B_0,
MSM_RPM_ID_LDO6B_1,
MSM_RPM_ID_LVS0B,
MSM_RPM_ID_LVS1B,
MSM_RPM_ID_LVS2B,
MSM_RPM_ID_LVS3B,
MSM_RPM_ID_MVS,
/* pmic 8058 */
MSM_RPM_ID_SMPS0_0,
MSM_RPM_ID_SMPS0_1,
MSM_RPM_ID_SMPS1_0,
MSM_RPM_ID_SMPS1_1,
MSM_RPM_ID_SMPS2_0,
MSM_RPM_ID_SMPS2_1,
MSM_RPM_ID_SMPS3_0,
MSM_RPM_ID_SMPS3_1,
MSM_RPM_ID_SMPS4_0,
MSM_RPM_ID_SMPS4_1,
MSM_RPM_ID_LDO0_0,
MSM_RPM_ID_LDO0_1,
MSM_RPM_ID_LDO1_0,
MSM_RPM_ID_LDO1_1,
MSM_RPM_ID_LDO2_0,
MSM_RPM_ID_LDO2_1,
MSM_RPM_ID_LDO3_0,
MSM_RPM_ID_LDO3_1,
MSM_RPM_ID_LDO4_0,
MSM_RPM_ID_LDO4_1,
MSM_RPM_ID_LDO5_0,
MSM_RPM_ID_LDO5_1,
MSM_RPM_ID_LDO6_0,
MSM_RPM_ID_LDO6_1,
MSM_RPM_ID_LDO7_0,
MSM_RPM_ID_LDO7_1,
MSM_RPM_ID_LDO8_0,
MSM_RPM_ID_LDO8_1,
MSM_RPM_ID_LDO9_0,
MSM_RPM_ID_LDO9_1,
MSM_RPM_ID_LDO10_0,
MSM_RPM_ID_LDO10_1,
MSM_RPM_ID_LDO11_0,
MSM_RPM_ID_LDO11_1,
MSM_RPM_ID_LDO12_0,
MSM_RPM_ID_LDO12_1,
MSM_RPM_ID_LDO13_0,
MSM_RPM_ID_LDO13_1,
MSM_RPM_ID_LDO14_0,
MSM_RPM_ID_LDO14_1,
MSM_RPM_ID_LDO15_0,
MSM_RPM_ID_LDO15_1,
MSM_RPM_ID_LDO16_0,
MSM_RPM_ID_LDO16_1,
MSM_RPM_ID_LDO17_0,
MSM_RPM_ID_LDO17_1,
MSM_RPM_ID_LDO18_0,
MSM_RPM_ID_LDO18_1,
MSM_RPM_ID_LDO19_0,
MSM_RPM_ID_LDO19_1,
MSM_RPM_ID_LDO20_0,
MSM_RPM_ID_LDO20_1,
MSM_RPM_ID_LDO21_0,
MSM_RPM_ID_LDO21_1,
MSM_RPM_ID_LDO22_0,
MSM_RPM_ID_LDO22_1,
MSM_RPM_ID_LDO23_0,
MSM_RPM_ID_LDO23_1,
MSM_RPM_ID_LDO24_0,
MSM_RPM_ID_LDO24_1,
MSM_RPM_ID_LDO25_0,
MSM_RPM_ID_LDO25_1,
MSM_RPM_ID_LVS0,
MSM_RPM_ID_LVS1,
/* 9615 specific */
MSM_RPM_ID_PM8018_S1_0,
MSM_RPM_ID_PM8018_S1_1,
MSM_RPM_ID_PM8018_S2_0,
MSM_RPM_ID_PM8018_S2_1,
MSM_RPM_ID_PM8018_S3_0,
MSM_RPM_ID_PM8018_S3_1,
MSM_RPM_ID_PM8018_S4_0,
MSM_RPM_ID_PM8018_S4_1,
MSM_RPM_ID_PM8018_S5_0,
MSM_RPM_ID_PM8018_S5_1,
MSM_RPM_ID_PM8018_L1_0,
MSM_RPM_ID_PM8018_L1_1,
MSM_RPM_ID_PM8018_L2_0,
MSM_RPM_ID_PM8018_L2_1,
MSM_RPM_ID_PM8018_L3_0,
MSM_RPM_ID_PM8018_L3_1,
MSM_RPM_ID_PM8018_L4_0,
MSM_RPM_ID_PM8018_L4_1,
MSM_RPM_ID_PM8018_L5_0,
MSM_RPM_ID_PM8018_L5_1,
MSM_RPM_ID_PM8018_L6_0,
MSM_RPM_ID_PM8018_L6_1,
MSM_RPM_ID_PM8018_L7_0,
MSM_RPM_ID_PM8018_L7_1,
MSM_RPM_ID_PM8018_L8_0,
MSM_RPM_ID_PM8018_L8_1,
MSM_RPM_ID_PM8018_L9_0,
MSM_RPM_ID_PM8018_L9_1,
MSM_RPM_ID_PM8018_L10_0,
MSM_RPM_ID_PM8018_L10_1,
MSM_RPM_ID_PM8018_L11_0,
MSM_RPM_ID_PM8018_L11_1,
MSM_RPM_ID_PM8018_L12_0,
MSM_RPM_ID_PM8018_L12_1,
MSM_RPM_ID_PM8018_L13_0,
MSM_RPM_ID_PM8018_L13_1,
MSM_RPM_ID_PM8018_L14_0,
MSM_RPM_ID_PM8018_L14_1,
MSM_RPM_ID_PM8018_LVS1,
/* 8930 specific */
MSM_RPM_ID_PM8038_S1_0,
MSM_RPM_ID_PM8038_S1_1,
MSM_RPM_ID_PM8038_S2_0,
MSM_RPM_ID_PM8038_S2_1,
MSM_RPM_ID_PM8038_S3_0,
MSM_RPM_ID_PM8038_S3_1,
MSM_RPM_ID_PM8038_S4_0,
MSM_RPM_ID_PM8038_S4_1,
MSM_RPM_ID_PM8038_S5_0,
MSM_RPM_ID_PM8038_S5_1,
MSM_RPM_ID_PM8038_S6_0,
MSM_RPM_ID_PM8038_S6_1,
MSM_RPM_ID_PM8038_L1_0,
MSM_RPM_ID_PM8038_L1_1,
MSM_RPM_ID_PM8038_L2_0,
MSM_RPM_ID_PM8038_L2_1,
MSM_RPM_ID_PM8038_L3_0,
MSM_RPM_ID_PM8038_L3_1,
MSM_RPM_ID_PM8038_L4_0,
MSM_RPM_ID_PM8038_L4_1,
MSM_RPM_ID_PM8038_L5_0,
MSM_RPM_ID_PM8038_L5_1,
MSM_RPM_ID_PM8038_L6_0,
MSM_RPM_ID_PM8038_L6_1,
MSM_RPM_ID_PM8038_L7_0,
MSM_RPM_ID_PM8038_L7_1,
MSM_RPM_ID_PM8038_L8_0,
MSM_RPM_ID_PM8038_L8_1,
MSM_RPM_ID_PM8038_L9_0,
MSM_RPM_ID_PM8038_L9_1,
MSM_RPM_ID_PM8038_L10_0,
MSM_RPM_ID_PM8038_L10_1,
MSM_RPM_ID_PM8038_L11_0,
MSM_RPM_ID_PM8038_L11_1,
MSM_RPM_ID_PM8038_L12_0,
MSM_RPM_ID_PM8038_L12_1,
MSM_RPM_ID_PM8038_L13_0,
MSM_RPM_ID_PM8038_L13_1,
MSM_RPM_ID_PM8038_L14_0,
MSM_RPM_ID_PM8038_L14_1,
MSM_RPM_ID_PM8038_L15_0,
MSM_RPM_ID_PM8038_L15_1,
MSM_RPM_ID_PM8038_L16_0,
MSM_RPM_ID_PM8038_L16_1,
MSM_RPM_ID_PM8038_L17_0,
MSM_RPM_ID_PM8038_L17_1,
MSM_RPM_ID_PM8038_L18_0,
MSM_RPM_ID_PM8038_L18_1,
MSM_RPM_ID_PM8038_L19_0,
MSM_RPM_ID_PM8038_L19_1,
MSM_RPM_ID_PM8038_L20_0,
MSM_RPM_ID_PM8038_L20_1,
MSM_RPM_ID_PM8038_L21_0,
MSM_RPM_ID_PM8038_L21_1,
MSM_RPM_ID_PM8038_L22_0,
MSM_RPM_ID_PM8038_L22_1,
MSM_RPM_ID_PM8038_L23_0,
MSM_RPM_ID_PM8038_L23_1,
MSM_RPM_ID_PM8038_L24_0,
MSM_RPM_ID_PM8038_L24_1,
MSM_RPM_ID_PM8038_L25_0,
MSM_RPM_ID_PM8038_L25_1,
MSM_RPM_ID_PM8038_L26_0,
MSM_RPM_ID_PM8038_L26_1,
MSM_RPM_ID_PM8038_L27_0,
MSM_RPM_ID_PM8038_L27_1,
MSM_RPM_ID_PM8038_CLK1_0,
MSM_RPM_ID_PM8038_CLK1_1,
MSM_RPM_ID_PM8038_CLK2_0,
MSM_RPM_ID_PM8038_CLK2_1,
MSM_RPM_ID_PM8038_LVS1,
MSM_RPM_ID_PM8038_LVS2,
/* 8064 specific */
MSM_RPM_ID_PM8821_S1_0,
MSM_RPM_ID_PM8821_S1_1,
MSM_RPM_ID_PM8821_S2_0,
MSM_RPM_ID_PM8821_S2_1,
MSM_RPM_ID_PM8821_L1_0,
MSM_RPM_ID_PM8821_L1_1,
MSM_RPM_ID_LAST,
};
enum {
MSM_RPM_STATUS_ID_VERSION_MAJOR,
MSM_RPM_STATUS_ID_VERSION_MINOR,
MSM_RPM_STATUS_ID_VERSION_BUILD,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_0,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_1,
MSM_RPM_STATUS_ID_SUPPORTED_RESOURCES_2,
MSM_RPM_STATUS_ID_RESERVED_SUPPORTED_RESOURCES_0,
MSM_RPM_STATUS_ID_SEQUENCE,
MSM_RPM_STATUS_ID_RPM_CTL,
MSM_RPM_STATUS_ID_CXO_CLK,
MSM_RPM_STATUS_ID_PXO_CLK,
MSM_RPM_STATUS_ID_APPS_FABRIC_CLK,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLK,
MSM_RPM_STATUS_ID_MM_FABRIC_CLK,
MSM_RPM_STATUS_ID_DAYTONA_FABRIC_CLK,
MSM_RPM_STATUS_ID_SFPB_CLK,
MSM_RPM_STATUS_ID_CFPB_CLK,
MSM_RPM_STATUS_ID_MMFPB_CLK,
MSM_RPM_STATUS_ID_EBI1_CLK,
MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_HALT,
MSM_RPM_STATUS_ID_APPS_FABRIC_HALT =
MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_HALT,
MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_CLKMOD,
MSM_RPM_STATUS_ID_APPS_FABRIC_CLOCK_MODE =
MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_CLKMOD,
MSM_RPM_STATUS_ID_APPS_FABRIC_CFG_IOCTL,
MSM_RPM_STATUS_ID_APPS_FABRIC_ARB,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_HALT =
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_HALT,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_CLOCK_MODE =
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_CLKMOD,
MSM_RPM_STATUS_ID_SYS_FABRIC_CFG_IOCTL,
MSM_RPM_STATUS_ID_SYSTEM_FABRIC_ARB,
MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_HALT,
MSM_RPM_STATUS_ID_MM_FABRIC_HALT =
MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_HALT,
MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD,
MSM_RPM_STATUS_ID_MM_FABRIC_CLOCK_MODE =
MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_CLKMOD,
MSM_RPM_STATUS_ID_MMSS_FABRIC_CFG_IOCTL,
MSM_RPM_STATUS_ID_MM_FABRIC_ARB,
MSM_RPM_STATUS_ID_PM8921_S1_0,
MSM_RPM_STATUS_ID_PM8921_S1_1,
MSM_RPM_STATUS_ID_PM8921_S2_0,
MSM_RPM_STATUS_ID_PM8921_S2_1,
MSM_RPM_STATUS_ID_PM8921_S3_0,
MSM_RPM_STATUS_ID_PM8921_S3_1,
MSM_RPM_STATUS_ID_PM8921_S4_0,
MSM_RPM_STATUS_ID_PM8921_S4_1,
MSM_RPM_STATUS_ID_PM8921_S5_0,
MSM_RPM_STATUS_ID_PM8921_S5_1,
MSM_RPM_STATUS_ID_PM8921_S6_0,
MSM_RPM_STATUS_ID_PM8921_S6_1,
MSM_RPM_STATUS_ID_PM8921_S7_0,
MSM_RPM_STATUS_ID_PM8921_S7_1,
MSM_RPM_STATUS_ID_PM8921_S8_0,
MSM_RPM_STATUS_ID_PM8921_S8_1,
MSM_RPM_STATUS_ID_PM8921_L1_0,
MSM_RPM_STATUS_ID_PM8921_L1_1,
MSM_RPM_STATUS_ID_PM8921_L2_0,
MSM_RPM_STATUS_ID_PM8921_L2_1,
MSM_RPM_STATUS_ID_PM8921_L3_0,
MSM_RPM_STATUS_ID_PM8921_L3_1,
MSM_RPM_STATUS_ID_PM8921_L4_0,
MSM_RPM_STATUS_ID_PM8921_L4_1,
MSM_RPM_STATUS_ID_PM8921_L5_0,
MSM_RPM_STATUS_ID_PM8921_L5_1,
MSM_RPM_STATUS_ID_PM8921_L6_0,
MSM_RPM_STATUS_ID_PM8921_L6_1,
MSM_RPM_STATUS_ID_PM8921_L7_0,
MSM_RPM_STATUS_ID_PM8921_L7_1,
MSM_RPM_STATUS_ID_PM8921_L8_0,
MSM_RPM_STATUS_ID_PM8921_L8_1,
MSM_RPM_STATUS_ID_PM8921_L9_0,
MSM_RPM_STATUS_ID_PM8921_L9_1,
MSM_RPM_STATUS_ID_PM8921_L10_0,
MSM_RPM_STATUS_ID_PM8921_L10_1,
MSM_RPM_STATUS_ID_PM8921_L11_0,
MSM_RPM_STATUS_ID_PM8921_L11_1,
MSM_RPM_STATUS_ID_PM8921_L12_0,
MSM_RPM_STATUS_ID_PM8921_L12_1,
MSM_RPM_STATUS_ID_PM8921_L13_0,
MSM_RPM_STATUS_ID_PM8921_L13_1,
MSM_RPM_STATUS_ID_PM8921_L14_0,
MSM_RPM_STATUS_ID_PM8921_L14_1,
MSM_RPM_STATUS_ID_PM8921_L15_0,
MSM_RPM_STATUS_ID_PM8921_L15_1,
MSM_RPM_STATUS_ID_PM8921_L16_0,
MSM_RPM_STATUS_ID_PM8921_L16_1,
MSM_RPM_STATUS_ID_PM8921_L17_0,
MSM_RPM_STATUS_ID_PM8921_L17_1,
MSM_RPM_STATUS_ID_PM8921_L18_0,
MSM_RPM_STATUS_ID_PM8921_L18_1,
MSM_RPM_STATUS_ID_PM8921_L19_0,
MSM_RPM_STATUS_ID_PM8921_L19_1,
MSM_RPM_STATUS_ID_PM8921_L20_0,
MSM_RPM_STATUS_ID_PM8921_L20_1,
MSM_RPM_STATUS_ID_PM8921_L21_0,
MSM_RPM_STATUS_ID_PM8921_L21_1,
MSM_RPM_STATUS_ID_PM8921_L22_0,
MSM_RPM_STATUS_ID_PM8921_L22_1,
MSM_RPM_STATUS_ID_PM8921_L23_0,
MSM_RPM_STATUS_ID_PM8921_L23_1,
MSM_RPM_STATUS_ID_PM8921_L24_0,
MSM_RPM_STATUS_ID_PM8921_L24_1,
MSM_RPM_STATUS_ID_PM8921_L25_0,
MSM_RPM_STATUS_ID_PM8921_L25_1,
MSM_RPM_STATUS_ID_PM8921_L26_0,
MSM_RPM_STATUS_ID_PM8921_L26_1,
MSM_RPM_STATUS_ID_PM8921_L27_0,
MSM_RPM_STATUS_ID_PM8921_L27_1,
MSM_RPM_STATUS_ID_PM8921_L28_0,
MSM_RPM_STATUS_ID_PM8921_L28_1,
MSM_RPM_STATUS_ID_PM8921_L29_0,
MSM_RPM_STATUS_ID_PM8921_L29_1,
MSM_RPM_STATUS_ID_PM8921_CLK1_0,
MSM_RPM_STATUS_ID_PM8921_CLK1_1,
MSM_RPM_STATUS_ID_PM8921_CLK2_0,
MSM_RPM_STATUS_ID_PM8921_CLK2_1,
MSM_RPM_STATUS_ID_PM8921_LVS1,
MSM_RPM_STATUS_ID_PM8921_LVS2,
MSM_RPM_STATUS_ID_PM8921_LVS3,
MSM_RPM_STATUS_ID_PM8921_LVS4,
MSM_RPM_STATUS_ID_PM8921_LVS5,
MSM_RPM_STATUS_ID_PM8921_LVS6,
MSM_RPM_STATUS_ID_PM8921_LVS7,
MSM_RPM_STATUS_ID_NCP_0,
MSM_RPM_STATUS_ID_NCP_1,
MSM_RPM_STATUS_ID_CXO_BUFFERS,
MSM_RPM_STATUS_ID_USB_OTG_SWITCH,
MSM_RPM_STATUS_ID_HDMI_SWITCH,
MSM_RPM_STATUS_ID_DDR_DMM_0,
MSM_RPM_STATUS_ID_DDR_DMM_1,
MSM_RPM_STATUS_ID_EBI1_CH0_RANGE,
MSM_RPM_STATUS_ID_EBI1_CH1_RANGE,
/* 8660 Specific */
MSM_RPM_STATUS_ID_PLL_4,
MSM_RPM_STATUS_ID_SMI_CLK,
MSM_RPM_STATUS_ID_APPS_L2_CACHE_CTL,
MSM_RPM_STATUS_ID_SMPS0B_0,
MSM_RPM_STATUS_ID_SMPS0B_1,
MSM_RPM_STATUS_ID_SMPS1B_0,
MSM_RPM_STATUS_ID_SMPS1B_1,
MSM_RPM_STATUS_ID_SMPS2B_0,
MSM_RPM_STATUS_ID_SMPS2B_1,
MSM_RPM_STATUS_ID_SMPS3B_0,
MSM_RPM_STATUS_ID_SMPS3B_1,
MSM_RPM_STATUS_ID_SMPS4B_0,
MSM_RPM_STATUS_ID_SMPS4B_1,
MSM_RPM_STATUS_ID_LDO0B_0,
MSM_RPM_STATUS_ID_LDO0B_1,
MSM_RPM_STATUS_ID_LDO1B_0,
MSM_RPM_STATUS_ID_LDO1B_1,
MSM_RPM_STATUS_ID_LDO2B_0,
MSM_RPM_STATUS_ID_LDO2B_1,
MSM_RPM_STATUS_ID_LDO3B_0,
MSM_RPM_STATUS_ID_LDO3B_1,
MSM_RPM_STATUS_ID_LDO4B_0,
MSM_RPM_STATUS_ID_LDO4B_1,
MSM_RPM_STATUS_ID_LDO5B_0,
MSM_RPM_STATUS_ID_LDO5B_1,
MSM_RPM_STATUS_ID_LDO6B_0,
MSM_RPM_STATUS_ID_LDO6B_1,
MSM_RPM_STATUS_ID_LVS0B,
MSM_RPM_STATUS_ID_LVS1B,
MSM_RPM_STATUS_ID_LVS2B,
MSM_RPM_STATUS_ID_LVS3B,
MSM_RPM_STATUS_ID_MVS,
MSM_RPM_STATUS_ID_SMPS0_0,
MSM_RPM_STATUS_ID_SMPS0_1,
MSM_RPM_STATUS_ID_SMPS1_0,
MSM_RPM_STATUS_ID_SMPS1_1,
MSM_RPM_STATUS_ID_SMPS2_0,
MSM_RPM_STATUS_ID_SMPS2_1,
MSM_RPM_STATUS_ID_SMPS3_0,
MSM_RPM_STATUS_ID_SMPS3_1,
MSM_RPM_STATUS_ID_SMPS4_0,
MSM_RPM_STATUS_ID_SMPS4_1,
MSM_RPM_STATUS_ID_LDO0_0,
MSM_RPM_STATUS_ID_LDO0_1,
MSM_RPM_STATUS_ID_LDO1_0,
MSM_RPM_STATUS_ID_LDO1_1,
MSM_RPM_STATUS_ID_LDO2_0,
MSM_RPM_STATUS_ID_LDO2_1,
MSM_RPM_STATUS_ID_LDO3_0,
MSM_RPM_STATUS_ID_LDO3_1,
MSM_RPM_STATUS_ID_LDO4_0,
MSM_RPM_STATUS_ID_LDO4_1,
MSM_RPM_STATUS_ID_LDO5_0,
MSM_RPM_STATUS_ID_LDO5_1,
MSM_RPM_STATUS_ID_LDO6_0,
MSM_RPM_STATUS_ID_LDO6_1,
MSM_RPM_STATUS_ID_LDO7_0,
MSM_RPM_STATUS_ID_LDO7_1,
MSM_RPM_STATUS_ID_LDO8_0,
MSM_RPM_STATUS_ID_LDO8_1,
MSM_RPM_STATUS_ID_LDO9_0,
MSM_RPM_STATUS_ID_LDO9_1,
MSM_RPM_STATUS_ID_LDO10_0,
MSM_RPM_STATUS_ID_LDO10_1,
MSM_RPM_STATUS_ID_LDO11_0,
MSM_RPM_STATUS_ID_LDO11_1,
MSM_RPM_STATUS_ID_LDO12_0,
MSM_RPM_STATUS_ID_LDO12_1,
MSM_RPM_STATUS_ID_LDO13_0,
MSM_RPM_STATUS_ID_LDO13_1,
MSM_RPM_STATUS_ID_LDO14_0,
MSM_RPM_STATUS_ID_LDO14_1,
MSM_RPM_STATUS_ID_LDO15_0,
MSM_RPM_STATUS_ID_LDO15_1,
MSM_RPM_STATUS_ID_LDO16_0,
MSM_RPM_STATUS_ID_LDO16_1,
MSM_RPM_STATUS_ID_LDO17_0,
MSM_RPM_STATUS_ID_LDO17_1,
MSM_RPM_STATUS_ID_LDO18_0,
MSM_RPM_STATUS_ID_LDO18_1,
MSM_RPM_STATUS_ID_LDO19_0,
MSM_RPM_STATUS_ID_LDO19_1,
MSM_RPM_STATUS_ID_LDO20_0,
MSM_RPM_STATUS_ID_LDO20_1,
MSM_RPM_STATUS_ID_LDO21_0,
MSM_RPM_STATUS_ID_LDO21_1,
MSM_RPM_STATUS_ID_LDO22_0,
MSM_RPM_STATUS_ID_LDO22_1,
MSM_RPM_STATUS_ID_LDO23_0,
MSM_RPM_STATUS_ID_LDO23_1,
MSM_RPM_STATUS_ID_LDO24_0,
MSM_RPM_STATUS_ID_LDO24_1,
MSM_RPM_STATUS_ID_LDO25_0,
MSM_RPM_STATUS_ID_LDO25_1,
MSM_RPM_STATUS_ID_LVS0,
MSM_RPM_STATUS_ID_LVS1,
/* 9615 Specific */
MSM_RPM_STATUS_ID_PM8018_S1_0,
MSM_RPM_STATUS_ID_PM8018_S1_1,
MSM_RPM_STATUS_ID_PM8018_S2_0,
MSM_RPM_STATUS_ID_PM8018_S2_1,
MSM_RPM_STATUS_ID_PM8018_S3_0,
MSM_RPM_STATUS_ID_PM8018_S3_1,
MSM_RPM_STATUS_ID_PM8018_S4_0,
MSM_RPM_STATUS_ID_PM8018_S4_1,
MSM_RPM_STATUS_ID_PM8018_S5_0,
MSM_RPM_STATUS_ID_PM8018_S5_1,
MSM_RPM_STATUS_ID_PM8018_L1_0,
MSM_RPM_STATUS_ID_PM8018_L1_1,
MSM_RPM_STATUS_ID_PM8018_L2_0,
MSM_RPM_STATUS_ID_PM8018_L2_1,
MSM_RPM_STATUS_ID_PM8018_L3_0,
MSM_RPM_STATUS_ID_PM8018_L3_1,
MSM_RPM_STATUS_ID_PM8018_L4_0,
MSM_RPM_STATUS_ID_PM8018_L4_1,
MSM_RPM_STATUS_ID_PM8018_L5_0,
MSM_RPM_STATUS_ID_PM8018_L5_1,
MSM_RPM_STATUS_ID_PM8018_L6_0,
MSM_RPM_STATUS_ID_PM8018_L6_1,
MSM_RPM_STATUS_ID_PM8018_L7_0,
MSM_RPM_STATUS_ID_PM8018_L7_1,
MSM_RPM_STATUS_ID_PM8018_L8_0,
MSM_RPM_STATUS_ID_PM8018_L8_1,
MSM_RPM_STATUS_ID_PM8018_L9_0,
MSM_RPM_STATUS_ID_PM8018_L9_1,
MSM_RPM_STATUS_ID_PM8018_L10_0,
MSM_RPM_STATUS_ID_PM8018_L10_1,
MSM_RPM_STATUS_ID_PM8018_L11_0,
MSM_RPM_STATUS_ID_PM8018_L11_1,
MSM_RPM_STATUS_ID_PM8018_L12_0,
MSM_RPM_STATUS_ID_PM8018_L12_1,
MSM_RPM_STATUS_ID_PM8018_L13_0,
MSM_RPM_STATUS_ID_PM8018_L13_1,
MSM_RPM_STATUS_ID_PM8018_L14_0,
MSM_RPM_STATUS_ID_PM8018_L14_1,
MSM_RPM_STATUS_ID_PM8018_LVS1,
/* 8930 specific */
MSM_RPM_STATUS_ID_PM8038_S1_0,
MSM_RPM_STATUS_ID_PM8038_S1_1,
MSM_RPM_STATUS_ID_PM8038_S2_0,
MSM_RPM_STATUS_ID_PM8038_S2_1,
MSM_RPM_STATUS_ID_PM8038_S3_0,
MSM_RPM_STATUS_ID_PM8038_S3_1,
MSM_RPM_STATUS_ID_PM8038_S4_0,
MSM_RPM_STATUS_ID_PM8038_S4_1,
MSM_RPM_STATUS_ID_PM8038_S5_0,
MSM_RPM_STATUS_ID_PM8038_S5_1,
MSM_RPM_STATUS_ID_PM8038_S6_0,
MSM_RPM_STATUS_ID_PM8038_S6_1,
MSM_RPM_STATUS_ID_PM8038_L1_0,
MSM_RPM_STATUS_ID_PM8038_L1_1,
MSM_RPM_STATUS_ID_PM8038_L2_0,
MSM_RPM_STATUS_ID_PM8038_L2_1,
MSM_RPM_STATUS_ID_PM8038_L3_0,
MSM_RPM_STATUS_ID_PM8038_L3_1,
MSM_RPM_STATUS_ID_PM8038_L4_0,
MSM_RPM_STATUS_ID_PM8038_L4_1,
MSM_RPM_STATUS_ID_PM8038_L5_0,
MSM_RPM_STATUS_ID_PM8038_L5_1,
MSM_RPM_STATUS_ID_PM8038_L6_0,
MSM_RPM_STATUS_ID_PM8038_L6_1,
MSM_RPM_STATUS_ID_PM8038_L7_0,
MSM_RPM_STATUS_ID_PM8038_L7_1,
MSM_RPM_STATUS_ID_PM8038_L8_0,
MSM_RPM_STATUS_ID_PM8038_L8_1,
MSM_RPM_STATUS_ID_PM8038_L9_0,
MSM_RPM_STATUS_ID_PM8038_L9_1,
MSM_RPM_STATUS_ID_PM8038_L10_0,
MSM_RPM_STATUS_ID_PM8038_L10_1,
MSM_RPM_STATUS_ID_PM8038_L11_0,
MSM_RPM_STATUS_ID_PM8038_L11_1,
MSM_RPM_STATUS_ID_PM8038_L12_0,
MSM_RPM_STATUS_ID_PM8038_L12_1,
MSM_RPM_STATUS_ID_PM8038_L13_0,
MSM_RPM_STATUS_ID_PM8038_L13_1,
MSM_RPM_STATUS_ID_PM8038_L14_0,
MSM_RPM_STATUS_ID_PM8038_L14_1,
MSM_RPM_STATUS_ID_PM8038_L15_0,
MSM_RPM_STATUS_ID_PM8038_L15_1,
MSM_RPM_STATUS_ID_PM8038_L16_0,
MSM_RPM_STATUS_ID_PM8038_L16_1,
MSM_RPM_STATUS_ID_PM8038_L17_0,
MSM_RPM_STATUS_ID_PM8038_L17_1,
MSM_RPM_STATUS_ID_PM8038_L18_0,
MSM_RPM_STATUS_ID_PM8038_L18_1,
MSM_RPM_STATUS_ID_PM8038_L19_0,
MSM_RPM_STATUS_ID_PM8038_L19_1,
MSM_RPM_STATUS_ID_PM8038_L20_0,
MSM_RPM_STATUS_ID_PM8038_L20_1,
MSM_RPM_STATUS_ID_PM8038_L21_0,
MSM_RPM_STATUS_ID_PM8038_L21_1,
MSM_RPM_STATUS_ID_PM8038_L22_0,
MSM_RPM_STATUS_ID_PM8038_L22_1,
MSM_RPM_STATUS_ID_PM8038_L23_0,
MSM_RPM_STATUS_ID_PM8038_L23_1,
MSM_RPM_STATUS_ID_PM8038_L24_0,
MSM_RPM_STATUS_ID_PM8038_L24_1,
MSM_RPM_STATUS_ID_PM8038_L25_0,
MSM_RPM_STATUS_ID_PM8038_L25_1,
MSM_RPM_STATUS_ID_PM8038_L26_0,
MSM_RPM_STATUS_ID_PM8038_L26_1,
MSM_RPM_STATUS_ID_PM8038_L27_0,
MSM_RPM_STATUS_ID_PM8038_L27_1,
MSM_RPM_STATUS_ID_PM8038_CLK1_0,
MSM_RPM_STATUS_ID_PM8038_CLK1_1,
MSM_RPM_STATUS_ID_PM8038_CLK2_0,
MSM_RPM_STATUS_ID_PM8038_CLK2_1,
MSM_RPM_STATUS_ID_PM8038_LVS1,
MSM_RPM_STATUS_ID_PM8038_LVS2,
/* 8064 specific */
MSM_RPM_STATUS_ID_PM8821_S1_0,
MSM_RPM_STATUS_ID_PM8821_S1_1,
MSM_RPM_STATUS_ID_PM8821_S2_0,
MSM_RPM_STATUS_ID_PM8821_S2_1,
MSM_RPM_STATUS_ID_PM8821_L1_0,
MSM_RPM_STATUS_ID_PM8821_L1_1,
MSM_RPM_STATUS_ID_LAST,
};
static inline uint32_t msm_rpm_get_ctx_mask(unsigned int ctx)
{
return 1UL << ctx;
}
#define MSM_RPM_SEL_MASK_SIZE (MSM_RPM_SEL_LAST / 32 + 1)
static inline unsigned int msm_rpm_get_sel_mask_reg(unsigned int sel)
{
return sel / 32;
@@ -69,7 +849,7 @@ struct msm_rpm_iv_pair {
struct msm_rpm_notification {
struct list_head list; /* reserved for RPM use */
struct semaphore sem;
uint32_t sel_masks[MSM_RPM_SEL_MASK_SIZE]; /* reserved for RPM use */
uint32_t sel_masks[SEL_MASK_SIZE]; /* reserved for RPM use */
};
struct msm_rpm_map_data {
@@ -78,22 +858,41 @@ struct msm_rpm_map_data {
uint32_t count;
};
#define MSM_RPM_MAP(i, s, c) { \
.id = MSM_RPM_ID_##i, .sel = MSM_RPM_SEL_##s, .count = c }
#define MSM_RPM_MAP(t, i, s, c) \
[MSM_RPM_ID_##i] = \
{\
.id = MSM_RPM_##t##_ID_##i, \
.sel = MSM_RPM_##t##_SEL_##s, \
.count = c, \
}
#define MSM_RPM_STATUS_ID_VALID BIT(31)
#define MSM_RPM_STATUS_ID_MAP(t, i) \
[MSM_RPM_STATUS_ID_## i] = (MSM_RPM_##t##_STATUS_ID_##i \
| MSM_RPM_STATUS_ID_VALID)
#define MSM_RPM_CTRL_MAP(t, i) \
[MSM_RPM_CTRL_##i] = MSM_RPM_##t##_CTRL_##i
struct msm_rpm_platform_data {
void __iomem *reg_base_addrs[MSM_RPM_PAGE_COUNT];
unsigned int irq_ack;
unsigned int irq_err;
unsigned int irq_vmpm;
void *msm_apps_ipc_rpm_reg;
unsigned int msm_apps_ipc_rpm_val;
void *ipc_rpm_reg;
unsigned int ipc_rpm_val;
struct msm_rpm_map_data target_id[MSM_RPM_ID_LAST];
unsigned int target_status[MSM_RPM_STATUS_ID_LAST];
unsigned int target_ctrl_id[MSM_RPM_CTRL_LAST];
unsigned int sel_invalidate, sel_notification, sel_last;
unsigned int ver[3];
};
extern struct msm_rpm_map_data rpm_map_data[];
extern unsigned int rpm_map_data_size;
extern struct msm_rpm_platform_data msm8660_rpm_data;
extern struct msm_rpm_platform_data msm8960_rpm_data;
extern struct msm_rpm_platform_data msm9615_rpm_data;
extern struct msm_rpm_platform_data msm8930_rpm_data;
extern struct msm_rpm_platform_data apq8064_rpm_data;
int msm_rpm_local_request_is_outstanding(void);
int msm_rpm_get_status(struct msm_rpm_iv_pair *status, int count);

31
arch/arm/mach-msm/mpm.c
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -20,8 +20,9 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <asm/hardware/gic.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <asm/hardware/gic.h>
#include <mach/msm_iomap.h>
#include <mach/gpio.h>
@@ -68,6 +69,7 @@ enum {
#define MSM_MPM_IRQ_INDEX(irq) (irq / 32)
#define MSM_MPM_IRQ_MASK(irq) BIT(irq % 32)
static struct msm_mpm_device_data msm_mpm_dev_data;
static uint8_t msm_mpm_irqs_a2m[MSM_MPM_NR_APPS_IRQS];
static DEFINE_SPINLOCK(msm_mpm_lock);
@@ -472,7 +474,7 @@ static int __init msm_mpm_early_init(void)
}
core_initcall(msm_mpm_early_init);
void msm_mpm_irq_extn_init(void)
void __init msm_mpm_irq_extn_init(struct msm_mpm_device_data *mpm_data)
{
gic_arch_extn.irq_mask = msm_mpm_disable_irq;
gic_arch_extn.irq_unmask = msm_mpm_enable_irq;
@@ -487,6 +489,29 @@ void msm_mpm_irq_extn_init(void)
msm_gpio_irq_extn.irq_set_wake = msm_mpm_set_irq_wake;
bitmap_set(msm_mpm_gpio_irqs_mask, NR_MSM_IRQS, NR_GPIO_IRQS);
if (!mpm_data) {
#ifdef CONFIG_MSM_MPM
BUG();
#endif
return;
}
memcpy(&msm_mpm_dev_data, mpm_data, sizeof(struct msm_mpm_device_data));
msm_mpm_dev_data.irqs_m2a =
kzalloc(msm_mpm_dev_data.irqs_m2a_size * sizeof(uint16_t),
GFP_KERNEL);
BUG_ON(!msm_mpm_dev_data.irqs_m2a);
memcpy(msm_mpm_dev_data.irqs_m2a, mpm_data->irqs_m2a,
msm_mpm_dev_data.irqs_m2a_size * sizeof(uint16_t));
msm_mpm_dev_data.bypassed_apps_irqs =
kzalloc(msm_mpm_dev_data.bypassed_apps_irqs_size *
sizeof(uint16_t), GFP_KERNEL);
BUG_ON(!msm_mpm_dev_data.bypassed_apps_irqs);
memcpy(msm_mpm_dev_data.bypassed_apps_irqs,
mpm_data->bypassed_apps_irqs,
msm_mpm_dev_data.bypassed_apps_irqs_size * sizeof(uint16_t));
}
static int __init msm_mpm_init(void)

14
arch/arm/mach-msm/mpm.h
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -38,9 +38,14 @@ struct msm_mpm_device_data {
unsigned int mpm_ipc_irq;
};
#ifdef CONFIG_MSM_MPM
extern struct msm_mpm_device_data msm_mpm_dev_data;
extern struct msm_mpm_device_data msm8660_mpm_dev_data;
extern struct msm_mpm_device_data msm8960_mpm_dev_data;
extern struct msm_mpm_device_data msm9615_mpm_dev_data;
extern struct msm_mpm_device_data apq8064_mpm_dev_data;
void msm_mpm_irq_extn_init(struct msm_mpm_device_data *mpm_data);
#ifdef CONFIG_MSM_MPM
int msm_mpm_enable_pin(enum msm_mpm_pin pin, unsigned int enable);
int msm_mpm_set_pin_wake(enum msm_mpm_pin pin, unsigned int on);
int msm_mpm_set_pin_type(enum msm_mpm_pin pin, unsigned int flow_type);
@@ -48,9 +53,7 @@ bool msm_mpm_irqs_detectable(bool from_idle);
bool msm_mpm_gpio_irqs_detectable(bool from_idle);
void msm_mpm_enter_sleep(bool from_idle);
void msm_mpm_exit_sleep(bool from_idle);
void msm_mpm_irq_extn_init(void);
#else
int msm_mpm_enable_irq(unsigned int irq, unsigned int enable)
{ return -ENODEV; }
int msm_mpm_set_irq_wake(unsigned int irq, unsigned int on)
@@ -69,7 +72,6 @@ bool msm_mpm_gpio_irqs_detectable(bool from_idle)
{ return false; }
void msm_mpm_enter_sleep(bool from_idle) {}
void msm_mpm_exit_sleep(bool from_idle) {}
void msm_mpm_irq_extn_init(void) {}
#endif

270
arch/arm/mach-msm/rpm.c
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -27,6 +27,7 @@
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
#include <asm/hardware/gic.h>
#include <mach/msm_iomap.h>
#include <mach/rpm.h>
@@ -45,14 +46,15 @@ struct msm_rpm_request {
};
struct msm_rpm_notif_config {
struct msm_rpm_iv_pair iv[MSM_RPM_SEL_MASK_SIZE * 2];
struct msm_rpm_iv_pair iv[SEL_MASK_SIZE * 2];
};
#define configured_iv(notif_cfg) ((notif_cfg)->iv)
#define registered_iv(notif_cfg) ((notif_cfg)->iv + MSM_RPM_SEL_MASK_SIZE)
#define registered_iv(notif_cfg) ((notif_cfg)->iv + msm_rpm_sel_mask_size)
static uint32_t msm_rpm_sel_mask_size;
static struct msm_rpm_platform_data msm_rpm_data;
static struct msm_rpm_platform_data *msm_rpm_platform;
static uint32_t msm_rpm_map[MSM_RPM_ID_LAST + 1];
static DEFINE_MUTEX(msm_rpm_mutex);
static DEFINE_SPINLOCK(msm_rpm_lock);
@@ -69,15 +71,34 @@ static bool msm_rpm_init_notif_done;
* Internal functions
*****************************************************************************/
static inline unsigned int target_enum(unsigned int id)
{
BUG_ON(id >= MSM_RPM_ID_LAST);
return msm_rpm_data.target_id[id].id;
}
static inline unsigned int target_status(unsigned int id)
{
BUG_ON(id >= MSM_RPM_STATUS_ID_LAST);
return msm_rpm_data.target_status[id];
}
static inline unsigned int target_ctrl(unsigned int id)
{
BUG_ON(id >= MSM_RPM_CTRL_LAST);
return msm_rpm_data.target_ctrl_id[id];
}
static inline uint32_t msm_rpm_read(unsigned int page, unsigned int reg)
{
return __raw_readl(msm_rpm_platform->reg_base_addrs[page] + reg * 4);
return __raw_readl(msm_rpm_data.reg_base_addrs[page] + reg * 4);
}
static inline void msm_rpm_write(
unsigned int page, unsigned int reg, uint32_t value)
{
__raw_writel(value, msm_rpm_platform->reg_base_addrs[page] + reg * 4);
__raw_writel(value,
msm_rpm_data.reg_base_addrs[page] + reg * 4);
}
static inline void msm_rpm_read_contiguous(
@@ -109,7 +130,8 @@ static inline void msm_rpm_write_contiguous_zeros(
static inline uint32_t msm_rpm_map_id_to_sel(uint32_t id)
{
return (id > MSM_RPM_ID_LAST) ? MSM_RPM_SEL_LAST + 1 : msm_rpm_map[id];
return (id >= MSM_RPM_ID_LAST) ? msm_rpm_data.sel_last + 1 :
msm_rpm_data.target_id[id].sel;
}
/*
@@ -128,8 +150,11 @@ static int msm_rpm_fill_sel_masks(
for (i = 0; i < count; i++) {
sel = msm_rpm_map_id_to_sel(req[i].id);
if (sel > MSM_RPM_SEL_LAST)
if (sel > msm_rpm_data.sel_last) {
pr_err("%s(): RPM ID %d not defined for target\n",
__func__, req[i].id);
return -EINVAL;
}
sel_masks[msm_rpm_get_sel_mask_reg(sel)] |=
msm_rpm_get_sel_mask(sel);
@@ -140,8 +165,8 @@ static int msm_rpm_fill_sel_masks(
static inline void msm_rpm_send_req_interrupt(void)
{
__raw_writel(msm_rpm_platform->msm_apps_ipc_rpm_val,
msm_rpm_platform->msm_apps_ipc_rpm_reg);
__raw_writel(msm_rpm_data.ipc_rpm_val,
msm_rpm_data.ipc_rpm_reg);
}
/*
@@ -155,26 +180,30 @@ static inline void msm_rpm_send_req_interrupt(void)
static int msm_rpm_process_ack_interrupt(void)
{
uint32_t ctx_mask_ack;
uint32_t sel_masks_ack[MSM_RPM_SEL_MASK_SIZE];
uint32_t sel_masks_ack[SEL_MASK_SIZE] = {0};
ctx_mask_ack = msm_rpm_read(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_ACK_CTX_0);
ctx_mask_ack = msm_rpm_read(MSM_RPM_PAGE_CTRL,
target_ctrl(MSM_RPM_CTRL_ACK_CTX_0));
msm_rpm_read_contiguous(MSM_RPM_PAGE_CTRL,
MSM_RPM_CTRL_ACK_SEL_0, sel_masks_ack, MSM_RPM_SEL_MASK_SIZE);
target_ctrl(MSM_RPM_CTRL_ACK_SEL_0),
sel_masks_ack, msm_rpm_sel_mask_size);
if (ctx_mask_ack & msm_rpm_get_ctx_mask(MSM_RPM_CTX_NOTIFICATION)) {
struct msm_rpm_notification *n;
int i;
list_for_each_entry(n, &msm_rpm_notifications, list)
for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++)
for (i = 0; i < msm_rpm_sel_mask_size; i++)
if (sel_masks_ack[i] & n->sel_masks[i]) {
up(&n->sem);
break;
}
msm_rpm_write_contiguous_zeros(MSM_RPM_PAGE_CTRL,
MSM_RPM_CTRL_ACK_SEL_0, MSM_RPM_SEL_MASK_SIZE);
msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_ACK_CTX_0, 0);
target_ctrl(MSM_RPM_CTRL_ACK_SEL_0),
msm_rpm_sel_mask_size);
msm_rpm_write(MSM_RPM_PAGE_CTRL,
target_ctrl(MSM_RPM_CTRL_ACK_CTX_0), 0);
/* Ensure the write is complete before return */
mb();
@@ -191,11 +220,13 @@ static int msm_rpm_process_ack_interrupt(void)
for (i = 0; i < msm_rpm_request->count; i++)
msm_rpm_request->req[i].value =
msm_rpm_read(MSM_RPM_PAGE_ACK,
msm_rpm_request->req[i].id);
target_enum(msm_rpm_request->req[i].id));
msm_rpm_write_contiguous_zeros(MSM_RPM_PAGE_CTRL,
MSM_RPM_CTRL_ACK_SEL_0, MSM_RPM_SEL_MASK_SIZE);
msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_ACK_CTX_0, 0);
target_ctrl(MSM_RPM_CTRL_ACK_SEL_0),
msm_rpm_sel_mask_size);
msm_rpm_write(MSM_RPM_PAGE_CTRL,
target_ctrl(MSM_RPM_CTRL_ACK_CTX_0), 0);
/* Ensure the write is complete before return */
mb();
@@ -233,7 +264,7 @@ static void msm_rpm_busy_wait_for_request_completion(
int rc;
do {
while (!gic_is_spi_pending(msm_rpm_platform->irq_ack) &&
while (!gic_is_spi_pending(msm_rpm_data.irq_ack) &&
msm_rpm_request) {
if (allow_async_completion)
spin_unlock(&msm_rpm_irq_lock);
@@ -246,7 +277,7 @@ static void msm_rpm_busy_wait_for_request_completion(
break;
rc = msm_rpm_process_ack_interrupt();
gic_clear_spi_pending(msm_rpm_platform->irq_ack);
gic_clear_spi_pending(msm_rpm_data.irq_ack);
} while (rc);
}
@@ -265,7 +296,7 @@ static int msm_rpm_set_exclusive(int ctx,
unsigned long flags;
uint32_t ctx_mask = msm_rpm_get_ctx_mask(ctx);
uint32_t ctx_mask_ack = 0;
uint32_t sel_masks_ack[MSM_RPM_SEL_MASK_SIZE];
uint32_t sel_masks_ack[SEL_MASK_SIZE];
int i;
msm_rpm_request_irq_mode.req = req;
@@ -281,13 +312,16 @@ static int msm_rpm_set_exclusive(int ctx,
msm_rpm_request = &msm_rpm_request_irq_mode;
for (i = 0; i < count; i++) {
BUG_ON(req[i].id > MSM_RPM_ID_LAST);
msm_rpm_write(MSM_RPM_PAGE_REQ, req[i].id, req[i].value);
BUG_ON(target_enum(req[i].id) >= MSM_RPM_ID_LAST);
msm_rpm_write(MSM_RPM_PAGE_REQ,
target_enum(req[i].id), req[i].value);
}
msm_rpm_write_contiguous(MSM_RPM_PAGE_CTRL,
MSM_RPM_CTRL_REQ_SEL_0, sel_masks, MSM_RPM_SEL_MASK_SIZE);
msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_REQ_CTX_0, ctx_mask);
target_ctrl(MSM_RPM_CTRL_REQ_SEL_0),
sel_masks, msm_rpm_sel_mask_size);
msm_rpm_write(MSM_RPM_PAGE_CTRL,
target_ctrl(MSM_RPM_CTRL_REQ_CTX_0), ctx_mask);
/* Ensure RPM data is written before sending the interrupt */
mb();
@@ -317,11 +351,11 @@ static int msm_rpm_set_exclusive(int ctx,
static int msm_rpm_set_exclusive_noirq(int ctx,
uint32_t *sel_masks, struct msm_rpm_iv_pair *req, int count)
{
unsigned int irq = msm_rpm_platform->irq_ack;
unsigned int irq = msm_rpm_data.irq_ack;
unsigned long flags;
uint32_t ctx_mask = msm_rpm_get_ctx_mask(ctx);
uint32_t ctx_mask_ack = 0;
uint32_t sel_masks_ack[MSM_RPM_SEL_MASK_SIZE];
uint32_t sel_masks_ack[SEL_MASK_SIZE];
struct irq_chip *irq_chip = NULL;
int i;
@@ -347,13 +381,16 @@ static int msm_rpm_set_exclusive_noirq(int ctx,
msm_rpm_request = &msm_rpm_request_poll_mode;
for (i = 0; i < count; i++) {
BUG_ON(req[i].id > MSM_RPM_ID_LAST);
msm_rpm_write(MSM_RPM_PAGE_REQ, req[i].id, req[i].value);
BUG_ON(target_enum(req[i].id) >= MSM_RPM_ID_LAST);
msm_rpm_write(MSM_RPM_PAGE_REQ,
target_enum(req[i].id), req[i].value);
}
msm_rpm_write_contiguous(MSM_RPM_PAGE_CTRL,
MSM_RPM_CTRL_REQ_SEL_0, sel_masks, MSM_RPM_SEL_MASK_SIZE);
msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_REQ_CTX_0, ctx_mask);
target_ctrl(MSM_RPM_CTRL_REQ_SEL_0),
sel_masks, msm_rpm_sel_mask_size);
msm_rpm_write(MSM_RPM_PAGE_CTRL,
target_ctrl(MSM_RPM_CTRL_REQ_CTX_0), ctx_mask);
/* Ensure RPM data is written before sending the interrupt */
mb();
@@ -385,15 +422,11 @@ static int msm_rpm_set_exclusive_noirq(int ctx,
static int msm_rpm_set_common(
int ctx, struct msm_rpm_iv_pair *req, int count, bool noirq)
{
uint32_t sel_masks[MSM_RPM_SEL_MASK_SIZE] = {};
uint32_t sel_masks[SEL_MASK_SIZE] = {};
int rc;
if (!msm_rpm_platform) {
if (cpu_is_apq8064())
return 0;
else
return -ENODEV;
}
if (cpu_is_apq8064())
return 0;
if (ctx >= MSM_RPM_CTX_SET_COUNT) {
rc = -EINVAL;
@@ -433,17 +466,13 @@ set_common_exit:
static int msm_rpm_clear_common(
int ctx, struct msm_rpm_iv_pair *req, int count, bool noirq)
{
uint32_t sel_masks[MSM_RPM_SEL_MASK_SIZE] = {};
struct msm_rpm_iv_pair r[MSM_RPM_SEL_MASK_SIZE];
uint32_t sel_masks[SEL_MASK_SIZE] = {};
struct msm_rpm_iv_pair r[SEL_MASK_SIZE];
int rc;
int i;
if (!msm_rpm_platform) {
if (cpu_is_apq8064())
return 0;
else
return -ENODEV;
}
if (cpu_is_apq8064())
return 0;
if (ctx >= MSM_RPM_CTX_SET_COUNT) {
rc = -EINVAL;
@@ -460,8 +489,8 @@ static int msm_rpm_clear_common(
}
memset(sel_masks, 0, sizeof(sel_masks));
sel_masks[msm_rpm_get_sel_mask_reg(MSM_RPM_SEL_INVALIDATE)] |=
msm_rpm_get_sel_mask(MSM_RPM_SEL_INVALIDATE);
sel_masks[msm_rpm_get_sel_mask_reg(msm_rpm_data.sel_invalidate)] |=
msm_rpm_get_sel_mask(msm_rpm_data.sel_invalidate);
if (noirq) {
unsigned long flags;
@@ -492,12 +521,14 @@ static void msm_rpm_update_notification(uint32_t ctx,
struct msm_rpm_notif_config *curr_cfg,
struct msm_rpm_notif_config *new_cfg)
{
unsigned int sel_notif = msm_rpm_data.sel_notification;
if (memcmp(curr_cfg, new_cfg, sizeof(*new_cfg))) {
uint32_t sel_masks[MSM_RPM_SEL_MASK_SIZE] = {};
uint32_t sel_masks[SEL_MASK_SIZE] = {};
int rc;
sel_masks[msm_rpm_get_sel_mask_reg(MSM_RPM_SEL_NOTIFICATION)]
|= msm_rpm_get_sel_mask(MSM_RPM_SEL_NOTIFICATION);
sel_masks[msm_rpm_get_sel_mask_reg(sel_notif)]
|= msm_rpm_get_sel_mask(sel_notif);
rc = msm_rpm_set_exclusive(ctx,
sel_masks, new_cfg->iv, ARRAY_SIZE(new_cfg->iv));
@@ -519,7 +550,7 @@ static void msm_rpm_initialize_notification(void)
for (ctx = MSM_RPM_CTX_SET_0; ctx <= MSM_RPM_CTX_SET_SLEEP; ctx++) {
cfg = msm_rpm_notif_cfgs[ctx];
for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++) {
for (i = 0; i < msm_rpm_sel_mask_size; i++) {
configured_iv(&cfg)[i].id =
MSM_RPM_ID_NOTIFICATION_CONFIGURED_0 + i;
configured_iv(&cfg)[i].value = ~0UL;
@@ -581,28 +612,36 @@ int msm_rpm_get_status(struct msm_rpm_iv_pair *status, int count)
int rc;
int i;
if (!msm_rpm_platform) {
if (cpu_is_apq8064())
return 0;
else
return -ENODEV;
}
if (cpu_is_apq8064())
return 0;
seq_begin = msm_rpm_read(MSM_RPM_PAGE_STATUS,
MSM_RPM_STATUS_ID_SEQUENCE);
target_status(MSM_RPM_STATUS_ID_SEQUENCE));
for (i = 0; i < count; i++) {
if (status[i].id > MSM_RPM_STATUS_ID_LAST) {
int target_status_id;
if (status[i].id >= MSM_RPM_STATUS_ID_LAST) {
pr_err("%s(): Status ID beyond limits\n", __func__);
rc = -EINVAL;
goto get_status_exit;
}
target_status_id = target_status(status[i].id);
if (target_status_id >= MSM_RPM_STATUS_ID_LAST) {
pr_err("%s(): Status id %d not defined for target\n",
__func__,
target_status_id);
rc = -EINVAL;
goto get_status_exit;
}
status[i].value = msm_rpm_read(MSM_RPM_PAGE_STATUS,
status[i].id);
target_status_id);
}
seq_end = msm_rpm_read(MSM_RPM_PAGE_STATUS,
MSM_RPM_STATUS_ID_SEQUENCE);
target_status(MSM_RPM_STATUS_ID_SEQUENCE));
rc = (seq_begin != seq_end || (seq_begin & 0x01)) ? -EBUSY : 0;
@@ -729,12 +768,8 @@ int msm_rpm_register_notification(struct msm_rpm_notification *n,
int rc;
int i;
if (!msm_rpm_platform) {
if (cpu_is_apq8064())
return 0;
else
return -ENODEV;
}
if (cpu_is_apq8064())
return 0;
INIT_LIST_HEAD(&n->list);
rc = msm_rpm_fill_sel_masks(n->sel_masks, req, count);
@@ -757,7 +792,7 @@ int msm_rpm_register_notification(struct msm_rpm_notification *n,
ctx = MSM_RPM_CTX_SET_0;
cfg = msm_rpm_notif_cfgs[ctx];
for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++)
for (i = 0; i < msm_rpm_sel_mask_size; i++)
registered_iv(&cfg)[i].value |= n->sel_masks[i];
msm_rpm_update_notification(ctx, &msm_rpm_notif_cfgs[ctx], &cfg);
@@ -788,12 +823,8 @@ int msm_rpm_unregister_notification(struct msm_rpm_notification *n)
int rc;
int i;
if (!msm_rpm_platform) {
if (cpu_is_apq8064())
return 0;
else
return -ENODEV;
}
if (cpu_is_apq8064())
return 0;
rc = mutex_lock_interruptible(&msm_rpm_mutex);
if (rc)
@@ -802,13 +833,13 @@ int msm_rpm_unregister_notification(struct msm_rpm_notification *n)
ctx = MSM_RPM_CTX_SET_0;
cfg = msm_rpm_notif_cfgs[ctx];
for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++)
for (i = 0; i < msm_rpm_sel_mask_size; i++)
registered_iv(&cfg)[i].value = 0;
spin_lock_irqsave(&msm_rpm_irq_lock, flags);
list_del(&n->list);
list_for_each_entry(n, &msm_rpm_notifications, list)
for (i = 0; i < MSM_RPM_SEL_MASK_SIZE; i++)
for (i = 0; i < msm_rpm_sel_mask_size; i++)
registered_iv(&cfg)[i].value |= n->sel_masks[i];
spin_unlock_irqrestore(&msm_rpm_irq_lock, flags);
@@ -826,7 +857,7 @@ static ssize_t driver_version_show(struct kobject *kobj,
struct kobj_attribute *attr, char *buf)
{
return snprintf(buf, PAGE_SIZE, "%u.%u.%u\n",
RPM_MAJOR_VER, RPM_MINOR_VER, RPM_BUILD_VER);
msm_rpm_data.ver[0], msm_rpm_data.ver[1], msm_rpm_data.ver[2]);
}
static ssize_t fw_version_show(struct kobject *kobj,
@@ -869,18 +900,49 @@ static struct platform_driver msm_rpm_platform_driver = {
},
};
static void __init msm_rpm_populate_map(void)
static void __init msm_rpm_populate_map(struct msm_rpm_platform_data *data)
{
int i, k;
int i, j;
struct msm_rpm_map_data *src = NULL;
struct msm_rpm_map_data *dst = NULL;
for (i = 0; i < ARRAY_SIZE(msm_rpm_map); i++)
msm_rpm_map[i] = MSM_RPM_SEL_LAST + 1;
for (i = 0; i < MSM_RPM_ID_LAST;) {
src = &data->target_id[i];
dst = &msm_rpm_data.target_id[i];
for (i = 0; i < rpm_map_data_size; i++) {
struct msm_rpm_map_data *raw_data = &rpm_map_data[i];
dst->id = MSM_RPM_ID_LAST;
dst->sel = msm_rpm_data.sel_last + 1;
for (k = 0; k < raw_data->count; k++)
msm_rpm_map[raw_data->id + k] = raw_data->sel;
/*
* copy the target specific id of the current and also of
* all the #count id's that follow the current.
* [MSM_RPM_ID_PM8921_S1_0] = { MSM_RPM_8960_ID_PM8921_S1_0,
* MSM_RPM_8960_SEL_PM8921_S1,
* 2},
* [MSM_RPM_ID_PM8921_S1_1] = { 0, 0, 0 },
* should translate to
* [MSM_RPM_ID_PM8921_S1_0] = { MSM_RPM_8960_ID_PM8921_S1_0,
* MSM_RPM_8960_SEL_PM8921,
* 2 },
* [MSM_RPM_ID_PM8921_S1_1] = { MSM_RPM_8960_ID_PM8921_S1_0 + 1,
* MSM_RPM_8960_SEL_PM8921,
* 0 },
*/
for (j = 0; j < src->count; j++) {
dst = &msm_rpm_data.target_id[i + j];
dst->id = src->id + j;
dst->sel = src->sel;
}
i += (src->count) ? src->count : 1;
}
for (i = 0; i < MSM_RPM_STATUS_ID_LAST; i++) {
if (data->target_status[i] & MSM_RPM_STATUS_ID_VALID)
msm_rpm_data.target_status[i] &=
~MSM_RPM_STATUS_ID_VALID;
else
msm_rpm_data.target_status[i] = MSM_RPM_STATUS_ID_LAST;
}
}
@@ -892,33 +954,37 @@ int __init msm_rpm_init(struct msm_rpm_platform_data *data)
if (cpu_is_apq8064())
return 0;
msm_rpm_platform = data;
memcpy(&msm_rpm_data, data, sizeof(struct msm_rpm_platform_data));
msm_rpm_sel_mask_size = msm_rpm_data.sel_last / 32 + 1;
BUG_ON(SEL_MASK_SIZE < msm_rpm_sel_mask_size);
fw_major = msm_rpm_read(MSM_RPM_PAGE_STATUS,
MSM_RPM_STATUS_ID_VERSION_MAJOR);
target_status(MSM_RPM_STATUS_ID_VERSION_MAJOR));
fw_minor = msm_rpm_read(MSM_RPM_PAGE_STATUS,
MSM_RPM_STATUS_ID_VERSION_MINOR);
target_status(MSM_RPM_STATUS_ID_VERSION_MINOR));
fw_build = msm_rpm_read(MSM_RPM_PAGE_STATUS,
MSM_RPM_STATUS_ID_VERSION_BUILD);
target_status(MSM_RPM_STATUS_ID_VERSION_BUILD));
pr_info("%s: RPM firmware %u.%u.%u\n", __func__,
fw_major, fw_minor, fw_build);
if (fw_major != RPM_MAJOR_VER) {
if (fw_major != msm_rpm_data.ver[0]) {
pr_err("%s: RPM version %u.%u.%u incompatible with "
"this driver version %u.%u.%u\n", __func__,
fw_major, fw_minor, fw_build,
RPM_MAJOR_VER, RPM_MINOR_VER, RPM_BUILD_VER);
msm_rpm_data.ver[0],
msm_rpm_data.ver[1],
msm_rpm_data.ver[2]);
return -EFAULT;
}
msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_VERSION_MAJOR,
RPM_MAJOR_VER);
msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_VERSION_MINOR,
RPM_MINOR_VER);
msm_rpm_write(MSM_RPM_PAGE_CTRL, MSM_RPM_CTRL_VERSION_BUILD,
RPM_BUILD_VER);
msm_rpm_write(MSM_RPM_PAGE_CTRL,
target_ctrl(MSM_RPM_CTRL_VERSION_MAJOR), msm_rpm_data.ver[0]);
msm_rpm_write(MSM_RPM_PAGE_CTRL,
target_ctrl(MSM_RPM_CTRL_VERSION_MINOR), msm_rpm_data.ver[1]);
msm_rpm_write(MSM_RPM_PAGE_CTRL,
target_ctrl(MSM_RPM_CTRL_VERSION_BUILD), msm_rpm_data.ver[2]);
irq = msm_rpm_platform->irq_ack;
irq = data->irq_ack;
rc = request_irq(irq, msm_rpm_ack_interrupt,
IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND,
@@ -936,7 +1002,7 @@ int __init msm_rpm_init(struct msm_rpm_platform_data *data)
return rc;
}
msm_rpm_populate_map();
msm_rpm_populate_map(data);
return platform_driver_register(&msm_rpm_platform_driver);
}

156
arch/arm/mach-msm/rpm_resources.c
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -65,6 +65,10 @@ static ssize_t msm_rpmrs_resource_attr_show(
static ssize_t msm_rpmrs_resource_attr_store(struct kobject *kobj,
struct kobj_attribute *attr, const char *buf, size_t count);
static int vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_LAST];
static int vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_LAST];
static int vdd_mask;
#define MSM_RPMRS_MAX_RS_REGISTER_COUNT 2
#define RPMRS_ATTR(_name) \
@@ -86,7 +90,6 @@ struct msm_rpmrs_resource {
};
static struct msm_rpmrs_resource msm_rpmrs_pxo = {
.rs[0].id = MSM_RPMRS_ID_PXO_CLK,
.size = 1,
.name = "pxo",
.beyond_limits = msm_rpmrs_pxo_beyond_limits,
@@ -96,7 +99,6 @@ static struct msm_rpmrs_resource msm_rpmrs_pxo = {
};
static struct msm_rpmrs_resource msm_rpmrs_l2_cache = {
.rs[0].id = MSM_RPMRS_ID_APPS_L2_CACHE_CTL,
.size = 1,
.name = "L2_cache",
.beyond_limits = msm_rpmrs_l2_cache_beyond_limits,
@@ -106,8 +108,6 @@ static struct msm_rpmrs_resource msm_rpmrs_l2_cache = {
};
static struct msm_rpmrs_resource msm_rpmrs_vdd_mem = {
.rs[0].id = MSM_RPMRS_ID_VDD_MEM_0,
.rs[1].id = MSM_RPMRS_ID_VDD_MEM_1,
.size = 2,
.name = "vdd_mem",
.beyond_limits = msm_rpmrs_vdd_mem_beyond_limits,
@@ -117,8 +117,6 @@ static struct msm_rpmrs_resource msm_rpmrs_vdd_mem = {
};
static struct msm_rpmrs_resource msm_rpmrs_vdd_dig = {
.rs[0].id = MSM_RPMRS_ID_VDD_DIG_0,
.rs[1].id = MSM_RPMRS_ID_VDD_DIG_1,
.size = 2,
.name = "vdd_dig",
.beyond_limits = msm_rpmrs_vdd_dig_beyond_limits,
@@ -128,7 +126,6 @@ static struct msm_rpmrs_resource msm_rpmrs_vdd_dig = {
};
static struct msm_rpmrs_resource msm_rpmrs_rpm_ctl = {
.rs[0].id = MSM_RPMRS_ID_RPM_CTL,
.size = 1,
.name = "rpm_ctl",
.beyond_limits = NULL,
@@ -145,12 +142,12 @@ static struct msm_rpmrs_resource *msm_rpmrs_resources[] = {
&msm_rpmrs_rpm_ctl,
};
static uint32_t msm_rpmrs_buffer[MSM_RPM_ID_LAST + 1];
static DECLARE_BITMAP(msm_rpmrs_buffered, MSM_RPM_ID_LAST + 1);
static DECLARE_BITMAP(msm_rpmrs_listed, MSM_RPM_ID_LAST + 1);
static uint32_t msm_rpmrs_buffer[MSM_RPM_ID_LAST];
static DECLARE_BITMAP(msm_rpmrs_buffered, MSM_RPM_ID_LAST);
static DECLARE_BITMAP(msm_rpmrs_listed, MSM_RPM_ID_LAST);
static DEFINE_SPINLOCK(msm_rpmrs_lock);
#define MSM_RPMRS_VDD(v) ((v) & (MSM_RPMRS_VDD_MASK))
#define MSM_RPMRS_VDD(v) ((v) & (vdd_mask))
/******************************************************************************
* Attribute Definitions
@@ -290,20 +287,19 @@ static bool msm_rpmrs_vdd_mem_beyond_limits(struct msm_rpmrs_limits *limits)
uint32_t buffered_value = msm_rpmrs_buffer[rs->rs[0].id];
if (rs->enable_low_power == 0)
vdd_mem = MSM_RPMRS_VDD_MEM_ACTIVE;
vdd_mem = vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_ACTIVE];
else if (rs->enable_low_power == 1)
vdd_mem = MSM_RPMRS_VDD_MEM_RET_HIGH;
vdd_mem = vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_RET_HIGH];
else
vdd_mem = MSM_RPMRS_VDD_MEM_RET_LOW;
vdd_mem = vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_RET_LOW];
if (MSM_RPMRS_VDD(buffered_value) > MSM_RPMRS_VDD(vdd_mem))
vdd_mem = buffered_value;
vdd_mem = MSM_RPMRS_VDD(buffered_value);
} else {
vdd_mem = MSM_RPMRS_VDD_MEM_ACTIVE;
vdd_mem = vdd_mem_vlevels[MSM_RPMRS_VDD_MEM_ACTIVE];
}
return MSM_RPMRS_VDD(vdd_mem) >
MSM_RPMRS_VDD(limits->vdd_mem_upper_bound);
return vdd_mem > vdd_mem_vlevels[limits->vdd_mem_upper_bound];
}
static void msm_rpmrs_aggregate_vdd_mem(struct msm_rpmrs_limits *limits)
@@ -313,9 +309,9 @@ static void msm_rpmrs_aggregate_vdd_mem(struct msm_rpmrs_limits *limits)
if (test_bit(rs->rs[0].id, msm_rpmrs_buffered)) {
rs->rs[0].value = *buf;
if (MSM_RPMRS_VDD(limits->vdd_mem) > MSM_RPMRS_VDD(*buf)) {
*buf &= ~MSM_RPMRS_VDD_MASK;
*buf |= MSM_RPMRS_VDD(limits->vdd_mem);
if (vdd_mem_vlevels[limits->vdd_mem] > MSM_RPMRS_VDD(*buf)) {
*buf &= ~vdd_mask;
*buf |= vdd_mem_vlevels[limits->vdd_mem];
}
if (MSM_RPMRS_DEBUG_OUTPUT & msm_rpmrs_debug_mask)
@@ -341,20 +337,19 @@ static bool msm_rpmrs_vdd_dig_beyond_limits(struct msm_rpmrs_limits *limits)
uint32_t buffered_value = msm_rpmrs_buffer[rs->rs[0].id];
if (rs->enable_low_power == 0)
vdd_dig = MSM_RPMRS_VDD_DIG_ACTIVE;
vdd_dig = vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_ACTIVE];
else if (rs->enable_low_power == 1)
vdd_dig = MSM_RPMRS_VDD_DIG_RET_HIGH;
vdd_dig = vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_RET_HIGH];
else
vdd_dig = MSM_RPMRS_VDD_DIG_RET_LOW;
vdd_dig = vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_RET_LOW];
if (MSM_RPMRS_VDD(buffered_value) > MSM_RPMRS_VDD(vdd_dig))
vdd_dig = buffered_value;
vdd_dig = MSM_RPMRS_VDD(buffered_value);
} else {
vdd_dig = MSM_RPMRS_VDD_DIG_ACTIVE;
vdd_dig = vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_ACTIVE];
}
return MSM_RPMRS_VDD(vdd_dig) >
MSM_RPMRS_VDD(limits->vdd_dig_upper_bound);
return vdd_dig > vdd_dig_vlevels[limits->vdd_dig_upper_bound];
}
static void msm_rpmrs_aggregate_vdd_dig(struct msm_rpmrs_limits *limits)
@@ -364,9 +359,9 @@ static void msm_rpmrs_aggregate_vdd_dig(struct msm_rpmrs_limits *limits)
if (test_bit(rs->rs[0].id, msm_rpmrs_buffered)) {
rs->rs[0].value = *buf;
if (MSM_RPMRS_VDD(limits->vdd_dig) > MSM_RPMRS_VDD(*buf)) {
*buf &= ~MSM_RPMRS_VDD_MASK;
*buf |= MSM_RPMRS_VDD(limits->vdd_dig);
if (vdd_dig_vlevels[limits->vdd_dig] > MSM_RPMRS_VDD(*buf)) {
*buf &= ~vdd_mask;
*buf |= vdd_dig_vlevels[limits->vdd_dig];
}
@@ -392,7 +387,8 @@ static bool msm_rpmrs_irqs_detectable(struct msm_rpmrs_limits *limits,
bool irqs_detect, bool gpio_detect)
{
if (limits->vdd_dig_upper_bound <= MSM_RPMRS_VDD_DIG_RET_HIGH)
if (vdd_dig_vlevels[limits->vdd_dig_upper_bound] <=
vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_RET_HIGH])
return irqs_detect;
if (limits->pxo == MSM_RPMRS_PXO_OFF)
@@ -404,7 +400,8 @@ static bool msm_rpmrs_irqs_detectable(struct msm_rpmrs_limits *limits,
static bool msm_rpmrs_use_mpm(struct msm_rpmrs_limits *limits)
{
return (limits->pxo == MSM_RPMRS_PXO_OFF) ||
(limits->vdd_dig <= MSM_RPMRS_VDD_DIG_RET_HIGH);
(vdd_dig_vlevels[limits->vdd_dig] <=
vdd_dig_vlevels[MSM_RPMRS_VDD_DIG_RET_HIGH]);
}
static void msm_rpmrs_update_levels(void)
@@ -428,6 +425,7 @@ static void msm_rpmrs_update_levels(void)
break;
}
}
}
}
@@ -443,7 +441,7 @@ static int msm_rpmrs_buffer_request(struct msm_rpm_iv_pair *req, int count)
int i;
for (i = 0; i < count; i++)
if (req[i].id > MSM_RPM_ID_LAST)
if (req[i].id >= MSM_RPM_ID_LAST)
return -EINVAL;
for (i = 0, listed = false; i < count; i++) {
@@ -476,7 +474,7 @@ static int msm_rpmrs_clear_buffer(struct msm_rpm_iv_pair *req, int count)
int i;
for (i = 0; i < count; i++)
if (req[i].id > MSM_RPM_ID_LAST)
if (req[i].id >= MSM_RPM_ID_LAST)
return -EINVAL;
for (i = 0, listed = false; i < count; i++) {
@@ -557,7 +555,7 @@ static int msm_rpmrs_flush_buffer(
msm_rpmrs_resources[i]->aggregate(limits);
}
count = bitmap_weight(msm_rpmrs_buffered, MSM_RPM_ID_LAST + 1);
count = bitmap_weight(msm_rpmrs_buffered, MSM_RPM_ID_LAST);
req = kmalloc(sizeof(*req) * count, GFP_ATOMIC);
if (!req) {
@@ -566,9 +564,9 @@ static int msm_rpmrs_flush_buffer(
}
count = 0;
i = find_first_bit(msm_rpmrs_buffered, MSM_RPM_ID_LAST + 1);
i = find_first_bit(msm_rpmrs_buffered, MSM_RPM_ID_LAST);
while (i < MSM_RPM_ID_LAST + 1) {
while (i < MSM_RPM_ID_LAST) {
if (MSM_RPMRS_DEBUG_OUTPUT & msm_rpmrs_debug_mask)
pr_info("%s: reg %d: 0x%x\n",
__func__, i, msm_rpmrs_buffer[i]);
@@ -577,7 +575,7 @@ static int msm_rpmrs_flush_buffer(
req[count].value = msm_rpmrs_buffer[i];
count++;
i = find_next_bit(msm_rpmrs_buffered, MSM_RPM_ID_LAST+1, i+1);
i = find_next_bit(msm_rpmrs_buffered, MSM_RPM_ID_LAST, i + 1);
}
rc = msm_rpm_set_noirq(MSM_RPM_CTX_SET_SLEEP, req, count);
@@ -587,7 +585,7 @@ static int msm_rpmrs_flush_buffer(
goto flush_buffer_restore;
bitmap_and(msm_rpmrs_buffered,
msm_rpmrs_buffered, msm_rpmrs_listed, MSM_RPM_ID_LAST + 1);
msm_rpmrs_buffered, msm_rpmrs_listed, MSM_RPM_ID_LAST);
flush_buffer_restore:
for (i = 0; i < ARRAY_SIZE(msm_rpmrs_resources); i++) {
@@ -664,7 +662,8 @@ static ssize_t msm_rpmrs_resource_attr_show(
spin_lock_irqsave(&msm_rpmrs_lock, flags);
/* special case active-set signal for MSM_RPMRS_ID_RPM_CTL */
if (GET_RS_FROM_ATTR(attr)->rs[0].id == MSM_RPMRS_ID_RPM_CTL)
if (GET_RS_FROM_ATTR(attr)->rs[0].id ==
msm_rpmrs_rpm_ctl.rs[0].id)
temp = GET_RS_FROM_ATTR(attr)->rs[0].value;
else
temp = GET_RS_FROM_ATTR(attr)->enable_low_power;
@@ -698,9 +697,10 @@ static ssize_t msm_rpmrs_resource_attr_store(struct kobject *kobj,
GET_RS_FROM_ATTR(attr)->enable_low_power = temp;
/* special case active-set signal for MSM_RPMRS_ID_RPM_CTL */
if (GET_RS_FROM_ATTR(attr)->rs[0].id == MSM_RPMRS_ID_RPM_CTL) {
if (GET_RS_FROM_ATTR(attr)->rs[0].id ==
msm_rpmrs_rpm_ctl.rs[0].id) {
struct msm_rpm_iv_pair req;
req.id = MSM_RPMRS_ID_RPM_CTL;
req.id = msm_rpmrs_rpm_ctl.rs[0].id;
req.value = GET_RS_FROM_ATTR(attr)->enable_low_power;
GET_RS_FROM_ATTR(attr)->rs[0].value = req.value;
@@ -855,7 +855,7 @@ void msm_rpmrs_show_resources(void)
spin_lock_irqsave(&msm_rpmrs_lock, flags);
for (i = 0; i < ARRAY_SIZE(msm_rpmrs_resources); i++) {
rs = msm_rpmrs_resources[i];
if (rs->rs[0].id < MSM_RPM_ID_LAST + 1)
if (rs->rs[0].id < MSM_RPM_ID_LAST)
pr_info("%s: resource %s: buffered %d, value 0x%x\n",
__func__, rs->name,
test_bit(rs->rs[0].id, msm_rpmrs_buffered),
@@ -978,14 +978,51 @@ static struct notifier_block __refdata rpmrs_cpu_notifier = {
.notifier_call = rpmrs_cpu_callback,
};
int __init msm_rpmrs_levels_init(struct msm_rpmrs_level *levels, int size)
int __init msm_rpmrs_levels_init(struct msm_rpmrs_platform_data *data)
{
msm_rpmrs_levels = kzalloc(sizeof(struct msm_rpmrs_level) * size,
GFP_KERNEL);
int i, k;
struct msm_rpmrs_level *levels = data->levels;
msm_rpmrs_level_count = data->num_levels;
msm_rpmrs_levels = kzalloc(sizeof(struct msm_rpmrs_level) *
msm_rpmrs_level_count, GFP_KERNEL);
if (!msm_rpmrs_levels)
return -ENOMEM;
msm_rpmrs_level_count = size;
memcpy(msm_rpmrs_levels, levels, size * sizeof(struct msm_rpmrs_level));
memcpy(msm_rpmrs_levels, levels,
msm_rpmrs_level_count * sizeof(struct msm_rpmrs_level));
memcpy(vdd_dig_vlevels, data->vdd_dig_levels,
(MSM_RPMRS_VDD_DIG_MAX + 1) * sizeof(vdd_dig_vlevels[0]));
memcpy(vdd_mem_vlevels, data->vdd_mem_levels,
(MSM_RPMRS_VDD_MEM_MAX + 1) * sizeof(vdd_mem_vlevels[0]));
vdd_mask = data->vdd_mask;
msm_rpmrs_pxo.rs[0].id = data->rpmrs_target_id[MSM_RPMRS_ID_PXO_CLK];
msm_rpmrs_l2_cache.rs[0].id =
data->rpmrs_target_id[MSM_RPMRS_ID_L2_CACHE_CTL];
msm_rpmrs_vdd_mem.rs[0].id =
data->rpmrs_target_id[MSM_RPMRS_ID_VDD_MEM_0];
msm_rpmrs_vdd_mem.rs[1].id =
data->rpmrs_target_id[MSM_RPMRS_ID_VDD_MEM_1];
msm_rpmrs_vdd_dig.rs[0].id =
data->rpmrs_target_id[MSM_RPMRS_ID_VDD_DIG_0];
msm_rpmrs_vdd_dig.rs[1].id =
data->rpmrs_target_id[MSM_RPMRS_ID_VDD_DIG_1];
msm_rpmrs_rpm_ctl.rs[0].id =
data->rpmrs_target_id[MSM_RPMRS_ID_RPM_CTL];
/* Initialize listed bitmap for valid resource IDs */
for (i = 0; i < ARRAY_SIZE(msm_rpmrs_resources); i++) {
for (k = 0; k < msm_rpmrs_resources[i]->size; k++)
if (msm_rpmrs_resources[i]->rs[k].id >=
MSM_RPM_ID_LAST)
continue;
set_bit(msm_rpmrs_resources[i]->rs[k].id,
msm_rpmrs_listed);
}
return 0;
}
@@ -1001,7 +1038,7 @@ static int __init msm_rpmrs_init(void)
BUG_ON(!msm_rpmrs_levels);
if (cpu_is_msm8x60()) {
req.id = MSM_RPMRS_ID_APPS_L2_CACHE_CTL;
req.id = msm_rpmrs_l2_cache.rs[0].id;
req.value = 1;
rc = msm_rpm_set(MSM_RPM_CTX_SET_0, &req, 1);
@@ -1011,7 +1048,7 @@ static int __init msm_rpmrs_init(void)
goto init_exit;
}
req.id = MSM_RPMRS_ID_APPS_L2_CACHE_CTL;
req.id = msm_rpmrs_l2_cache.rs[0].id;
req.value = 0;
rc = msm_rpmrs_set(MSM_RPM_CTX_SET_SLEEP, &req, 1);
@@ -1029,21 +1066,6 @@ init_exit:
}
device_initcall(msm_rpmrs_init);
static int __init msm_rpmrs_early_init(void)
{
int i, k;
/* Initialize listed bitmap for valid resource IDs */
for (i = 0; i < ARRAY_SIZE(msm_rpmrs_resources); i++) {
for (k = 0; k < msm_rpmrs_resources[i]->size; k++)
set_bit(msm_rpmrs_resources[i]->rs[k].id,
msm_rpmrs_listed);
}
return 0;
}
early_initcall(msm_rpmrs_early_init);
static int __init msm_rpmrs_l2_init(void)
{
if (cpu_is_msm8960() || cpu_is_msm8930()) {

61
arch/arm/mach-msm/rpm_resources.h
View File

@@ -1,4 +1,4 @@
/* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
/* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -17,17 +17,15 @@
#include <mach/rpm.h>
#include <mach/pm.h>
struct msm_rpmrs_limits {
uint32_t pxo;
uint32_t l2_cache;
uint32_t vdd_mem_upper_bound;
uint32_t vdd_mem;
uint32_t vdd_dig_upper_bound;
uint32_t vdd_dig;
uint32_t latency_us[NR_CPUS];
uint32_t power[NR_CPUS];
enum {
MSM_RPMRS_ID_PXO_CLK = 0,
MSM_RPMRS_ID_L2_CACHE_CTL = 1,
MSM_RPMRS_ID_VDD_DIG_0 = 2,
MSM_RPMRS_ID_VDD_DIG_1 = 3,
MSM_RPMRS_ID_VDD_MEM_0 = 4,
MSM_RPMRS_ID_VDD_MEM_1 = 5,
MSM_RPMRS_ID_RPM_CTL = 6,
MSM_RPMRS_ID_LAST,
};
enum {
@@ -47,6 +45,22 @@ enum {
MSM_RPMRS_MASK_RPM_CTL_MULTI_TIER = 2,
};
enum {
MSM_RPMRS_VDD_MEM_RET_LOW = 0,
MSM_RPMRS_VDD_MEM_RET_HIGH = 1,
MSM_RPMRS_VDD_MEM_ACTIVE = 2,
MSM_RPMRS_VDD_MEM_MAX = 3,
MSM_RPMRS_VDD_MEM_LAST,
};
enum {
MSM_RPMRS_VDD_DIG_RET_LOW = 0,
MSM_RPMRS_VDD_DIG_RET_HIGH = 1,
MSM_RPMRS_VDD_DIG_ACTIVE = 2,
MSM_RPMRS_VDD_DIG_MAX = 3,
MSM_RPMRS_VDD_DIG_LAST,
};
#define MSM_RPMRS_LIMITS(_pxo, _l2, _vdd_upper_b, _vdd) { \
MSM_RPMRS_PXO_##_pxo, \
MSM_RPMRS_L2_CACHE_##_l2, \
@@ -57,6 +71,18 @@ enum {
{0}, {0}, \
}
struct msm_rpmrs_limits {
uint32_t pxo;
uint32_t l2_cache;
uint32_t vdd_mem_upper_bound;
uint32_t vdd_mem;
uint32_t vdd_dig_upper_bound;
uint32_t vdd_dig;
uint32_t latency_us[NR_CPUS];
uint32_t power[NR_CPUS];
};
struct msm_rpmrs_level {
enum msm_pm_sleep_mode sleep_mode;
struct msm_rpmrs_limits rs_limits;
@@ -67,6 +93,15 @@ struct msm_rpmrs_level {
uint32_t time_overhead_us;
};
struct msm_rpmrs_platform_data {
struct msm_rpmrs_level *levels;
unsigned int num_levels;
unsigned int vdd_mem_levels[MSM_RPMRS_VDD_MEM_LAST];
unsigned int vdd_dig_levels[MSM_RPMRS_VDD_DIG_LAST];
unsigned int vdd_mask;
unsigned int rpmrs_target_id[MSM_RPMRS_ID_LAST];
};
int msm_rpmrs_set(int ctx, struct msm_rpm_iv_pair *req, int count);
int msm_rpmrs_set_noirq(int ctx, struct msm_rpm_iv_pair *req, int count);
int msm_rpmrs_set_bits_noirq(int ctx, struct msm_rpm_iv_pair *req, int count,
@@ -112,6 +147,6 @@ int msm_rpmrs_enter_sleep(uint32_t sclk_count, struct msm_rpmrs_limits *limits,
void msm_rpmrs_exit_sleep(struct msm_rpmrs_limits *limits, bool from_idle,
bool notify_rpm, bool collapsed);
int msm_rpmrs_levels_init(struct msm_rpmrs_level *levels, int size);
int msm_rpmrs_levels_init(struct msm_rpmrs_platform_data *data);
#endif /* __ARCH_ARM_MACH_MSM_RPM_RESOURCES_H */