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qup_i2c: Fix delay when polling for write ready

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We wait for FIFO number of bytes to ensure that the
I2C state machine is not idle.

Change-Id: I24d2a22ac261bd1b53ca57a83c812c3c9f0fbdc4
Signed-off-by: Harini Jayaraman <harinij@codeaurora.org>
This commit is contained in:
Harini Jayaraman
2011-10-11 14:25:29 -06:00
parent 550aa1ab4b
commit d997b3b7a9
1 changed files with 10 additions and 3 deletions
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13
drivers/i2c/busses/i2c-qup.c
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@@ -335,8 +335,15 @@ qup_i2c_poll_writeready(struct qup_i2c_dev *dev, int rem)
else /* 1-bit delay before we check for bus busy */
udelay(dev->one_bit_t);
}
if (retries++ == 1000)
udelay(100);
if (retries++ == 1000) {
/*
* Wait for FIFO number of bytes to be absolutely sure
* that I2C write state machine is not idle. Each byte
* takes 9 clock cycles. (8 bits + 1 ack)
*/
usleep_range((dev->one_bit_t * (dev->out_fifo_sz * 9)),
(dev->one_bit_t * (dev->out_fifo_sz * 9)));
}
}
qup_print_status(dev);
return -ETIMEDOUT;
@@ -1076,7 +1083,7 @@ qup_i2c_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, dev);
dev->one_bit_t = USEC_PER_SEC/pdata->clk_freq;
dev->one_bit_t = (USEC_PER_SEC/pdata->clk_freq) + 1;
dev->pdata = pdata;
dev->clk_ctl = 0;
dev->pos = 0;