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msm: acpuclock: Move SoC-specific data into acpuclock drivers

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As part of this, hard-code any configuration values that will
not change from board-to-board inside each driver instead of
passing them through the acpuclk_soc_data struct.

Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Conflicts:

	arch/arm/mach-msm/acpuclock-8x50.c
This commit is contained in:
Matt Wagantall
2011-08-16 23:54:46 -07:00
committed by Bryan Huntsman
parent 6d9ebeef79
commit ec57f06be0
15 changed files with 121 additions and 136 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
arch/arm/mach-msm/acpuclock-7201.c
View File

@@ -75,9 +75,7 @@ static const struct pll {
struct clock_state {
struct clkctl_acpu_speed *current_speed;
struct mutex lock;
uint32_t acpu_switch_time_us;
uint32_t max_speed_delta_khz;
uint32_t vdd_switch_time_us;
unsigned long max_axi_khz;
struct clk *ebi1_clk;
};
@@ -502,7 +500,7 @@ static int acpuclk_set_vdd_level(int vdd)
writel_relaxed((1 << 7) | (vdd << 3), A11S_VDD_SVS_PLEVEL_ADDR);
mb();
udelay(drv_state.vdd_switch_time_us);
udelay(62);
if ((readl_relaxed(A11S_VDD_SVS_PLEVEL_ADDR) & 0x7) != vdd) {
pr_err("VDD set failed\n");
return -EIO;
@@ -690,7 +688,7 @@ static int acpuclk_7201_set_rate(int cpu, unsigned long rate,
/* Re-adjust lpj for the new clock speed. */
loops_per_jiffy = cur_s->lpj;
mb();
udelay(drv_state.acpu_switch_time_us);
udelay(50);
}
/* Nothing else to do for SWFI. */
@@ -1062,9 +1060,10 @@ static struct acpuclk_data acpuclk_7201_data = {
.set_rate = acpuclk_7201_set_rate,
.get_rate = acpuclk_7201_get_rate,
.power_collapse_khz = POWER_COLLAPSE_KHZ,
.switch_time_us = 50,
};
int __init acpuclk_7201_init(struct acpuclk_platform_data *clkdata)
static int __init acpuclk_7201_init(struct acpuclk_soc_data *soc_data)
{
pr_info("%s()\n", __func__);
@@ -1073,11 +1072,8 @@ int __init acpuclk_7201_init(struct acpuclk_platform_data *clkdata)
mutex_init(&drv_state.lock);
shared_pll_control_init();
acpuclk_7201_data.switch_time_us = clkdata->acpu_switch_time_us;
drv_state.acpu_switch_time_us = clkdata->acpu_switch_time_us;
drv_state.max_speed_delta_khz = clkdata->max_speed_delta_khz;
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
drv_state.max_axi_khz = clkdata->max_axi_khz;
drv_state.max_speed_delta_khz = soc_data->max_speed_delta_khz;
drv_state.max_axi_khz = soc_data->max_axi_khz;
acpu_freq_tbl_fixup();
acpuclk_7201_data.wait_for_irq_khz = find_wait_for_irq_khz();
precompute_stepping();
@@ -1094,3 +1090,27 @@ int __init acpuclk_7201_init(struct acpuclk_platform_data *clkdata)
#endif
return 0;
}
struct acpuclk_soc_data acpuclk_7201_soc_data __initdata = {
.max_speed_delta_khz = 400000,
.max_axi_khz = 160000,
.init = acpuclk_7201_init,
};
struct acpuclk_soc_data acpuclk_7x27_soc_data __initdata = {
.max_speed_delta_khz = 400000,
.max_axi_khz = 200000,
.init = acpuclk_7201_init,
};
struct acpuclk_soc_data acpuclk_7x27a_soc_data __initdata = {
.max_speed_delta_khz = 400000,
.max_axi_khz = 200000,
.init = acpuclk_7201_init,
};
struct acpuclk_soc_data acpuclk_7x27aa_soc_data __initdata = {
.max_speed_delta_khz = 504000,
.max_axi_khz = 200000,
.init = acpuclk_7201_init,
};

12
arch/arm/mach-msm/acpuclock-7x30.c
View File

@@ -56,7 +56,6 @@
struct clock_state {
struct clkctl_acpu_speed *current_speed;
struct mutex lock;
uint32_t vdd_switch_time_us;
struct clk *ebi1_clk;
};
@@ -139,7 +138,7 @@ static int acpuclk_set_acpu_vdd(struct clkctl_acpu_speed *s)
return ret;
/* Wait for voltage to stabilize. */
udelay(drv_state.vdd_switch_time_us);
udelay(62);
return 0;
}
@@ -471,15 +470,14 @@ static struct acpuclk_data acpuclk_7x30_data = {
.get_rate = acpuclk_7x30_get_rate,
.power_collapse_khz = MAX_AXI_KHZ,
.wait_for_irq_khz = MAX_AXI_KHZ,
.switch_time_us = 50,
};
int __init acpuclk_7x30_init(struct acpuclk_platform_data *clkdata)
static int __init acpuclk_7x30_init(struct acpuclk_soc_data *soc_data)
{
pr_info("%s()\n", __func__);
mutex_init(&drv_state.lock);
acpuclk_7x30_data.switch_time_us = clkdata->acpu_switch_time_us;
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
pll2_fixup();
populate_plls();
acpuclk_hw_init();
@@ -489,3 +487,7 @@ int __init acpuclk_7x30_init(struct acpuclk_platform_data *clkdata)
return 0;
}
struct acpuclk_soc_data acpuclk_7x30_soc_data __initdata = {
.init = acpuclk_7x30_init,
};

6
arch/arm/mach-msm/acpuclock-8960.c
View File

@@ -1035,7 +1035,7 @@ static struct acpuclk_data acpuclk_8960_data = {
.wait_for_irq_khz = STBY_KHZ,
};
int __init acpuclk_8960_init(struct acpuclk_platform_data *data)
static int __init acpuclk_8960_init(struct acpuclk_soc_data *soc_data)
{
if (cpu_is_msm8960()) {
scalable = scalable_8960;
@@ -1065,3 +1065,7 @@ int __init acpuclk_8960_init(struct acpuclk_platform_data *data)
return 0;
}
struct acpuclk_soc_data acpuclk_8960_soc_data __initdata = {
.init = acpuclk_8960_init,
};

49
arch/arm/mach-msm/acpuclock-8x50.c
View File

@@ -19,6 +19,7 @@
#include <linux/errno.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <linux/mfd/tps65023.h>
#include <mach/board.h>
#include <mach/msm_iomap.h>
@@ -39,6 +40,12 @@
#define SCPLL_STATUS_ADDR (MSM_SCPLL_BASE + 0x18)
#define SCPLL_FSM_CTL_EXT_ADDR (MSM_SCPLL_BASE + 0x10)
#ifdef CONFIG_QSD_SVS
#define TPS65023_MAX_DCDC1 1600
#else
#define TPS65023_MAX_DCDC1 CONFIG_QSD_PMIC_DEFAULT_DCDC1
#endif
enum {
ACPU_PLL_TCXO = -1,
ACPU_PLL_0 = 0,
@@ -155,8 +162,6 @@ static void __init cpufreq_table_init(void)
struct clock_state {
struct clkctl_acpu_speed *current_speed;
struct mutex lock;
uint32_t vdd_switch_time_us;
unsigned int max_vdd;
struct clk *ebi1_clk;
int (*acpu_set_vdd) (int mvolts);
};
@@ -238,7 +243,7 @@ static void scpll_apps_enable(bool state)
regval &= ~(0x7);
writel(regval, SCPLL_CTL_ADDR);
}
udelay(drv_state.vdd_switch_time_us);
udelay(62);
if (state)
pr_debug("PLL 3 Enabled\n");
@@ -624,7 +629,6 @@ static void __init acpu_freq_tbl_fixup(void)
skip_efuse_fixup:
iounmap(ct_csr_base);
BUG_ON(drv_state.max_vdd == 0);
/* pll0_m_val will be 36 when PLL0 is run at 235MHz
* instead of the usual 245MHz. */
@@ -633,7 +637,7 @@ skip_efuse_fixup:
PLL0_S->acpuclk_khz = 235930;
for (i = 0; acpu_freq_tbl[i].acpuclk_khz != 0; i++) {
if (acpu_freq_tbl[i].vdd > drv_state.max_vdd) {
if (acpu_freq_tbl[i].vdd > TPS65023_MAX_DCDC1) {
acpu_freq_tbl[i].acpuclk_khz = 0;
break;
}
@@ -669,20 +673,41 @@ static int __init acpu_avs_init(int (*set_vdd) (int), int khz)
}
#endif
static int qsd8x50_tps65023_set_dcdc1(int mVolts)
{
int rc = 0;
#ifdef CONFIG_QSD_SVS
rc = tps65023_set_dcdc1_level(mVolts);
/*
* By default the TPS65023 will be initialized to 1.225V.
* So we can safely switch to any frequency within this
* voltage even if the device is not probed/ready.
*/
if (rc == -ENODEV && mVolts <= CONFIG_QSD_PMIC_DEFAULT_DCDC1)
rc = 0;
#else
/*
* Disallow frequencies not supported in the default PMIC
* output voltage.
*/
if (mVolts > CONFIG_QSD_PMIC_DEFAULT_DCDC1)
rc = -EFAULT;
#endif
return rc;
}
static struct acpuclk_data acpuclk_8x50_data = {
.set_rate = acpuclk_8x50_set_rate,
.get_rate = acpuclk_8x50_get_rate,
.power_collapse_khz = POWER_COLLAPSE_KHZ,
.wait_for_irq_khz = WAIT_FOR_IRQ_KHZ,
.switch_time_us = 20,
};
int __init acpuclk_8x50_init(struct acpuclk_platform_data *clkdata)
static int __init acpuclk_8x50_init(struct acpuclk_soc_data *soc_data)
{
mutex_init(&drv_state.lock);
acpuclk_8x50_data.switch_time_us = clkdata->acpu_switch_time_us;
drv_state.vdd_switch_time_us = clkdata->vdd_switch_time_us;
drv_state.max_vdd = clkdata->max_vdd;
drv_state.acpu_set_vdd = clkdata->acpu_set_vdd;
drv_state.acpu_set_vdd = qsd8x50_tps65023_set_dcdc1;
drv_state.ebi1_clk = clk_get(NULL, "ebi1_acpu_clk");
BUG_ON(IS_ERR(drv_state.ebi1_clk));
@@ -710,3 +735,7 @@ int __init acpuclk_8x50_init(struct acpuclk_platform_data *clkdata)
#endif
return 0;
}
struct acpuclk_soc_data acpuclk_8x50_soc_data __initdata = {
.init = acpuclk_8x50_init,
};

6
arch/arm/mach-msm/acpuclock-8x60.c
View File

@@ -920,7 +920,7 @@ static struct acpuclk_data acpuclk_8x60_data = {
.wait_for_irq_khz = MAX_AXI,
};
int __init acpuclk_8x60_init(struct acpuclk_platform_data *clkdata)
static int __init acpuclk_8x60_init(struct acpuclk_soc_data *soc_data)
{
unsigned int max_cpu_khz;
int cpu;
@@ -948,3 +948,7 @@ int __init acpuclk_8x60_init(struct acpuclk_platform_data *clkdata)
return 0;
}
struct acpuclk_soc_data acpuclk_8x60_soc_data __initdata = {
.init = acpuclk_8x60_init,
};

6
arch/arm/mach-msm/acpuclock-fsm9xxx.c
View File

@@ -40,9 +40,13 @@ static struct acpuclk_data acpuclk_9xxx_data = {
.get_rate = acpuclk_9xxx_get_rate,
};
int __init acpuclk_9xxx_init(struct acpuclk_platform_data *clkdata)
static int __init acpuclk_9xxx_init(struct acpuclk_soc_data *soc_data)
{
acpuclk_register(&acpuclk_9xxx_data);
pr_info("ACPU running at %lu KHz\n", acpuclk_get_rate(0));
return 0;
}
struct acpuclk_soc_data acpuclk_9xxx_soc_data __initdata = {
.init = acpuclk_9xxx_init,
};

6
arch/arm/mach-msm/acpuclock.c
View File

@@ -57,14 +57,14 @@ void __init acpuclk_register(struct acpuclk_data *data)
acpuclk_data = data;
}
int __init acpuclk_init(struct acpuclk_platform_data *pdata)
int __init acpuclk_init(struct acpuclk_soc_data *soc_data)
{
int rc;
if (!pdata->init)
if (!soc_data->init)
return -EINVAL;
rc = pdata->init(pdata);
rc = soc_data->init(soc_data);
if (rc)
return rc;

28
arch/arm/mach-msm/acpuclock.h
View File

@@ -31,16 +31,12 @@ enum setrate_reason {
};
/**
* struct acpuclk_platform_data - Platform data for acpuclk_init()
* struct acpuclk_soc_data - SoC data for acpuclk_init()
*/
struct acpuclk_platform_data {
uint32_t acpu_switch_time_us;
struct acpuclk_soc_data {
unsigned long max_speed_delta_khz;
uint32_t vdd_switch_time_us;
unsigned int max_axi_khz;
unsigned int max_vdd;
int (*acpu_set_vdd) (int mvolts);
int (*init)(struct acpuclk_platform_data *);
int (*init)(struct acpuclk_soc_data *);
};
/**
@@ -100,14 +96,16 @@ void acpuclk_register(struct acpuclk_data *data);
*
* Return 0 for success.
*/
int acpuclk_init(struct acpuclk_platform_data *);
int acpuclk_init(struct acpuclk_soc_data *);
/* SoC-specific acpuclock initialization functions. */
int acpuclk_7201_init(struct acpuclk_platform_data *);
int acpuclk_7x30_init(struct acpuclk_platform_data *);
int acpuclk_8x50_init(struct acpuclk_platform_data *);
int acpuclk_8x60_init(struct acpuclk_platform_data *);
int acpuclk_8960_init(struct acpuclk_platform_data *);
int acpuclk_9xxx_init(struct acpuclk_platform_data *);
extern struct acpuclk_soc_data acpuclk_7x27_soc_data;
extern struct acpuclk_soc_data acpuclk_7x27a_soc_data;
extern struct acpuclk_soc_data acpuclk_7x27aa_soc_data;
extern struct acpuclk_soc_data acpuclk_7201_soc_data;
extern struct acpuclk_soc_data acpuclk_7x30_soc_data;
extern struct acpuclk_soc_data acpuclk_8x50_soc_data;
extern struct acpuclk_soc_data acpuclk_8x60_soc_data;
extern struct acpuclk_soc_data acpuclk_8960_soc_data;
extern struct acpuclk_soc_data acpuclk_9xxx_soc_data;
#endif

8
arch/arm/mach-msm/board-fsm9xxx.c
View File

@@ -835,12 +835,6 @@ static struct platform_device *devices[] __initdata = {
&fsm_xo_device,
};
static struct acpuclk_platform_data fsm9xxx_clock_data __initdata = {
.acpu_switch_time_us = 50,
.vdd_switch_time_us = 62,
.init = acpuclk_9xxx_init,
};
static void __init fsm9xxx_init_irq(void)
{
msm_init_irq();
@@ -879,7 +873,7 @@ static void __init fsm9xxx_init(void)
pr_err("%s: socinfo_init() failed!\n",
__func__);
acpuclk_init(&fsm9xxx_clock_data);
acpuclk_init(&acpuclk_9xxx_soc_data);
regulator_has_full_constraints();

15
arch/arm/mach-msm/board-msm7x27.c
View File

@@ -1489,14 +1489,6 @@ static void __init msm7x2x_init_irq(void)
msm_init_irq();
}
static struct acpuclk_platform_data msm7x2x_clock_data __initdata = {
.acpu_switch_time_us = 50,
.max_speed_delta_khz = 400000,
.vdd_switch_time_us = 62,
.max_axi_khz = 160000,
.init = acpuclk_7201_init,
};
void msm_serial_debug_init(unsigned int base, int irq,
struct device *clk_device, int signal_irq);
@@ -1892,11 +1884,10 @@ static void __init msm7x2x_init(void)
}
}
#endif
if (cpu_is_msm7x27())
msm7x2x_clock_data.max_axi_khz = 200000;
acpuclk_init(&msm7x2x_clock_data);
acpuclk_init(&acpuclk_7x27_soc_data);
else
acpuclk_init(&acpuclk_7201_soc_data);
usb_mpp_init();

8
arch/arm/mach-msm/board-msm7x30.c
View File

@@ -5524,12 +5524,6 @@ static struct msm_i2c_ssbi_platform_data msm_i2c_ssbi7_pdata = {
};
#endif
static struct acpuclk_platform_data msm7x30_clock_data __initdata = {
.acpu_switch_time_us = 50,
.vdd_switch_time_us = 62,
.init = acpuclk_7x30_init,
};
static void __init msm7x30_init_irq(void)
{
msm_init_irq();
@@ -6955,7 +6949,7 @@ static void __init msm7x30_init(void)
msm7x30_init_uart2();
#endif
msm_spm_init(&msm_spm_data, 1);
acpuclk_init(&msm7x30_clock_data);
acpuclk_init(&acpuclk_7x30_soc_data);
if (machine_is_msm7x30_surf() || machine_is_msm7x30_fluid())
msm7x30_cfg_smsc911x();

10
arch/arm/mach-msm/board-msm8960.c
View File

@@ -1931,12 +1931,6 @@ static int __init gpiomux_init(void)
return 0;
}
static struct acpuclk_platform_data msm8960_acpuclk_data __initdata = {
.acpu_switch_time_us = 0,
.vdd_switch_time_us = 0,
.init = acpuclk_8960_init,
};
#define MSM_SHARED_RAM_PHYS 0x80000000
static struct pm8921_adc_amux pm8921_adc_channels_data[] = {
@@ -3512,7 +3506,7 @@ static void __init msm8960_sim_init(void)
platform_add_devices(common_devices, ARRAY_SIZE(common_devices));
pm8921_gpio_mpp_init();
platform_add_devices(sim_devices, ARRAY_SIZE(sim_devices));
acpuclk_init(&msm8960_acpuclk_data);
acpuclk_init(&acpuclk_8960_soc_data);
msm8960_device_qup_spi_gsbi1.dev.platform_data =
&msm8960_qup_spi_gsbi1_pdata;
@@ -3603,7 +3597,7 @@ static void __init msm8960_cdp_init(void)
platform_add_devices(cdp_devices, ARRAY_SIZE(cdp_devices));
msm8960_init_cam();
msm8960_init_mmc();
acpuclk_init(&msm8960_acpuclk_data);
acpuclk_init(&acpuclk_8960_soc_data);
register_i2c_devices();
msm8960_wcnss_init();
msm_fb_add_devices();

6
arch/arm/mach-msm/board-msm8x60.c
View File

@@ -398,10 +398,6 @@ static struct msm_spm_platform_data msm_spm_data[] __initdata = {
},
};
static struct acpuclk_platform_data msm8x60_acpuclk_data __initdata = {
.init = acpuclk_8x60_init,
};
/*
* Consumer specific regulator names:
* regulator name consumer dev_name
@@ -10060,7 +10056,7 @@ static void __init msm8x60_init(struct msm_board_data *board_data)
platform_add_devices(early_devices, ARRAY_SIZE(early_devices));
/* CPU frequency control is not supported on simulated targets. */
if (!machine_is_msm8x60_rumi3() && !machine_is_msm8x60_sim())
acpuclk_init(&msm8x60_acpuclk_data);
acpuclk_init(&acpuclk_8x60_soc_data);
/* No EBI2 on 8660 charm targets */
if (!machine_is_msm8x60_fusion() && !machine_is_msm8x60_fusn_ffa())

40
arch/arm/mach-msm/board-qsd8x50.c
View File

@@ -20,7 +20,6 @@
#include <linux/i2c.h>
#include <linux/spi/spi.h>
#include <linux/delay.h>
#include <linux/mfd/tps65023.h>
#include <linux/bma150.h>
#include <linux/power_supply.h>
#include <linux/clk.h>
@@ -1213,43 +1212,6 @@ static struct msm_tsif_platform_data tsif_platform_data = {
#endif /* defined(CONFIG_TSIF) || defined(CONFIG_TSIF_MODULE) */
/* TSIF end */
#ifdef CONFIG_QSD_SVS
#define TPS65023_MAX_DCDC1 1600
#else
#define TPS65023_MAX_DCDC1 CONFIG_QSD_PMIC_DEFAULT_DCDC1
#endif
static int qsd8x50_tps65023_set_dcdc1(int mVolts)
{
int rc = 0;
#ifdef CONFIG_QSD_SVS
rc = tps65023_set_dcdc1_level(mVolts);
/* By default the TPS65023 will be initialized to 1.225V.
* So we can safely switch to any frequency within this
* voltage even if the device is not probed/ready.
*/
if (rc == -ENODEV && mVolts <= CONFIG_QSD_PMIC_DEFAULT_DCDC1)
rc = 0;
#else
/* Disallow frequencies not supported in the default PMIC
* output voltage.
*/
if (mVolts > CONFIG_QSD_PMIC_DEFAULT_DCDC1)
rc = -EFAULT;
#endif
return rc;
}
static struct acpuclk_platform_data qsd8x50_clock_data __initdata = {
.acpu_switch_time_us = 20,
.max_speed_delta_khz = 256000,
.vdd_switch_time_us = 62,
.max_vdd = TPS65023_MAX_DCDC1,
.acpu_set_vdd = qsd8x50_tps65023_set_dcdc1,
.init = acpuclk_8x50_init,
};
static void touchpad_gpio_release(void)
{
gpio_free(TOUCHPAD_IRQ);
@@ -2444,7 +2406,7 @@ static void __init qsd8x50_init(void)
__func__);
msm_clock_init(&qds8x50_clock_init_data);
qsd8x50_cfg_smc91x();
acpuclk_init(&qsd8x50_clock_data);
acpuclk_init(&acpuclk_8x50_soc_data);
msm_hsusb_pdata.swfi_latency =
msm_pm_data

17
arch/arm/mach-msm/devices-msm7x27a.c
View File

@@ -695,24 +695,17 @@ struct platform_device asoc_msm_dai1 = {
.id = 0,
};
static struct acpuclk_platform_data msm7x2x_clock_data __initdata = {
.acpu_switch_time_us = 50,
.max_speed_delta_khz = 400000,
.vdd_switch_time_us = 62,
.max_axi_khz = 200000,
.init = acpuclk_7201_init,
};
int __init msm7x2x_misc_init(void)
{
if (socinfo_init() < 0)
pr_err("%s: socinfo_init() failed!\n", __func__);
if (cpu_is_msm7x27aa())
msm7x2x_clock_data.max_speed_delta_khz = 504000;
msm_clock_init(&msm7x27a_clock_init_data);
acpuclk_init(&msm7x2x_clock_data);
if (cpu_is_msm7x27aa())
acpuclk_init(&acpuclk_7x27aa_soc_data);
else
acpuclk_init(&acpuclk_7x27a_soc_data);
return 0;
}