Merge Upstream's stable 3.0.21 branch into msm-3.0
This consists 814 commits and some merge conflicts.
The merge conflicts are because of some local changes to
msm-3.0 as well as some conflicts between google's tree and
the upstream tree.
Conflicts:
arch/arm/kernel/head.S
drivers/bluetooth/ath3k.c
drivers/bluetooth/btusb.c
drivers/mmc/core/core.c
drivers/tty/serial/serial_core.c
drivers/usb/host/ehci-hub.c
drivers/usb/serial/qcserial.c
fs/namespace.c
fs/proc/base.c
Change-Id: I62e2edbe213f84915e27f8cd6e4f6ce23db22a21
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
When request for scaling bus fails, log error message.
Also do not return error on failing to service the
bus scaling request.
Change-Id: Ia893b3fe1b2b7b644ac2f44ed81fb2e33d451b4b
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Remove config_ce_engine. This is already being done in
probe ce callback function.
Change-Id: I5d4dea54b4b28258c2ed0ab2b0e65fd469fb09e7
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Add support for CE block size to 64 bytes on MDM9x15 target.
The modem on MDM9x15 did not support 64byte crci on data mover till now.
Change-Id: I4ea08f9e6097a17280763b9c0ca063de19a5c0f4
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
Add bus bandwidth request in crypto driver modules.
Add bus scaling request information to platform data files.
Currently the support for bandwidth request is enabled and tested on
msm8960 only.
Change-Id: I77edb827b1633218405cecf3a494c13b7b982c05
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
commit 274252862f386b7868f35bf5ceaa5391a8ccfdf3 upstream.
This was broken by commit 7759995c75 (yes,
myself). The basic problem here is since the digest state is only saved
after the last chunk, the state array is only valid when handling the
first chunk of the next buffer. Broken since linux-3.0.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This patch fixes 2 issues that was causing cipher operation
failure
(1) Status register reflecting an SW_ERR (ACCESS_VIOL bit set)
Status register needed to be cleared initially before
starting any operation
(2) Occasional failure observed in some cipher operation(s)
(encryption and/or decryption) for modes that require
reading in the CNTR IV register values after an
operation is complete.
These failures show up when doing a 3DES-CBC operation.
But there is potential for it to raise its head when doing
DES-CBC, AES-CBC or AES_XTS modes as well (since all of this
modes require reading in the CNTR IV register).
The CNTR IV register was being read after writing data to
the IN FIFO. There is a potential for encryption (or decryption)
operations to not have completed fully on all the data in the FIFO
before the IV register is read, resulting in incorrect IV value.
The fix is to read the CNTR IV register after the operation
is guranteed to have completed sucessfully. This is done after
reading data out of DATA OUT FIFO.
Change-Id: Icef0d544ecb463cea4be978c3d2809049b92da05
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
-add new clock - ce3_core_src_clk to 8064 target.
-ce3_p_clk and ce3_core_clk are derived from ce3_core_src_clk.
-ce3 core src clock expects that the driver(qce40) set the clock
rate before the clock is enabled.
-set ce3_core_src_clk rate to 100mhz.
-add new DMA channels for APQ8064.
Change-Id: I3f0897b43d5d58a60a1df4f61a241868b8b9a926
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
This change makes the configuration of ce register target
agnostic.
-On targets where the register is xpu protected, a 0 value
is returned and the register has already been configured.
-On targets when a non-zero value is returned, the driver
configures the register.
Change-Id: Icd1888d6d87d19c52952c27d277bb4b787d72a93
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
Added checks for
-Initializations of alg and mode values in qcedev.
-Buffer overflow in qcrypto.
CRs-fixed: 313705
Change-Id: I20e285679af4967f989427ea50eb5a287df28cca
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
Fixed compilation warnings when PMEM is not defined.
Change-Id: Ifdb7c10fabaa2e05737497dbed89457906e8f459
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
Added the configuration settings for supporting MSM9615.
-MSM9615 does not have TZ(trust zone) hence DM configurations are done
when checking the target.
-MSM9615 does not support PMEM and hence pmem related functions are
featurized under PMEM feature - CONFIG_ANDROID_PMEM
- Added changes to Kconfig to have QCE40 built for MSM9615.
Change-Id: If2946463cc1869f5b0014c68d8e19816cedc8a3a
Signed-off-by: Ramesh Masavarapu <rameshm@codeaurora.org>
For some large (32KB+) packets for AES CCM algorithms,
depending on assoc data length, padding, actual data,
the ce_in_dst_desc, ce_out_src_desc are found to be
incorrect. This patch clears up the supports for 32KB+
and makes it more generic (not cipher/hash specific)
Relocate where the following are being processed
for 32KB+ packets
- ce_in_dst_desc from chain_sg_buffer_in() to ce_in_final()
- ce_out_src_desc from chain_sg_buffer_out() to ce_out_final()
With the above the AES-CCM algorithms passes all scenarios.
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
This patch clears up the supports for 32KB+ packet
and makes it more generic (not cipher/hash specific)
This is done by relocating where the following are being
processed for 32KB+ packets
- ce_in_dst_desc: from chain_sg_buffer_in() to ce_in_final()
- ce_out_src_desc: from chain_sg_buffer_out() to ce_out_final()
Furthermore, the descriptor length for the last (single or
multiple descriptors) entry of the above mentioned descriptor
lists is not set correctly.
With the above fixes, f8, f9 and AEAD operations (on supported
targets) is functioning properly.
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Adds support for CE block size larger than 16 bytes
by setting appropriate bits in CRYPTO_CONFIG register.
NOTE: This bits are functional in rev 4.2 and higher
of the CE hardware. Setting the bits in 4.0 HW does not
do anything.
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
CRYPTO_CONFIG is configured by secure code and the register
is XPU protected. Writing to this register has no effect.
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
Remove direct access to CRYPTO register when configuring
for a cipher or authentication operation. Create DM commands
and command pointer list to configure registers.
This change is needed to allow multiple clients from different
execution environment use the same CE1 hardware. DM synchronizes
the request by blocking any access to the CE hardware by any
other pair of DM channels (used by other EE clients)
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
The crci conflict checking code was designed for a system where a crci's
mux could be changed at runtime. In reality, our chips configure these
statically, so it is not necessary.
Signed-off-by: Jeff Ohlstein <johlstei@codeaurora.org>
Rename the clocks per the new naming convention under which
similarly named clocks are distinguished between using their
associated device's name and ID.
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>
- Create a flat directory structure for hw crypto modules
that includes all source and all header files.
- Remove msm/inc directory
- Relocate qcedev.h header file to include/linux
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
- Define a new handle data structure "qcedev_handle"
This structures holds internal context data
"qcedev_sha_ctxt" and pointer to "qcedev_control"
- Allocate memory for the hanlde, each time a client
opens the device. Thereby, ensuring a unique handle
for each client.
- Use the new handle for each operation (instead of
qcedev_control pointer)
- Remove the internal sha context data structure
"qcedev_sha_ctx" from the "qcedev_sha_op_req".
This is now correctly tied to each handle.
Signed-off-by: Mona Hossain <mhossain@codeaurora.org>
setkey allocates 16 bytes (CAAM_CMD_SZ *
DESC_AEAD_SHARED_TEXT_LEN) shy of what is needed to
store the shared descriptor, resulting in memory
corruption. Fix this.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The registration of an ap device will be skipped, if the device type
probing fails.
Add names of current crypto adapters to the Kconfig help.
Signed-off-by: Holger Dengler <hd@linux.vnet.ibm.com>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
* git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (45 commits)
crypto: caam - add support for sha512 variants of existing AEAD algorithms
crypto: caam - remove unused authkeylen from caam_ctx
crypto: caam - fix decryption shared vs. non-shared key setting
crypto: caam - platform_bus_type migration
crypto: aesni-intel - fix aesni build on i386
crypto: aesni-intel - Merge with fpu.ko
crypto: mv_cesa - make count_sgs() null-pointer proof
crypto: mv_cesa - copy remaining bytes to SRAM only when needed
crypto: mv_cesa - move digest state initialisation to a better place
crypto: mv_cesa - fill inner/outer IV fields only in HMAC case
crypto: mv_cesa - refactor copy_src_to_buf()
crypto: mv_cesa - no need to save digest state after the last chunk
crypto: mv_cesa - print a warning when registration of AES algos fail
crypto: mv_cesa - drop this call to mv_hash_final from mv_hash_finup
crypto: mv_cesa - the descriptor pointer register needs to be set just once
crypto: mv_cesa - use ablkcipher_request_cast instead of the manual container_of
crypto: caam - fix printk recursion for long error texts
crypto: caam - remove unused keylen from session context
hwrng: amd - enable AMD hw rnd driver for Maple PPC boards
hwrng: amd - manage resource allocation
...
In doing so, sha512 sized keys would not fit with the current
descriptor inlining mechanism, so we now calculate whether keys
should be referenced instead by pointers in the shared descriptor.
also, use symbols for descriptor text lengths, and, ahem, unmap and
free key i/o memory in cra_exit.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Key sharing is enabled by default in the shared descriptor.
Using CBC decrypt, AES has to alter the key in order to decrypt.
During high traffic decryption rates, i.e, when sharing starts to
take place, we need to use a different OPERATION option to tell AES
that the key was already altered by the PRIOR descriptor - we need
the following kind of logic:
if ( shared )
operation where AES uses decryption key (DK=1)
else
operation where AES uses encryption key (DK=0)
this patch implements this logic using a conditional and
a non-conditional local jump within the decryption job
descriptor.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This also makes the dummy scatterlist in mv_hash_final() needless, so
drop it.
XXX: should this routine be made pulicly available? There are probably
other users with their own implementations.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
On one hand, the digest state registers need to be set only when
actually using the crypto engine. On the other hand, there is a check
for ctx->first_hash in mv_process_hash_current() already, so use that.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The main goal was to have it not do anything when a zero len parameter
was being passed (which could lead to a null pointer dereference, as in
this case p->src_sg is null, either). Using the min() macro, the lower
part of the loop gets simpler, too.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
The code in mv_hash_final is actually a superset of mv_hash_finup's
body. Since the driver works fine without, drop it.
Signed-off-by: Phil Sutter <phil.sutter@viprinet.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
during recent descriptor development, an Invalid Sequence Command
error triggered a:
BUG: recent printk recursion!
due to insufficient memory allocated for the error text.
The Invalid Sequence Command error text is the longest.
The length of the maximum error string is computed as
the sum of:
"DECO: ": 6
"jump tgt desc idx 255: ": 23
Invalid Sequence Command text: 272
zero termination character: 1
i.e, 302 characters.
Define this maximum error string length in error.h and fix
caam_jr_strstatus callsites.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
