Harsh Vardhan Dwivedi d9fa3d511c msm: kgsl: Use default hardcoded value for CP's ROQ queue size ...

The command processor FIFO depth is different for A330 and A2xx GPUs.
It is best to let each GPU use the default value which is hardcoded in
the respective GPU.

Change-Id: I5db6a1c0671d0ad4253dcad7f386429d78a4bd62
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>

2012-04-19 13:24:26 -06:00

..

drm

drm/i915: handle 3rd pipe

2012-02-13 11:06:09 -08:00

ion

gpu: ion: Add check for addr out of bounds

2012-04-14 07:12:04 -07:00

msm

msm: kgsl: Use default hardcoded value for CP's ROQ queue size

2012-04-19 13:24:26 -06:00

stub

…

vga

Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

2011-05-24 12:06:40 -07:00

Makefile

Initial Contribution

2011-10-03 09:57:10 -07:00