msm: kgsl: Use default hardcoded value for CP's ROQ queue size

The command processor FIFO depth is different for A330 and A2xx GPUs.
It is best to let each GPU use the default value which is hardcoded in
the respective GPU.

Change-Id: I5db6a1c0671d0ad4253dcad7f386429d78a4bd62
Signed-off-by: Harsh Vardhan Dwivedi <hdwivedi@codeaurora.org>

drivers/gpu/msm/adreno_ringbuffer.c

@@ -339,7 +339,6 @@ int adreno_ringbuffer_start(struct adreno_ringbuffer *rb, unsigned int init_ram)
 	if (status != 0)
 		return status;
 
-	adreno_regwrite(device, REG_CP_QUEUE_THRESHOLDS, 0x000C0804);
 
 	rb->rptr = 0;
 	rb->wptr = 0;