fb fix, ts fix, flash ttfs experemental
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311
Start_WM/test6/inc/GFVxScr.h
Executable file
311
Start_WM/test6/inc/GFVxScr.h
Executable file
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/* Copyright (c) 2006 NVIDIA Corporation. All rights reserved.
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*
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* NVIDIA Corporation and its licensors retain all intellectual property
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* and proprietary rights in and to this software, related documentation
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* and any modifications thereto. Any use, reproduction, disclosure or
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* distribution of this software and related documentation without an
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* express license agreement from NVIDIA Corporation is strictly prohibited.
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*/
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#if !defined (__GFVXSCR_INC__)
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#define __GFVXSCR_INC__
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/** VxAPI GFVXVIPINFO::Flag flagbit: 8-bit/clock video data.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_PARALLEL_INPUT 0x00000001
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/** VxAPI GFVXVIPINFO::Flag flagbit: Serial input.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_SERIAL_INPUT 0x00000002
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/** VxAPI GFVXVIPINFO::Flag flagbit: VHSYNC and VVSYNC in the data stream.
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If this flag is set, vertical and horizontal sync for the camera picture
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is contained in the data stream going into the data port of the VIP.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_HVSYNC_IN_STREAM 0x00000004
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/** VxAPI GFVXVIPINFO::Flag flagbit: Camera VHSYNC asserted by external signal.
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If this flag is set, vertical and horizontal sync for the camera picture
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is asserted to the GoForce chip by external signals, usually coming from
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the camera chip.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_EXTERNAL_VHSYNC 0x00000008
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/** VxAPI GFVXVIPINFO::Flag flagbit: Camera VHSYNC generated by GoForce chip.
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If this flag is set, vertical and horizontal sync is generated by the
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GoForce chip, and not contained in the data stream. The following members
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of GFVXVIPINFO have to be set to define the timing:
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- GFVXVIPINFO::VHPulseWidth
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- GFVXVIPINFO::VHPulsePeriod
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- GFVXVIPINFO::VVPulseWidth
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- GFVXVIPINFO::VVPulsePeriod
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- GFVXVIPINFO::VVDelay
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_INTERNAL_VHSYNC 0x00000010
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/** VxAPI GFVXVIPINFO::Flag flagbit: VCLK generated externally.
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If this flag is set, camera VCLK is provided from an external source,
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and VLCK will be selected as clock source for VI module.
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@see GFVXVIPINFO, GFVxVIPSetVIP(), GFVX_VIP_EXTERNAL_VCLK_PRESERVE_CLKSEL
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*/
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#define GFVX_VIP_EXTERNAL_VCLK 0x00000020
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/** VxAPI GFVXVIPINFO::Flag flagbit: VCLK generated by GoForce chip.
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If this flag is set, camera VCLK is provided by the GoForce chip.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_INTERNAL_VCLK 0x00000040
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/** VxAPI GFVXVIPINFO::Flag flagbit: Detect field 0 or 1, will not work for
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internal VHSYNC (#GFVX_VIP_INTERNAL_VHSYNC).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_DETECT_FIELD 0x00000080
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/** VxAPI GFVXVIPINFO::Flag flagbit: Horizontal flip.
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Flip VIP image horizontally.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_RGB_H_FLIP 0x00000100
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/** VxAPI GFVXVIPINFO::Flag flagbit: Vertical flip.
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Flip VIP image vertically.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_RGB_V_FLIP 0x00000200
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/** VxAPI GFVXVIPINFO::Flag flagbit: CPU feeds image to VIP.
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This flag indicates to the VIP, that image data is fed from the
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host interface.
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@see GFVXVIPINFO, GFVxVIPSetVIP(), GFVxVIPFeedImage()
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*/
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#define GFVX_VIP_HOST_IMAGE 0x00000400
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/** VxAPI GFVXVIPINFO::Flag flagbit: Change the default timing for VHSYNC and
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VCLK. If this flag is set, VHSYNC and VCLK timing characteristics such as
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polarity, active edge, serial frame polarity, size, field info are
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overridden with GFVxVIPSetVIP() by the parameters passed in
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GFVXVIPINFO::NewTiming.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_CHANGE_DEFAULT_TIMING 0x00000800
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/** VxAPI GFVXVIPINFO::Flag flagbit: Camera master clock provided by GoForce
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chip. When this flag is set, GFVXVIPINFO::MClockFreq must be set to the
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ideal clock which the camera wants. Internally the best matching frequency
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is provided to the camera.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_ASK_FOR_MCLOCK 0x00001000
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/** VxAPI GFVXVIPINFO::Flag flagbit: VIP input type A interface.
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@see GFVXVIPINFO, GFVxVIPSetVIP(), pageVxOverview2
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*/
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#define GFVX_VIP_TYPE_A 0x00002000
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/** VxAPI GFVXVIPINFO::Flag flagbit: VIP input type B interface.
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@see GFVXVIPINFO, GFVxVIPSetVIP(), pageVxOverview2
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*/
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#define GFVX_VIP_TYPE_B 0x00004000
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/** VxAPI GFVXVIPINFO::Flag flagbit: VIP input type C interface.
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@see GFVXVIPINFO, GFVxVIPSetVIP(), pageVxOverview2
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*/
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#define GFVX_VIP_TYPE_C 0x00008000
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/** VxAPI GFVXVIPINFO::Flag flagbit: Camera is running at type C interface
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and do not remove the 0xFF, 0x02 sequence.
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@see GFVXVIPINFO, GFVxVIPSetVIP(), pageVxOverview2
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*/
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#define GFVX_VIP_TYPE_C_RAW 0x00010000
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/** VxAPI GFVXVIPINFO::Flag flagbit: Enable destination byte swap for YUV/RGB
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data written to preview surface.
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This flag enables byte swap for 32 bit words of data coming from VIP and
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going to a target RGB or YUV422 surface. The sequence of 4 byte groups in
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<code>(LSB)b0 b1 b2 b3(MSB)</code> order is swapped to
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<code>(LSB)b1 b0 b3 b2(MSB)</code>.
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This flag only affects data written to a preview surface, i.e. VIP image
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capture enabled with GFVxVIPSetVIP() and GFVxVIPUpdate(). It does not
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affect raw data going to the JPEG/MPEG encoder.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_DEST_BYTE_SWAP 0x00020000
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/** VxAPI GFVXVIPINFO::Flag flagbit: VI output without rotation
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Rotate VIP image 0 degree
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@version SC15 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_ROTATE_0 0x00040000
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/** VxAPI GFVXVIPINFO::Flag flagbit: VI output with 90 degree rotation
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Rotate VIP image 90 degree
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@version SC15 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_ROTATE_90 0x00080000
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/** VxAPI GFVXVIPINFO::Flag flagbit: VI output with 180 degree rotation
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Rotate VIP image 180 degree
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@version SC15 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_ROTATE_180 0x00100000
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/** VxAPI GFVXVIPINFO::Flag flagbit: VI output with 270 degree rotation
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Rotate VIP image 270 degree
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@version SC15 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_ROTATE_270 0x00200000
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/** VxAPI GFVXVIPINFO::Flag flagbit: RGB565 input to EPP.
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@todo clarify
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@version SC15 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_RGB565 0x00400000
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/** VxAPI GFVXVIPINFO::Flag flagbit: RGB888 input to EPP.
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@todo clarify
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@version SC15 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_RGB888 0x00800000
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/** VxAPI GFVXVIPINFO::Flag flagbit: RGB444 input to EPP.
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@todo clarify
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@version SC15 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_RGB444 0x01000000
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/** VxAPI GFVXVIPINFO::Flag flagbit: Preserve VI clock source but enable external VLCK pad.
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This flag can be used in combination with GFVX_VIP_EXTERNAL_VCLK to enable
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an external clock on VLCK, but keep the VI module clocksource.
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@version SC15 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP(), GFVX_VIP_EXTERNAL_VCLK
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*/
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#define GFVX_VIP_EXTERNAL_VCLK_PRESERVE_CLKSEL 0x02000000
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/** VxAPI GFVXVIPINFO::Flag flagbit: VIP input type D interface.
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@version SC17 and above
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_TYPE_D 0x04000000
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#define GFVX_VIP_CSI_ENABLE 0x08000000
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/** VxAPI GFVXVIPINFO::Flag flagbit: Bypass any manipulation on internal master
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clock generation output pin.
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This flag is mutually exclusive to #GFVX_VIP_PRE_GENERATE_MCLOCK and
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#GFVX_VIP_ASK_FOR_MCLOCK.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_BYPASS_MCLOCK_PIN 0x20000000
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/** VxAPI GFVXVIPINFO::Flag flagbit: Bypass any manipulation on VCLK, VHSYNC,
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and VID[7:0] pins.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_BYPASS_NON_MCLOCK_PINS 0x40000000
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/** VxAPI GFVXVIPINFO::Flag flagbit: Pre-generation of master clock.
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Useful for scanning the I2C bus for a camera.
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_PRE_GENERATE_MCLOCK 0x80000000
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/**
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Bypass ISP mode.
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*/
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#define GFVX_VIP_BYPASS_ISP 0x10000000
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: Parallel data latched at falling edge
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of VCLK (default is rising edge).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_PDL_FALLING_VCLK 0x00000001
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: Serial data lacthed at rising edge of
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VCLK (default is falling edge).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_SDL_RISING_VCLK 0x00000001
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: VHSYNC active low (default is active
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high).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_VHSYNC_ACTIVE_LOW 0x00000002
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: VVSYNC active low (default is active
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high).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_VVSYNC_ACTIVE_LOW 0x00000004
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: VHSYNC active leading edge (default
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is trailing edge).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_VHSYNC_ACTIVE_EDGE_LEAD 0x00000008
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: VVSYNC active leading edge (default
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is trailing edge).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_VVSYNC_ACTIVE_EDGE_LEAD 0x00000010
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: Serial video frame sync active low,
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falling edge indicates start of data frame (default is active high, rising
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edge indicates start of data frame).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_SFRAME_ACTIVE_LOW 0x00000020
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: Serial video input is 16 bit per
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frame (default is 8 bit per frame).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_SFRAME_SIZE_16 0x00000040
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: Field 0 is bottom/even field
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(default is top/odd field).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_FILED_0_BOTTOM 0x00000080
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: VCLK output from GoForce chip active
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low (default is active high).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_VCLK_OUTPUT_ACTIVE_LOW 0x00000100
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#define GFVX_VIP_VHSYNC_ACTIVE_LOW_RESET 0x00000200
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: VVSYNC reset active low (default is active
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high).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#define GFVX_VIP_VVSYNC_ACTIVE_LOW_RESET 0x00000400
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/** VxAPI GFVXVIPINFO::NewTiming flagbit: VHSYNC reset active leading edge (default
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is trailing edge).
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@see GFVXVIPINFO, GFVxVIPSetVIP()
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*/
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#endif
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